52 #ifndef __STM32F769xx_H 53 #define __STM32F769xx_H 197 #define __CM7_REV 0x0100U 198 #define __MPU_PRESENT 1 199 #define __NVIC_PRIO_BITS 4 200 #define __Vendor_SysTickConfig 0 201 #define __FPU_PRESENT 1 202 #define __ICACHE_PRESENT 1 203 #define __DCACHE_PRESENT 1 204 #include "core_cm7.h" 207 #include "system_stm32f7xx.h" 299 uint32_t RESERVED0[88];
302 uint32_t RESERVED1[12];
311 uint32_t RESERVED5[8];
481 uint32_t RESERVED[236];
501 uint32_t RESERVED0[2];
516 uint32_t RESERVED2[40];
522 uint32_t RESERVED3[14];
525 uint32_t RESERVED4[5];
527 uint32_t RESERVED5[10];
530 uint32_t RESERVED6[10];
532 uint32_t RESERVED7[334];
544 uint32_t RESERVED9[565];
555 uint32_t RESERVED10[8];
709 uint32_t RESERVED0[2];
715 uint32_t RESERVED1[2];
717 uint32_t RESERVED2[1];
719 uint32_t RESERVED3[1];
742 uint32_t RESERVED0[2];
746 uint32_t RESERVED1[3];
780 uint32_t RESERVED1[2];
787 uint32_t RESERVED3[2];
794 uint32_t RESERVED5[2];
797 uint32_t RESERVED6[2];
925 uint32_t RESERVED0[2];
927 uint32_t RESERVED1[13];
1084 uint32_t Reserved30[2];
1087 uint32_t Reserved5[3];
1094 uint32_t Reserved43[39];
1123 uint32_t Reserved44[15];
1155 uint32_t Reserved18[2];
1184 uint32_t Reserved[2];
1203 uint32_t Reserved20[4];
1210 uint32_t Reserved48[2];
1240 uint32_t RESERVED0[57];
1320 uint32_t RESERVED0[4];
1350 uint32_t RESERVED1[2];
1353 uint32_t RESERVED2[3];
1355 uint32_t RESERVED3[8];
1357 uint32_t RESERVED4[2];
1362 uint32_t RESERVED6[7];
1374 uint32_t RESERVED7[11];
1376 uint32_t RESERVED8[155];
1391 #define RAMITCM_BASE 0x00000000U 1392 #define FLASHITCM_BASE 0x00200000U 1393 #define FLASHAXI_BASE 0x08000000U 1394 #define RAMDTCM_BASE 0x20000000U 1395 #define PERIPH_BASE 0x40000000U 1396 #define BKPSRAM_BASE 0x40024000U 1397 #define QSPI_BASE 0x90000000U 1398 #define FMC_R_BASE 0xA0000000U 1399 #define QSPI_R_BASE 0xA0001000U 1400 #define SRAM1_BASE 0x20020000U 1401 #define SRAM2_BASE 0x2007C000U 1402 #define FLASH_END 0x081FFFFFU 1403 #define FLASH_OTP_BASE 0x1FF0F000U 1404 #define FLASH_OTP_END 0x1FF0F41FU 1407 #define FLASH_BASE FLASHAXI_BASE 1410 #define APB1PERIPH_BASE PERIPH_BASE 1411 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) 1412 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) 1413 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U) 1416 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) 1417 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) 1418 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) 1419 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) 1420 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) 1421 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) 1422 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U) 1423 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U) 1424 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U) 1425 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U) 1426 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U) 1427 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) 1428 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) 1429 #define CAN3_BASE (APB1PERIPH_BASE + 0x3400U) 1430 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) 1431 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) 1432 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U) 1433 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U) 1434 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U) 1435 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) 1436 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U) 1437 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) 1438 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) 1439 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) 1440 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000U) 1441 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) 1442 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U) 1443 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00U) 1444 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U) 1445 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U) 1446 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U) 1447 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U) 1450 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U) 1451 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U) 1452 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U) 1453 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U) 1454 #define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U) 1455 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) 1456 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U) 1457 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U) 1458 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U) 1459 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U) 1460 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) 1461 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U) 1462 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U) 1463 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U) 1464 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U) 1465 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U) 1466 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U) 1467 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U) 1468 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U) 1469 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U) 1470 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U) 1471 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U) 1472 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U) 1473 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004U) 1474 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024U) 1475 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U) 1476 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U) 1477 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U) 1478 #define DSI_BASE (APB2PERIPH_BASE + 0x6C00U) 1479 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400U) 1480 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U) 1481 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U) 1482 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U) 1483 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U) 1484 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80U) 1485 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0U) 1486 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0U) 1487 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0U) 1488 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U) 1489 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U) 1490 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200U) 1491 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280U) 1492 #define MDIOS_BASE (APB2PERIPH_BASE + 0x7800U) 1494 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U) 1495 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U) 1496 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U) 1497 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U) 1498 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U) 1499 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U) 1500 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U) 1501 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U) 1502 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U) 1503 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U) 1504 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U) 1505 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) 1506 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U) 1507 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) 1508 #define UID_BASE 0x1FF0F420U 1509 #define FLASHSIZE_BASE 0x1FF0F442U 1510 #define PACKAGE_BASE 0x1FFF7BF0U 1512 #define PACKAGESIZE_BASE PACKAGE_BASE 1514 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) 1515 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) 1516 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) 1517 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U) 1518 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U) 1519 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U) 1520 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U) 1521 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U) 1522 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U) 1523 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U) 1524 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U) 1525 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U) 1526 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U) 1527 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U) 1528 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U) 1529 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U) 1530 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U) 1531 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U) 1532 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U) 1533 #define ETH_MAC_BASE (ETH_BASE) 1534 #define ETH_MMC_BASE (ETH_BASE + 0x0100U) 1535 #define ETH_PTP_BASE (ETH_BASE + 0x0700U) 1536 #define ETH_DMA_BASE (ETH_BASE + 0x1000U) 1537 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U) 1539 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U) 1540 #define JPEG_BASE (AHB2PERIPH_BASE + 0x51000U) 1541 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U) 1543 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) 1544 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) 1545 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) 1546 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U) 1549 #define DBGMCU_BASE 0xE0042000U 1552 #define USB_OTG_HS_PERIPH_BASE 0x40040000U 1553 #define USB_OTG_FS_PERIPH_BASE 0x50000000U 1555 #define USB_OTG_GLOBAL_BASE 0x000U 1556 #define USB_OTG_DEVICE_BASE 0x800U 1557 #define USB_OTG_IN_ENDPOINT_BASE 0x900U 1558 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U 1559 #define USB_OTG_EP_REG_SIZE 0x20U 1560 #define USB_OTG_HOST_BASE 0x400U 1561 #define USB_OTG_HOST_PORT_BASE 0x440U 1562 #define USB_OTG_HOST_CHANNEL_BASE 0x500U 1563 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U 1564 #define USB_OTG_PCGCCTL_BASE 0xE00U 1565 #define USB_OTG_FIFO_BASE 0x1000U 1566 #define USB_OTG_FIFO_SIZE 0x1000U 1575 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 1576 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 1577 #define TIM4 ((TIM_TypeDef *) TIM4_BASE) 1578 #define TIM5 ((TIM_TypeDef *) TIM5_BASE) 1579 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 1580 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 1581 #define TIM12 ((TIM_TypeDef *) TIM12_BASE) 1582 #define TIM13 ((TIM_TypeDef *) TIM13_BASE) 1583 #define TIM14 ((TIM_TypeDef *) TIM14_BASE) 1584 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) 1585 #define RTC ((RTC_TypeDef *) RTC_BASE) 1586 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 1587 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 1588 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 1589 #define SPI3 ((SPI_TypeDef *) SPI3_BASE) 1590 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) 1591 #define USART2 ((USART_TypeDef *) USART2_BASE) 1592 #define USART3 ((USART_TypeDef *) USART3_BASE) 1593 #define UART4 ((USART_TypeDef *) UART4_BASE) 1594 #define UART5 ((USART_TypeDef *) UART5_BASE) 1595 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 1596 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 1597 #define I2C3 ((I2C_TypeDef *) I2C3_BASE) 1598 #define I2C4 ((I2C_TypeDef *) I2C4_BASE) 1599 #define CAN1 ((CAN_TypeDef *) CAN1_BASE) 1600 #define CAN2 ((CAN_TypeDef *) CAN2_BASE) 1601 #define CEC ((CEC_TypeDef *) CEC_BASE) 1602 #define PWR ((PWR_TypeDef *) PWR_BASE) 1603 #define DAC1 ((DAC_TypeDef *) DAC_BASE) 1604 #define DAC ((DAC_TypeDef *) DAC_BASE) 1605 #define UART7 ((USART_TypeDef *) UART7_BASE) 1606 #define UART8 ((USART_TypeDef *) UART8_BASE) 1607 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 1608 #define TIM8 ((TIM_TypeDef *) TIM8_BASE) 1609 #define USART1 ((USART_TypeDef *) USART1_BASE) 1610 #define USART6 ((USART_TypeDef *) USART6_BASE) 1611 #define ADC ((ADC_Common_TypeDef *) ADC_BASE) 1612 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 1613 #define ADC2 ((ADC_TypeDef *) ADC2_BASE) 1614 #define ADC3 ((ADC_TypeDef *) ADC3_BASE) 1615 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE) 1616 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) 1617 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 1618 #define SPI4 ((SPI_TypeDef *) SPI4_BASE) 1619 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 1620 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 1621 #define TIM9 ((TIM_TypeDef *) TIM9_BASE) 1622 #define TIM10 ((TIM_TypeDef *) TIM10_BASE) 1623 #define TIM11 ((TIM_TypeDef *) TIM11_BASE) 1624 #define SPI5 ((SPI_TypeDef *) SPI5_BASE) 1625 #define SPI6 ((SPI_TypeDef *) SPI6_BASE) 1626 #define SAI1 ((SAI_TypeDef *) SAI1_BASE) 1627 #define SAI2 ((SAI_TypeDef *) SAI2_BASE) 1628 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) 1629 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) 1630 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) 1631 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) 1632 #define LTDC ((LTDC_TypeDef *)LTDC_BASE) 1633 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) 1634 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) 1635 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 1636 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 1637 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 1638 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 1639 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 1640 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 1641 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) 1642 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) 1643 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) 1644 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) 1645 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) 1646 #define CRC ((CRC_TypeDef *) CRC_BASE) 1647 #define RCC ((RCC_TypeDef *) RCC_BASE) 1648 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 1649 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 1650 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) 1651 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) 1652 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) 1653 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) 1654 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) 1655 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) 1656 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) 1657 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) 1658 #define DMA2 ((DMA_TypeDef *) DMA2_BASE) 1659 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) 1660 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) 1661 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) 1662 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) 1663 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) 1664 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) 1665 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) 1666 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) 1667 #define ETH ((ETH_TypeDef *) ETH_BASE) 1668 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) 1669 #define DCMI ((DCMI_TypeDef *) DCMI_BASE) 1670 #define RNG ((RNG_TypeDef *) RNG_BASE) 1671 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) 1672 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) 1673 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) 1674 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) 1675 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) 1676 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 1677 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) 1678 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) 1679 #define CAN3 ((CAN_TypeDef *) CAN3_BASE) 1680 #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) 1681 #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) 1682 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) 1683 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) 1684 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) 1685 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) 1686 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) 1687 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) 1688 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) 1689 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) 1690 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) 1691 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) 1692 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) 1693 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) 1694 #define JPEG ((JPEG_TypeDef *) JPEG_BASE) 1695 #define DSI ((DSI_TypeDef *)DSI_BASE) 1719 #define ADC_SR_AWD_Pos (0U) 1720 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) 1721 #define ADC_SR_AWD ADC_SR_AWD_Msk 1722 #define ADC_SR_EOC_Pos (1U) 1723 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) 1724 #define ADC_SR_EOC ADC_SR_EOC_Msk 1725 #define ADC_SR_JEOC_Pos (2U) 1726 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) 1727 #define ADC_SR_JEOC ADC_SR_JEOC_Msk 1728 #define ADC_SR_JSTRT_Pos (3U) 1729 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) 1730 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk 1731 #define ADC_SR_STRT_Pos (4U) 1732 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) 1733 #define ADC_SR_STRT ADC_SR_STRT_Msk 1734 #define ADC_SR_OVR_Pos (5U) 1735 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) 1736 #define ADC_SR_OVR ADC_SR_OVR_Msk 1739 #define ADC_CR1_AWDCH_Pos (0U) 1740 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) 1741 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk 1742 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) 1743 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) 1744 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) 1745 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) 1746 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) 1747 #define ADC_CR1_EOCIE_Pos (5U) 1748 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) 1749 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk 1750 #define ADC_CR1_AWDIE_Pos (6U) 1751 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) 1752 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk 1753 #define ADC_CR1_JEOCIE_Pos (7U) 1754 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) 1755 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk 1756 #define ADC_CR1_SCAN_Pos (8U) 1757 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) 1758 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk 1759 #define ADC_CR1_AWDSGL_Pos (9U) 1760 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) 1761 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk 1762 #define ADC_CR1_JAUTO_Pos (10U) 1763 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) 1764 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk 1765 #define ADC_CR1_DISCEN_Pos (11U) 1766 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) 1767 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk 1768 #define ADC_CR1_JDISCEN_Pos (12U) 1769 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) 1770 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk 1771 #define ADC_CR1_DISCNUM_Pos (13U) 1772 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) 1773 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk 1774 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) 1775 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) 1776 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) 1777 #define ADC_CR1_JAWDEN_Pos (22U) 1778 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) 1779 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk 1780 #define ADC_CR1_AWDEN_Pos (23U) 1781 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) 1782 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk 1783 #define ADC_CR1_RES_Pos (24U) 1784 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) 1785 #define ADC_CR1_RES ADC_CR1_RES_Msk 1786 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) 1787 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) 1788 #define ADC_CR1_OVRIE_Pos (26U) 1789 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) 1790 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk 1793 #define ADC_CR2_ADON_Pos (0U) 1794 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) 1795 #define ADC_CR2_ADON ADC_CR2_ADON_Msk 1796 #define ADC_CR2_CONT_Pos (1U) 1797 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) 1798 #define ADC_CR2_CONT ADC_CR2_CONT_Msk 1799 #define ADC_CR2_DMA_Pos (8U) 1800 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) 1801 #define ADC_CR2_DMA ADC_CR2_DMA_Msk 1802 #define ADC_CR2_DDS_Pos (9U) 1803 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) 1804 #define ADC_CR2_DDS ADC_CR2_DDS_Msk 1805 #define ADC_CR2_EOCS_Pos (10U) 1806 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) 1807 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk 1808 #define ADC_CR2_ALIGN_Pos (11U) 1809 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) 1810 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk 1811 #define ADC_CR2_JEXTSEL_Pos (16U) 1812 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) 1813 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk 1814 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) 1815 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) 1816 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) 1817 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) 1818 #define ADC_CR2_JEXTEN_Pos (20U) 1819 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) 1820 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk 1821 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) 1822 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) 1823 #define ADC_CR2_JSWSTART_Pos (22U) 1824 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) 1825 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk 1826 #define ADC_CR2_EXTSEL_Pos (24U) 1827 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) 1828 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk 1829 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) 1830 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) 1831 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) 1832 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) 1833 #define ADC_CR2_EXTEN_Pos (28U) 1834 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) 1835 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk 1836 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) 1837 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) 1838 #define ADC_CR2_SWSTART_Pos (30U) 1839 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) 1840 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk 1843 #define ADC_SMPR1_SMP10_Pos (0U) 1844 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) 1845 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk 1846 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) 1847 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) 1848 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) 1849 #define ADC_SMPR1_SMP11_Pos (3U) 1850 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) 1851 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk 1852 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) 1853 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) 1854 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) 1855 #define ADC_SMPR1_SMP12_Pos (6U) 1856 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) 1857 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk 1858 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) 1859 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) 1860 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) 1861 #define ADC_SMPR1_SMP13_Pos (9U) 1862 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) 1863 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk 1864 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) 1865 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) 1866 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) 1867 #define ADC_SMPR1_SMP14_Pos (12U) 1868 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) 1869 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk 1870 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) 1871 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) 1872 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) 1873 #define ADC_SMPR1_SMP15_Pos (15U) 1874 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) 1875 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk 1876 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) 1877 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) 1878 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) 1879 #define ADC_SMPR1_SMP16_Pos (18U) 1880 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) 1881 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk 1882 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) 1883 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) 1884 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) 1885 #define ADC_SMPR1_SMP17_Pos (21U) 1886 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) 1887 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk 1888 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) 1889 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) 1890 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) 1891 #define ADC_SMPR1_SMP18_Pos (24U) 1892 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) 1893 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk 1894 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) 1895 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) 1896 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) 1899 #define ADC_SMPR2_SMP0_Pos (0U) 1900 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) 1901 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk 1902 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) 1903 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) 1904 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) 1905 #define ADC_SMPR2_SMP1_Pos (3U) 1906 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) 1907 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk 1908 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) 1909 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) 1910 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) 1911 #define ADC_SMPR2_SMP2_Pos (6U) 1912 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) 1913 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk 1914 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) 1915 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) 1916 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) 1917 #define ADC_SMPR2_SMP3_Pos (9U) 1918 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) 1919 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk 1920 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) 1921 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) 1922 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) 1923 #define ADC_SMPR2_SMP4_Pos (12U) 1924 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) 1925 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk 1926 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) 1927 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) 1928 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) 1929 #define ADC_SMPR2_SMP5_Pos (15U) 1930 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) 1931 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk 1932 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) 1933 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) 1934 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) 1935 #define ADC_SMPR2_SMP6_Pos (18U) 1936 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) 1937 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk 1938 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) 1939 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) 1940 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) 1941 #define ADC_SMPR2_SMP7_Pos (21U) 1942 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) 1943 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk 1944 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) 1945 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) 1946 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) 1947 #define ADC_SMPR2_SMP8_Pos (24U) 1948 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) 1949 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk 1950 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) 1951 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) 1952 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) 1953 #define ADC_SMPR2_SMP9_Pos (27U) 1954 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) 1955 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk 1956 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) 1957 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) 1958 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) 1961 #define ADC_JOFR1_JOFFSET1_Pos (0U) 1962 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) 1963 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk 1966 #define ADC_JOFR2_JOFFSET2_Pos (0U) 1967 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) 1968 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk 1971 #define ADC_JOFR3_JOFFSET3_Pos (0U) 1972 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) 1973 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk 1976 #define ADC_JOFR4_JOFFSET4_Pos (0U) 1977 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) 1978 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk 1981 #define ADC_HTR_HT_Pos (0U) 1982 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) 1983 #define ADC_HTR_HT ADC_HTR_HT_Msk 1986 #define ADC_LTR_LT_Pos (0U) 1987 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) 1988 #define ADC_LTR_LT ADC_LTR_LT_Msk 1991 #define ADC_SQR1_SQ13_Pos (0U) 1992 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) 1993 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk 1994 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) 1995 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) 1996 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) 1997 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) 1998 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) 1999 #define ADC_SQR1_SQ14_Pos (5U) 2000 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) 2001 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk 2002 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) 2003 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) 2004 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) 2005 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) 2006 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) 2007 #define ADC_SQR1_SQ15_Pos (10U) 2008 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) 2009 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk 2010 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) 2011 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) 2012 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) 2013 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) 2014 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) 2015 #define ADC_SQR1_SQ16_Pos (15U) 2016 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) 2017 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk 2018 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) 2019 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) 2020 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) 2021 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) 2022 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) 2023 #define ADC_SQR1_L_Pos (20U) 2024 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) 2025 #define ADC_SQR1_L ADC_SQR1_L_Msk 2026 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) 2027 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) 2028 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) 2029 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) 2032 #define ADC_SQR2_SQ7_Pos (0U) 2033 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) 2034 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk 2035 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) 2036 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) 2037 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) 2038 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) 2039 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) 2040 #define ADC_SQR2_SQ8_Pos (5U) 2041 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) 2042 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk 2043 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) 2044 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) 2045 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) 2046 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) 2047 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) 2048 #define ADC_SQR2_SQ9_Pos (10U) 2049 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) 2050 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk 2051 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) 2052 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) 2053 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) 2054 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) 2055 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) 2056 #define ADC_SQR2_SQ10_Pos (15U) 2057 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) 2058 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk 2059 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) 2060 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) 2061 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) 2062 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) 2063 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) 2064 #define ADC_SQR2_SQ11_Pos (20U) 2065 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) 2066 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk 2067 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) 2068 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) 2069 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) 2070 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) 2071 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) 2072 #define ADC_SQR2_SQ12_Pos (25U) 2073 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) 2074 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk 2075 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) 2076 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) 2077 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) 2078 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) 2079 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) 2082 #define ADC_SQR3_SQ1_Pos (0U) 2083 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) 2084 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk 2085 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) 2086 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) 2087 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) 2088 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) 2089 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) 2090 #define ADC_SQR3_SQ2_Pos (5U) 2091 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) 2092 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk 2093 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) 2094 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) 2095 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) 2096 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) 2097 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) 2098 #define ADC_SQR3_SQ3_Pos (10U) 2099 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) 2100 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk 2101 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) 2102 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) 2103 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) 2104 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) 2105 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) 2106 #define ADC_SQR3_SQ4_Pos (15U) 2107 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) 2108 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk 2109 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) 2110 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) 2111 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) 2112 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) 2113 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) 2114 #define ADC_SQR3_SQ5_Pos (20U) 2115 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) 2116 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk 2117 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) 2118 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) 2119 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) 2120 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) 2121 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) 2122 #define ADC_SQR3_SQ6_Pos (25U) 2123 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) 2124 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk 2125 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) 2126 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) 2127 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) 2128 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) 2129 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) 2132 #define ADC_JSQR_JSQ1_Pos (0U) 2133 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) 2134 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk 2135 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) 2136 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) 2137 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) 2138 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) 2139 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) 2140 #define ADC_JSQR_JSQ2_Pos (5U) 2141 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) 2142 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk 2143 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) 2144 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) 2145 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) 2146 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) 2147 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) 2148 #define ADC_JSQR_JSQ3_Pos (10U) 2149 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) 2150 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk 2151 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) 2152 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) 2153 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) 2154 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) 2155 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) 2156 #define ADC_JSQR_JSQ4_Pos (15U) 2157 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) 2158 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk 2159 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) 2160 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) 2161 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) 2162 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) 2163 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) 2164 #define ADC_JSQR_JL_Pos (20U) 2165 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) 2166 #define ADC_JSQR_JL ADC_JSQR_JL_Msk 2167 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) 2168 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) 2171 #define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) 2174 #define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) 2177 #define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) 2180 #define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) 2183 #define ADC_DR_DATA_Pos (0U) 2184 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) 2185 #define ADC_DR_DATA ADC_DR_DATA_Msk 2186 #define ADC_DR_ADC2DATA_Pos (16U) 2187 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) 2188 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk 2191 #define ADC_CSR_AWD1_Pos (0U) 2192 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) 2193 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk 2194 #define ADC_CSR_EOC1_Pos (1U) 2195 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) 2196 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk 2197 #define ADC_CSR_JEOC1_Pos (2U) 2198 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) 2199 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk 2200 #define ADC_CSR_JSTRT1_Pos (3U) 2201 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) 2202 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk 2203 #define ADC_CSR_STRT1_Pos (4U) 2204 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) 2205 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk 2206 #define ADC_CSR_OVR1_Pos (5U) 2207 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) 2208 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk 2209 #define ADC_CSR_AWD2_Pos (8U) 2210 #define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) 2211 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk 2212 #define ADC_CSR_EOC2_Pos (9U) 2213 #define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) 2214 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk 2215 #define ADC_CSR_JEOC2_Pos (10U) 2216 #define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) 2217 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk 2218 #define ADC_CSR_JSTRT2_Pos (11U) 2219 #define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) 2220 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk 2221 #define ADC_CSR_STRT2_Pos (12U) 2222 #define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) 2223 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk 2224 #define ADC_CSR_OVR2_Pos (13U) 2225 #define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) 2226 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk 2227 #define ADC_CSR_AWD3_Pos (16U) 2228 #define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) 2229 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk 2230 #define ADC_CSR_EOC3_Pos (17U) 2231 #define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) 2232 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk 2233 #define ADC_CSR_JEOC3_Pos (18U) 2234 #define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) 2235 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk 2236 #define ADC_CSR_JSTRT3_Pos (19U) 2237 #define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) 2238 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk 2239 #define ADC_CSR_STRT3_Pos (20U) 2240 #define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) 2241 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk 2242 #define ADC_CSR_OVR3_Pos (21U) 2243 #define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) 2244 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk 2247 #define ADC_CSR_DOVR1 ADC_CSR_OVR1 2248 #define ADC_CSR_DOVR2 ADC_CSR_OVR2 2249 #define ADC_CSR_DOVR3 ADC_CSR_OVR3 2253 #define ADC_CCR_MULTI_Pos (0U) 2254 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) 2255 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk 2256 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) 2257 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) 2258 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) 2259 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) 2260 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) 2261 #define ADC_CCR_DELAY_Pos (8U) 2262 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) 2263 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk 2264 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) 2265 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) 2266 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) 2267 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) 2268 #define ADC_CCR_DDS_Pos (13U) 2269 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) 2270 #define ADC_CCR_DDS ADC_CCR_DDS_Msk 2271 #define ADC_CCR_DMA_Pos (14U) 2272 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) 2273 #define ADC_CCR_DMA ADC_CCR_DMA_Msk 2274 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) 2275 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) 2276 #define ADC_CCR_ADCPRE_Pos (16U) 2277 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) 2278 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk 2279 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) 2280 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) 2281 #define ADC_CCR_VBATE_Pos (22U) 2282 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) 2283 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk 2284 #define ADC_CCR_TSVREFE_Pos (23U) 2285 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) 2286 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk 2289 #define ADC_CDR_DATA1_Pos (0U) 2290 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) 2291 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk 2292 #define ADC_CDR_DATA2_Pos (16U) 2293 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) 2294 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk 2297 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1 2298 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2 2307 #define CAN_MCR_INRQ_Pos (0U) 2308 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) 2309 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk 2310 #define CAN_MCR_SLEEP_Pos (1U) 2311 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) 2312 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk 2313 #define CAN_MCR_TXFP_Pos (2U) 2314 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) 2315 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk 2316 #define CAN_MCR_RFLM_Pos (3U) 2317 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) 2318 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk 2319 #define CAN_MCR_NART_Pos (4U) 2320 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) 2321 #define CAN_MCR_NART CAN_MCR_NART_Msk 2322 #define CAN_MCR_AWUM_Pos (5U) 2323 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) 2324 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk 2325 #define CAN_MCR_ABOM_Pos (6U) 2326 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) 2327 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk 2328 #define CAN_MCR_TTCM_Pos (7U) 2329 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) 2330 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk 2331 #define CAN_MCR_RESET_Pos (15U) 2332 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) 2333 #define CAN_MCR_RESET CAN_MCR_RESET_Msk 2336 #define CAN_MSR_INAK_Pos (0U) 2337 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) 2338 #define CAN_MSR_INAK CAN_MSR_INAK_Msk 2339 #define CAN_MSR_SLAK_Pos (1U) 2340 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) 2341 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk 2342 #define CAN_MSR_ERRI_Pos (2U) 2343 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) 2344 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk 2345 #define CAN_MSR_WKUI_Pos (3U) 2346 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) 2347 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk 2348 #define CAN_MSR_SLAKI_Pos (4U) 2349 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) 2350 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk 2351 #define CAN_MSR_TXM_Pos (8U) 2352 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) 2353 #define CAN_MSR_TXM CAN_MSR_TXM_Msk 2354 #define CAN_MSR_RXM_Pos (9U) 2355 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) 2356 #define CAN_MSR_RXM CAN_MSR_RXM_Msk 2357 #define CAN_MSR_SAMP_Pos (10U) 2358 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) 2359 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk 2360 #define CAN_MSR_RX_Pos (11U) 2361 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) 2362 #define CAN_MSR_RX CAN_MSR_RX_Msk 2365 #define CAN_TSR_RQCP0_Pos (0U) 2366 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) 2367 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk 2368 #define CAN_TSR_TXOK0_Pos (1U) 2369 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) 2370 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk 2371 #define CAN_TSR_ALST0_Pos (2U) 2372 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) 2373 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk 2374 #define CAN_TSR_TERR0_Pos (3U) 2375 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) 2376 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk 2377 #define CAN_TSR_ABRQ0_Pos (7U) 2378 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) 2379 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk 2380 #define CAN_TSR_RQCP1_Pos (8U) 2381 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) 2382 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk 2383 #define CAN_TSR_TXOK1_Pos (9U) 2384 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) 2385 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk 2386 #define CAN_TSR_ALST1_Pos (10U) 2387 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) 2388 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk 2389 #define CAN_TSR_TERR1_Pos (11U) 2390 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) 2391 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk 2392 #define CAN_TSR_ABRQ1_Pos (15U) 2393 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) 2394 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk 2395 #define CAN_TSR_RQCP2_Pos (16U) 2396 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) 2397 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk 2398 #define CAN_TSR_TXOK2_Pos (17U) 2399 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) 2400 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk 2401 #define CAN_TSR_ALST2_Pos (18U) 2402 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) 2403 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk 2404 #define CAN_TSR_TERR2_Pos (19U) 2405 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) 2406 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk 2407 #define CAN_TSR_ABRQ2_Pos (23U) 2408 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) 2409 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk 2410 #define CAN_TSR_CODE_Pos (24U) 2411 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) 2412 #define CAN_TSR_CODE CAN_TSR_CODE_Msk 2414 #define CAN_TSR_TME_Pos (26U) 2415 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) 2416 #define CAN_TSR_TME CAN_TSR_TME_Msk 2417 #define CAN_TSR_TME0_Pos (26U) 2418 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) 2419 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk 2420 #define CAN_TSR_TME1_Pos (27U) 2421 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) 2422 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk 2423 #define CAN_TSR_TME2_Pos (28U) 2424 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) 2425 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk 2427 #define CAN_TSR_LOW_Pos (29U) 2428 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) 2429 #define CAN_TSR_LOW CAN_TSR_LOW_Msk 2430 #define CAN_TSR_LOW0_Pos (29U) 2431 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) 2432 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk 2433 #define CAN_TSR_LOW1_Pos (30U) 2434 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) 2435 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk 2436 #define CAN_TSR_LOW2_Pos (31U) 2437 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) 2438 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk 2441 #define CAN_RF0R_FMP0_Pos (0U) 2442 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) 2443 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk 2444 #define CAN_RF0R_FULL0_Pos (3U) 2445 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) 2446 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk 2447 #define CAN_RF0R_FOVR0_Pos (4U) 2448 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) 2449 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk 2450 #define CAN_RF0R_RFOM0_Pos (5U) 2451 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) 2452 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk 2455 #define CAN_RF1R_FMP1_Pos (0U) 2456 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) 2457 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk 2458 #define CAN_RF1R_FULL1_Pos (3U) 2459 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) 2460 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk 2461 #define CAN_RF1R_FOVR1_Pos (4U) 2462 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) 2463 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk 2464 #define CAN_RF1R_RFOM1_Pos (5U) 2465 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) 2466 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk 2469 #define CAN_IER_TMEIE_Pos (0U) 2470 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) 2471 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk 2472 #define CAN_IER_FMPIE0_Pos (1U) 2473 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) 2474 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk 2475 #define CAN_IER_FFIE0_Pos (2U) 2476 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) 2477 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk 2478 #define CAN_IER_FOVIE0_Pos (3U) 2479 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) 2480 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk 2481 #define CAN_IER_FMPIE1_Pos (4U) 2482 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) 2483 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk 2484 #define CAN_IER_FFIE1_Pos (5U) 2485 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) 2486 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk 2487 #define CAN_IER_FOVIE1_Pos (6U) 2488 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) 2489 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk 2490 #define CAN_IER_EWGIE_Pos (8U) 2491 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) 2492 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk 2493 #define CAN_IER_EPVIE_Pos (9U) 2494 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) 2495 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk 2496 #define CAN_IER_BOFIE_Pos (10U) 2497 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) 2498 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk 2499 #define CAN_IER_LECIE_Pos (11U) 2500 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) 2501 #define CAN_IER_LECIE CAN_IER_LECIE_Msk 2502 #define CAN_IER_ERRIE_Pos (15U) 2503 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) 2504 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk 2505 #define CAN_IER_WKUIE_Pos (16U) 2506 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) 2507 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk 2508 #define CAN_IER_SLKIE_Pos (17U) 2509 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) 2510 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk 2513 #define CAN_ESR_EWGF_Pos (0U) 2514 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) 2515 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk 2516 #define CAN_ESR_EPVF_Pos (1U) 2517 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) 2518 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk 2519 #define CAN_ESR_BOFF_Pos (2U) 2520 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) 2521 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk 2523 #define CAN_ESR_LEC_Pos (4U) 2524 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) 2525 #define CAN_ESR_LEC CAN_ESR_LEC_Msk 2526 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) 2527 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) 2528 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) 2530 #define CAN_ESR_TEC_Pos (16U) 2531 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) 2532 #define CAN_ESR_TEC CAN_ESR_TEC_Msk 2533 #define CAN_ESR_REC_Pos (24U) 2534 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) 2535 #define CAN_ESR_REC CAN_ESR_REC_Msk 2538 #define CAN_BTR_BRP_Pos (0U) 2539 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) 2540 #define CAN_BTR_BRP CAN_BTR_BRP_Msk 2541 #define CAN_BTR_TS1_Pos (16U) 2542 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) 2543 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk 2544 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) 2545 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) 2546 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) 2547 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) 2548 #define CAN_BTR_TS2_Pos (20U) 2549 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) 2550 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk 2551 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) 2552 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) 2553 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) 2554 #define CAN_BTR_SJW_Pos (24U) 2555 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) 2556 #define CAN_BTR_SJW CAN_BTR_SJW_Msk 2557 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) 2558 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) 2559 #define CAN_BTR_LBKM_Pos (30U) 2560 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) 2561 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk 2562 #define CAN_BTR_SILM_Pos (31U) 2563 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) 2564 #define CAN_BTR_SILM CAN_BTR_SILM_Msk 2568 #define CAN_TI0R_TXRQ_Pos (0U) 2569 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) 2570 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk 2571 #define CAN_TI0R_RTR_Pos (1U) 2572 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) 2573 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk 2574 #define CAN_TI0R_IDE_Pos (2U) 2575 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) 2576 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk 2577 #define CAN_TI0R_EXID_Pos (3U) 2578 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) 2579 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk 2580 #define CAN_TI0R_STID_Pos (21U) 2581 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) 2582 #define CAN_TI0R_STID CAN_TI0R_STID_Msk 2585 #define CAN_TDT0R_DLC_Pos (0U) 2586 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) 2587 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk 2588 #define CAN_TDT0R_TGT_Pos (8U) 2589 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) 2590 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk 2591 #define CAN_TDT0R_TIME_Pos (16U) 2592 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) 2593 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk 2596 #define CAN_TDL0R_DATA0_Pos (0U) 2597 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) 2598 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk 2599 #define CAN_TDL0R_DATA1_Pos (8U) 2600 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) 2601 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk 2602 #define CAN_TDL0R_DATA2_Pos (16U) 2603 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) 2604 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk 2605 #define CAN_TDL0R_DATA3_Pos (24U) 2606 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) 2607 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk 2610 #define CAN_TDH0R_DATA4_Pos (0U) 2611 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) 2612 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk 2613 #define CAN_TDH0R_DATA5_Pos (8U) 2614 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) 2615 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk 2616 #define CAN_TDH0R_DATA6_Pos (16U) 2617 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) 2618 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk 2619 #define CAN_TDH0R_DATA7_Pos (24U) 2620 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) 2621 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk 2624 #define CAN_TI1R_TXRQ_Pos (0U) 2625 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) 2626 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk 2627 #define CAN_TI1R_RTR_Pos (1U) 2628 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) 2629 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk 2630 #define CAN_TI1R_IDE_Pos (2U) 2631 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) 2632 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk 2633 #define CAN_TI1R_EXID_Pos (3U) 2634 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) 2635 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk 2636 #define CAN_TI1R_STID_Pos (21U) 2637 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) 2638 #define CAN_TI1R_STID CAN_TI1R_STID_Msk 2641 #define CAN_TDT1R_DLC_Pos (0U) 2642 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) 2643 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk 2644 #define CAN_TDT1R_TGT_Pos (8U) 2645 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) 2646 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk 2647 #define CAN_TDT1R_TIME_Pos (16U) 2648 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) 2649 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk 2652 #define CAN_TDL1R_DATA0_Pos (0U) 2653 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) 2654 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk 2655 #define CAN_TDL1R_DATA1_Pos (8U) 2656 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) 2657 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk 2658 #define CAN_TDL1R_DATA2_Pos (16U) 2659 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) 2660 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk 2661 #define CAN_TDL1R_DATA3_Pos (24U) 2662 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) 2663 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk 2666 #define CAN_TDH1R_DATA4_Pos (0U) 2667 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) 2668 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk 2669 #define CAN_TDH1R_DATA5_Pos (8U) 2670 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) 2671 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk 2672 #define CAN_TDH1R_DATA6_Pos (16U) 2673 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) 2674 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk 2675 #define CAN_TDH1R_DATA7_Pos (24U) 2676 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) 2677 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk 2680 #define CAN_TI2R_TXRQ_Pos (0U) 2681 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) 2682 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk 2683 #define CAN_TI2R_RTR_Pos (1U) 2684 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) 2685 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk 2686 #define CAN_TI2R_IDE_Pos (2U) 2687 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) 2688 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk 2689 #define CAN_TI2R_EXID_Pos (3U) 2690 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) 2691 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk 2692 #define CAN_TI2R_STID_Pos (21U) 2693 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) 2694 #define CAN_TI2R_STID CAN_TI2R_STID_Msk 2697 #define CAN_TDT2R_DLC_Pos (0U) 2698 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) 2699 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk 2700 #define CAN_TDT2R_TGT_Pos (8U) 2701 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) 2702 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk 2703 #define CAN_TDT2R_TIME_Pos (16U) 2704 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) 2705 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk 2708 #define CAN_TDL2R_DATA0_Pos (0U) 2709 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) 2710 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk 2711 #define CAN_TDL2R_DATA1_Pos (8U) 2712 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) 2713 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk 2714 #define CAN_TDL2R_DATA2_Pos (16U) 2715 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) 2716 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk 2717 #define CAN_TDL2R_DATA3_Pos (24U) 2718 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) 2719 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk 2722 #define CAN_TDH2R_DATA4_Pos (0U) 2723 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) 2724 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk 2725 #define CAN_TDH2R_DATA5_Pos (8U) 2726 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) 2727 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk 2728 #define CAN_TDH2R_DATA6_Pos (16U) 2729 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) 2730 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk 2731 #define CAN_TDH2R_DATA7_Pos (24U) 2732 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) 2733 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk 2736 #define CAN_RI0R_RTR_Pos (1U) 2737 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) 2738 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk 2739 #define CAN_RI0R_IDE_Pos (2U) 2740 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) 2741 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk 2742 #define CAN_RI0R_EXID_Pos (3U) 2743 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) 2744 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk 2745 #define CAN_RI0R_STID_Pos (21U) 2746 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) 2747 #define CAN_RI0R_STID CAN_RI0R_STID_Msk 2750 #define CAN_RDT0R_DLC_Pos (0U) 2751 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) 2752 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk 2753 #define CAN_RDT0R_FMI_Pos (8U) 2754 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) 2755 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk 2756 #define CAN_RDT0R_TIME_Pos (16U) 2757 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) 2758 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk 2761 #define CAN_RDL0R_DATA0_Pos (0U) 2762 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) 2763 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk 2764 #define CAN_RDL0R_DATA1_Pos (8U) 2765 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) 2766 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk 2767 #define CAN_RDL0R_DATA2_Pos (16U) 2768 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) 2769 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk 2770 #define CAN_RDL0R_DATA3_Pos (24U) 2771 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) 2772 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk 2775 #define CAN_RDH0R_DATA4_Pos (0U) 2776 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) 2777 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk 2778 #define CAN_RDH0R_DATA5_Pos (8U) 2779 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) 2780 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk 2781 #define CAN_RDH0R_DATA6_Pos (16U) 2782 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) 2783 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk 2784 #define CAN_RDH0R_DATA7_Pos (24U) 2785 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) 2786 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk 2789 #define CAN_RI1R_RTR_Pos (1U) 2790 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) 2791 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk 2792 #define CAN_RI1R_IDE_Pos (2U) 2793 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) 2794 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk 2795 #define CAN_RI1R_EXID_Pos (3U) 2796 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) 2797 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk 2798 #define CAN_RI1R_STID_Pos (21U) 2799 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) 2800 #define CAN_RI1R_STID CAN_RI1R_STID_Msk 2803 #define CAN_RDT1R_DLC_Pos (0U) 2804 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) 2805 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk 2806 #define CAN_RDT1R_FMI_Pos (8U) 2807 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) 2808 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk 2809 #define CAN_RDT1R_TIME_Pos (16U) 2810 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) 2811 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk 2814 #define CAN_RDL1R_DATA0_Pos (0U) 2815 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) 2816 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk 2817 #define CAN_RDL1R_DATA1_Pos (8U) 2818 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) 2819 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk 2820 #define CAN_RDL1R_DATA2_Pos (16U) 2821 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) 2822 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk 2823 #define CAN_RDL1R_DATA3_Pos (24U) 2824 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) 2825 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk 2828 #define CAN_RDH1R_DATA4_Pos (0U) 2829 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) 2830 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk 2831 #define CAN_RDH1R_DATA5_Pos (8U) 2832 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) 2833 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk 2834 #define CAN_RDH1R_DATA6_Pos (16U) 2835 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) 2836 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk 2837 #define CAN_RDH1R_DATA7_Pos (24U) 2838 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) 2839 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk 2843 #define CAN_FMR_FINIT ((uint8_t)0x01U) 2844 #define CAN_FMR_CAN2SB_Pos (8U) 2845 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) 2846 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk 2849 #define CAN_FM1R_FBM_Pos (0U) 2850 #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) 2851 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk 2852 #define CAN_FM1R_FBM0_Pos (0U) 2853 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) 2854 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk 2855 #define CAN_FM1R_FBM1_Pos (1U) 2856 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) 2857 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk 2858 #define CAN_FM1R_FBM2_Pos (2U) 2859 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) 2860 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk 2861 #define CAN_FM1R_FBM3_Pos (3U) 2862 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) 2863 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk 2864 #define CAN_FM1R_FBM4_Pos (4U) 2865 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) 2866 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk 2867 #define CAN_FM1R_FBM5_Pos (5U) 2868 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) 2869 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk 2870 #define CAN_FM1R_FBM6_Pos (6U) 2871 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) 2872 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk 2873 #define CAN_FM1R_FBM7_Pos (7U) 2874 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) 2875 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk 2876 #define CAN_FM1R_FBM8_Pos (8U) 2877 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) 2878 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk 2879 #define CAN_FM1R_FBM9_Pos (9U) 2880 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) 2881 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk 2882 #define CAN_FM1R_FBM10_Pos (10U) 2883 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) 2884 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk 2885 #define CAN_FM1R_FBM11_Pos (11U) 2886 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) 2887 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk 2888 #define CAN_FM1R_FBM12_Pos (12U) 2889 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) 2890 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk 2891 #define CAN_FM1R_FBM13_Pos (13U) 2892 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) 2893 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk 2896 #define CAN_FS1R_FSC_Pos (0U) 2897 #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) 2898 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk 2899 #define CAN_FS1R_FSC0_Pos (0U) 2900 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) 2901 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk 2902 #define CAN_FS1R_FSC1_Pos (1U) 2903 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) 2904 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk 2905 #define CAN_FS1R_FSC2_Pos (2U) 2906 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) 2907 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk 2908 #define CAN_FS1R_FSC3_Pos (3U) 2909 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) 2910 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk 2911 #define CAN_FS1R_FSC4_Pos (4U) 2912 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) 2913 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk 2914 #define CAN_FS1R_FSC5_Pos (5U) 2915 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) 2916 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk 2917 #define CAN_FS1R_FSC6_Pos (6U) 2918 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) 2919 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk 2920 #define CAN_FS1R_FSC7_Pos (7U) 2921 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) 2922 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk 2923 #define CAN_FS1R_FSC8_Pos (8U) 2924 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) 2925 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk 2926 #define CAN_FS1R_FSC9_Pos (9U) 2927 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) 2928 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk 2929 #define CAN_FS1R_FSC10_Pos (10U) 2930 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) 2931 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk 2932 #define CAN_FS1R_FSC11_Pos (11U) 2933 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) 2934 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk 2935 #define CAN_FS1R_FSC12_Pos (12U) 2936 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) 2937 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk 2938 #define CAN_FS1R_FSC13_Pos (13U) 2939 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) 2940 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk 2943 #define CAN_FFA1R_FFA_Pos (0U) 2944 #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) 2945 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk 2946 #define CAN_FFA1R_FFA0_Pos (0U) 2947 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) 2948 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk 2949 #define CAN_FFA1R_FFA1_Pos (1U) 2950 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) 2951 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk 2952 #define CAN_FFA1R_FFA2_Pos (2U) 2953 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) 2954 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk 2955 #define CAN_FFA1R_FFA3_Pos (3U) 2956 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) 2957 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk 2958 #define CAN_FFA1R_FFA4_Pos (4U) 2959 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) 2960 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk 2961 #define CAN_FFA1R_FFA5_Pos (5U) 2962 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) 2963 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk 2964 #define CAN_FFA1R_FFA6_Pos (6U) 2965 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) 2966 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk 2967 #define CAN_FFA1R_FFA7_Pos (7U) 2968 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) 2969 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk 2970 #define CAN_FFA1R_FFA8_Pos (8U) 2971 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) 2972 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk 2973 #define CAN_FFA1R_FFA9_Pos (9U) 2974 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) 2975 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk 2976 #define CAN_FFA1R_FFA10_Pos (10U) 2977 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) 2978 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk 2979 #define CAN_FFA1R_FFA11_Pos (11U) 2980 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) 2981 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk 2982 #define CAN_FFA1R_FFA12_Pos (12U) 2983 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) 2984 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk 2985 #define CAN_FFA1R_FFA13_Pos (13U) 2986 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) 2987 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk 2990 #define CAN_FA1R_FACT_Pos (0U) 2991 #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) 2992 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk 2993 #define CAN_FA1R_FACT0_Pos (0U) 2994 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) 2995 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk 2996 #define CAN_FA1R_FACT1_Pos (1U) 2997 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) 2998 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk 2999 #define CAN_FA1R_FACT2_Pos (2U) 3000 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) 3001 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk 3002 #define CAN_FA1R_FACT3_Pos (3U) 3003 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) 3004 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk 3005 #define CAN_FA1R_FACT4_Pos (4U) 3006 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) 3007 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk 3008 #define CAN_FA1R_FACT5_Pos (5U) 3009 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) 3010 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk 3011 #define CAN_FA1R_FACT6_Pos (6U) 3012 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) 3013 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk 3014 #define CAN_FA1R_FACT7_Pos (7U) 3015 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) 3016 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk 3017 #define CAN_FA1R_FACT8_Pos (8U) 3018 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) 3019 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk 3020 #define CAN_FA1R_FACT9_Pos (9U) 3021 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) 3022 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk 3023 #define CAN_FA1R_FACT10_Pos (10U) 3024 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) 3025 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk 3026 #define CAN_FA1R_FACT11_Pos (11U) 3027 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) 3028 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk 3029 #define CAN_FA1R_FACT12_Pos (12U) 3030 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) 3031 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk 3032 #define CAN_FA1R_FACT13_Pos (13U) 3033 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) 3034 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk 3037 #define CAN_F0R1_FB0_Pos (0U) 3038 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) 3039 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk 3040 #define CAN_F0R1_FB1_Pos (1U) 3041 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) 3042 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk 3043 #define CAN_F0R1_FB2_Pos (2U) 3044 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) 3045 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk 3046 #define CAN_F0R1_FB3_Pos (3U) 3047 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) 3048 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk 3049 #define CAN_F0R1_FB4_Pos (4U) 3050 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) 3051 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk 3052 #define CAN_F0R1_FB5_Pos (5U) 3053 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) 3054 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk 3055 #define CAN_F0R1_FB6_Pos (6U) 3056 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) 3057 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk 3058 #define CAN_F0R1_FB7_Pos (7U) 3059 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) 3060 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk 3061 #define CAN_F0R1_FB8_Pos (8U) 3062 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) 3063 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk 3064 #define CAN_F0R1_FB9_Pos (9U) 3065 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) 3066 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk 3067 #define CAN_F0R1_FB10_Pos (10U) 3068 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) 3069 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk 3070 #define CAN_F0R1_FB11_Pos (11U) 3071 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) 3072 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk 3073 #define CAN_F0R1_FB12_Pos (12U) 3074 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) 3075 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk 3076 #define CAN_F0R1_FB13_Pos (13U) 3077 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) 3078 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk 3079 #define CAN_F0R1_FB14_Pos (14U) 3080 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) 3081 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk 3082 #define CAN_F0R1_FB15_Pos (15U) 3083 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) 3084 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk 3085 #define CAN_F0R1_FB16_Pos (16U) 3086 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) 3087 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk 3088 #define CAN_F0R1_FB17_Pos (17U) 3089 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) 3090 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk 3091 #define CAN_F0R1_FB18_Pos (18U) 3092 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) 3093 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk 3094 #define CAN_F0R1_FB19_Pos (19U) 3095 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) 3096 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk 3097 #define CAN_F0R1_FB20_Pos (20U) 3098 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) 3099 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk 3100 #define CAN_F0R1_FB21_Pos (21U) 3101 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) 3102 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk 3103 #define CAN_F0R1_FB22_Pos (22U) 3104 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) 3105 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk 3106 #define CAN_F0R1_FB23_Pos (23U) 3107 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) 3108 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk 3109 #define CAN_F0R1_FB24_Pos (24U) 3110 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) 3111 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk 3112 #define CAN_F0R1_FB25_Pos (25U) 3113 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) 3114 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk 3115 #define CAN_F0R1_FB26_Pos (26U) 3116 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) 3117 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk 3118 #define CAN_F0R1_FB27_Pos (27U) 3119 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) 3120 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk 3121 #define CAN_F0R1_FB28_Pos (28U) 3122 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) 3123 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk 3124 #define CAN_F0R1_FB29_Pos (29U) 3125 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) 3126 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk 3127 #define CAN_F0R1_FB30_Pos (30U) 3128 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) 3129 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk 3130 #define CAN_F0R1_FB31_Pos (31U) 3131 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) 3132 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk 3135 #define CAN_F1R1_FB0_Pos (0U) 3136 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) 3137 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk 3138 #define CAN_F1R1_FB1_Pos (1U) 3139 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) 3140 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk 3141 #define CAN_F1R1_FB2_Pos (2U) 3142 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) 3143 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk 3144 #define CAN_F1R1_FB3_Pos (3U) 3145 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) 3146 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk 3147 #define CAN_F1R1_FB4_Pos (4U) 3148 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) 3149 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk 3150 #define CAN_F1R1_FB5_Pos (5U) 3151 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) 3152 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk 3153 #define CAN_F1R1_FB6_Pos (6U) 3154 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) 3155 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk 3156 #define CAN_F1R1_FB7_Pos (7U) 3157 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) 3158 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk 3159 #define CAN_F1R1_FB8_Pos (8U) 3160 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) 3161 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk 3162 #define CAN_F1R1_FB9_Pos (9U) 3163 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) 3164 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk 3165 #define CAN_F1R1_FB10_Pos (10U) 3166 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) 3167 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk 3168 #define CAN_F1R1_FB11_Pos (11U) 3169 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) 3170 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk 3171 #define CAN_F1R1_FB12_Pos (12U) 3172 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) 3173 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk 3174 #define CAN_F1R1_FB13_Pos (13U) 3175 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) 3176 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk 3177 #define CAN_F1R1_FB14_Pos (14U) 3178 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) 3179 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk 3180 #define CAN_F1R1_FB15_Pos (15U) 3181 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) 3182 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk 3183 #define CAN_F1R1_FB16_Pos (16U) 3184 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) 3185 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk 3186 #define CAN_F1R1_FB17_Pos (17U) 3187 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) 3188 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk 3189 #define CAN_F1R1_FB18_Pos (18U) 3190 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) 3191 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk 3192 #define CAN_F1R1_FB19_Pos (19U) 3193 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) 3194 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk 3195 #define CAN_F1R1_FB20_Pos (20U) 3196 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) 3197 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk 3198 #define CAN_F1R1_FB21_Pos (21U) 3199 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) 3200 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk 3201 #define CAN_F1R1_FB22_Pos (22U) 3202 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) 3203 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk 3204 #define CAN_F1R1_FB23_Pos (23U) 3205 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) 3206 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk 3207 #define CAN_F1R1_FB24_Pos (24U) 3208 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) 3209 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk 3210 #define CAN_F1R1_FB25_Pos (25U) 3211 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) 3212 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk 3213 #define CAN_F1R1_FB26_Pos (26U) 3214 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) 3215 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk 3216 #define CAN_F1R1_FB27_Pos (27U) 3217 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) 3218 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk 3219 #define CAN_F1R1_FB28_Pos (28U) 3220 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) 3221 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk 3222 #define CAN_F1R1_FB29_Pos (29U) 3223 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) 3224 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk 3225 #define CAN_F1R1_FB30_Pos (30U) 3226 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) 3227 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk 3228 #define CAN_F1R1_FB31_Pos (31U) 3229 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) 3230 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk 3233 #define CAN_F2R1_FB0_Pos (0U) 3234 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) 3235 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk 3236 #define CAN_F2R1_FB1_Pos (1U) 3237 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) 3238 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk 3239 #define CAN_F2R1_FB2_Pos (2U) 3240 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) 3241 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk 3242 #define CAN_F2R1_FB3_Pos (3U) 3243 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) 3244 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk 3245 #define CAN_F2R1_FB4_Pos (4U) 3246 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) 3247 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk 3248 #define CAN_F2R1_FB5_Pos (5U) 3249 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) 3250 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk 3251 #define CAN_F2R1_FB6_Pos (6U) 3252 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) 3253 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk 3254 #define CAN_F2R1_FB7_Pos (7U) 3255 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) 3256 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk 3257 #define CAN_F2R1_FB8_Pos (8U) 3258 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) 3259 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk 3260 #define CAN_F2R1_FB9_Pos (9U) 3261 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) 3262 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk 3263 #define CAN_F2R1_FB10_Pos (10U) 3264 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) 3265 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk 3266 #define CAN_F2R1_FB11_Pos (11U) 3267 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) 3268 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk 3269 #define CAN_F2R1_FB12_Pos (12U) 3270 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) 3271 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk 3272 #define CAN_F2R1_FB13_Pos (13U) 3273 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) 3274 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk 3275 #define CAN_F2R1_FB14_Pos (14U) 3276 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) 3277 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk 3278 #define CAN_F2R1_FB15_Pos (15U) 3279 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) 3280 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk 3281 #define CAN_F2R1_FB16_Pos (16U) 3282 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) 3283 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk 3284 #define CAN_F2R1_FB17_Pos (17U) 3285 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) 3286 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk 3287 #define CAN_F2R1_FB18_Pos (18U) 3288 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) 3289 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk 3290 #define CAN_F2R1_FB19_Pos (19U) 3291 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) 3292 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk 3293 #define CAN_F2R1_FB20_Pos (20U) 3294 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) 3295 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk 3296 #define CAN_F2R1_FB21_Pos (21U) 3297 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) 3298 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk 3299 #define CAN_F2R1_FB22_Pos (22U) 3300 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) 3301 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk 3302 #define CAN_F2R1_FB23_Pos (23U) 3303 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) 3304 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk 3305 #define CAN_F2R1_FB24_Pos (24U) 3306 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) 3307 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk 3308 #define CAN_F2R1_FB25_Pos (25U) 3309 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) 3310 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk 3311 #define CAN_F2R1_FB26_Pos (26U) 3312 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) 3313 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk 3314 #define CAN_F2R1_FB27_Pos (27U) 3315 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) 3316 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk 3317 #define CAN_F2R1_FB28_Pos (28U) 3318 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) 3319 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk 3320 #define CAN_F2R1_FB29_Pos (29U) 3321 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) 3322 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk 3323 #define CAN_F2R1_FB30_Pos (30U) 3324 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) 3325 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk 3326 #define CAN_F2R1_FB31_Pos (31U) 3327 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) 3328 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk 3331 #define CAN_F3R1_FB0_Pos (0U) 3332 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) 3333 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk 3334 #define CAN_F3R1_FB1_Pos (1U) 3335 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) 3336 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk 3337 #define CAN_F3R1_FB2_Pos (2U) 3338 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) 3339 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk 3340 #define CAN_F3R1_FB3_Pos (3U) 3341 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) 3342 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk 3343 #define CAN_F3R1_FB4_Pos (4U) 3344 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) 3345 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk 3346 #define CAN_F3R1_FB5_Pos (5U) 3347 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) 3348 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk 3349 #define CAN_F3R1_FB6_Pos (6U) 3350 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) 3351 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk 3352 #define CAN_F3R1_FB7_Pos (7U) 3353 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) 3354 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk 3355 #define CAN_F3R1_FB8_Pos (8U) 3356 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) 3357 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk 3358 #define CAN_F3R1_FB9_Pos (9U) 3359 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) 3360 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk 3361 #define CAN_F3R1_FB10_Pos (10U) 3362 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) 3363 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk 3364 #define CAN_F3R1_FB11_Pos (11U) 3365 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) 3366 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk 3367 #define CAN_F3R1_FB12_Pos (12U) 3368 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) 3369 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk 3370 #define CAN_F3R1_FB13_Pos (13U) 3371 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) 3372 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk 3373 #define CAN_F3R1_FB14_Pos (14U) 3374 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) 3375 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk 3376 #define CAN_F3R1_FB15_Pos (15U) 3377 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) 3378 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk 3379 #define CAN_F3R1_FB16_Pos (16U) 3380 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) 3381 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk 3382 #define CAN_F3R1_FB17_Pos (17U) 3383 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) 3384 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk 3385 #define CAN_F3R1_FB18_Pos (18U) 3386 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) 3387 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk 3388 #define CAN_F3R1_FB19_Pos (19U) 3389 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) 3390 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk 3391 #define CAN_F3R1_FB20_Pos (20U) 3392 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) 3393 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk 3394 #define CAN_F3R1_FB21_Pos (21U) 3395 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) 3396 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk 3397 #define CAN_F3R1_FB22_Pos (22U) 3398 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) 3399 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk 3400 #define CAN_F3R1_FB23_Pos (23U) 3401 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) 3402 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk 3403 #define CAN_F3R1_FB24_Pos (24U) 3404 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) 3405 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk 3406 #define CAN_F3R1_FB25_Pos (25U) 3407 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) 3408 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk 3409 #define CAN_F3R1_FB26_Pos (26U) 3410 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) 3411 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk 3412 #define CAN_F3R1_FB27_Pos (27U) 3413 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) 3414 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk 3415 #define CAN_F3R1_FB28_Pos (28U) 3416 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) 3417 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk 3418 #define CAN_F3R1_FB29_Pos (29U) 3419 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) 3420 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk 3421 #define CAN_F3R1_FB30_Pos (30U) 3422 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) 3423 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk 3424 #define CAN_F3R1_FB31_Pos (31U) 3425 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) 3426 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk 3429 #define CAN_F4R1_FB0_Pos (0U) 3430 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) 3431 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk 3432 #define CAN_F4R1_FB1_Pos (1U) 3433 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) 3434 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk 3435 #define CAN_F4R1_FB2_Pos (2U) 3436 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) 3437 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk 3438 #define CAN_F4R1_FB3_Pos (3U) 3439 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) 3440 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk 3441 #define CAN_F4R1_FB4_Pos (4U) 3442 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) 3443 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk 3444 #define CAN_F4R1_FB5_Pos (5U) 3445 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) 3446 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk 3447 #define CAN_F4R1_FB6_Pos (6U) 3448 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) 3449 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk 3450 #define CAN_F4R1_FB7_Pos (7U) 3451 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) 3452 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk 3453 #define CAN_F4R1_FB8_Pos (8U) 3454 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) 3455 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk 3456 #define CAN_F4R1_FB9_Pos (9U) 3457 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) 3458 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk 3459 #define CAN_F4R1_FB10_Pos (10U) 3460 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) 3461 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk 3462 #define CAN_F4R1_FB11_Pos (11U) 3463 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) 3464 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk 3465 #define CAN_F4R1_FB12_Pos (12U) 3466 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) 3467 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk 3468 #define CAN_F4R1_FB13_Pos (13U) 3469 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) 3470 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk 3471 #define CAN_F4R1_FB14_Pos (14U) 3472 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) 3473 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk 3474 #define CAN_F4R1_FB15_Pos (15U) 3475 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) 3476 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk 3477 #define CAN_F4R1_FB16_Pos (16U) 3478 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) 3479 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk 3480 #define CAN_F4R1_FB17_Pos (17U) 3481 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) 3482 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk 3483 #define CAN_F4R1_FB18_Pos (18U) 3484 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) 3485 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk 3486 #define CAN_F4R1_FB19_Pos (19U) 3487 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) 3488 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk 3489 #define CAN_F4R1_FB20_Pos (20U) 3490 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) 3491 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk 3492 #define CAN_F4R1_FB21_Pos (21U) 3493 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) 3494 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk 3495 #define CAN_F4R1_FB22_Pos (22U) 3496 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) 3497 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk 3498 #define CAN_F4R1_FB23_Pos (23U) 3499 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) 3500 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk 3501 #define CAN_F4R1_FB24_Pos (24U) 3502 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) 3503 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk 3504 #define CAN_F4R1_FB25_Pos (25U) 3505 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) 3506 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk 3507 #define CAN_F4R1_FB26_Pos (26U) 3508 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) 3509 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk 3510 #define CAN_F4R1_FB27_Pos (27U) 3511 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) 3512 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk 3513 #define CAN_F4R1_FB28_Pos (28U) 3514 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) 3515 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk 3516 #define CAN_F4R1_FB29_Pos (29U) 3517 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) 3518 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk 3519 #define CAN_F4R1_FB30_Pos (30U) 3520 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) 3521 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk 3522 #define CAN_F4R1_FB31_Pos (31U) 3523 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) 3524 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk 3527 #define CAN_F5R1_FB0_Pos (0U) 3528 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) 3529 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk 3530 #define CAN_F5R1_FB1_Pos (1U) 3531 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) 3532 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk 3533 #define CAN_F5R1_FB2_Pos (2U) 3534 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) 3535 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk 3536 #define CAN_F5R1_FB3_Pos (3U) 3537 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) 3538 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk 3539 #define CAN_F5R1_FB4_Pos (4U) 3540 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) 3541 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk 3542 #define CAN_F5R1_FB5_Pos (5U) 3543 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) 3544 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk 3545 #define CAN_F5R1_FB6_Pos (6U) 3546 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) 3547 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk 3548 #define CAN_F5R1_FB7_Pos (7U) 3549 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) 3550 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk 3551 #define CAN_F5R1_FB8_Pos (8U) 3552 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) 3553 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk 3554 #define CAN_F5R1_FB9_Pos (9U) 3555 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) 3556 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk 3557 #define CAN_F5R1_FB10_Pos (10U) 3558 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) 3559 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk 3560 #define CAN_F5R1_FB11_Pos (11U) 3561 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) 3562 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk 3563 #define CAN_F5R1_FB12_Pos (12U) 3564 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) 3565 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk 3566 #define CAN_F5R1_FB13_Pos (13U) 3567 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) 3568 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk 3569 #define CAN_F5R1_FB14_Pos (14U) 3570 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) 3571 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk 3572 #define CAN_F5R1_FB15_Pos (15U) 3573 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) 3574 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk 3575 #define CAN_F5R1_FB16_Pos (16U) 3576 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) 3577 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk 3578 #define CAN_F5R1_FB17_Pos (17U) 3579 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) 3580 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk 3581 #define CAN_F5R1_FB18_Pos (18U) 3582 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) 3583 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk 3584 #define CAN_F5R1_FB19_Pos (19U) 3585 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) 3586 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk 3587 #define CAN_F5R1_FB20_Pos (20U) 3588 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) 3589 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk 3590 #define CAN_F5R1_FB21_Pos (21U) 3591 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) 3592 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk 3593 #define CAN_F5R1_FB22_Pos (22U) 3594 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) 3595 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk 3596 #define CAN_F5R1_FB23_Pos (23U) 3597 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) 3598 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk 3599 #define CAN_F5R1_FB24_Pos (24U) 3600 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) 3601 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk 3602 #define CAN_F5R1_FB25_Pos (25U) 3603 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) 3604 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk 3605 #define CAN_F5R1_FB26_Pos (26U) 3606 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) 3607 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk 3608 #define CAN_F5R1_FB27_Pos (27U) 3609 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) 3610 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk 3611 #define CAN_F5R1_FB28_Pos (28U) 3612 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) 3613 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk 3614 #define CAN_F5R1_FB29_Pos (29U) 3615 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) 3616 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk 3617 #define CAN_F5R1_FB30_Pos (30U) 3618 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) 3619 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk 3620 #define CAN_F5R1_FB31_Pos (31U) 3621 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) 3622 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk 3625 #define CAN_F6R1_FB0_Pos (0U) 3626 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) 3627 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk 3628 #define CAN_F6R1_FB1_Pos (1U) 3629 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) 3630 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk 3631 #define CAN_F6R1_FB2_Pos (2U) 3632 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) 3633 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk 3634 #define CAN_F6R1_FB3_Pos (3U) 3635 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) 3636 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk 3637 #define CAN_F6R1_FB4_Pos (4U) 3638 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) 3639 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk 3640 #define CAN_F6R1_FB5_Pos (5U) 3641 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) 3642 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk 3643 #define CAN_F6R1_FB6_Pos (6U) 3644 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) 3645 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk 3646 #define CAN_F6R1_FB7_Pos (7U) 3647 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) 3648 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk 3649 #define CAN_F6R1_FB8_Pos (8U) 3650 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) 3651 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk 3652 #define CAN_F6R1_FB9_Pos (9U) 3653 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) 3654 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk 3655 #define CAN_F6R1_FB10_Pos (10U) 3656 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) 3657 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk 3658 #define CAN_F6R1_FB11_Pos (11U) 3659 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) 3660 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk 3661 #define CAN_F6R1_FB12_Pos (12U) 3662 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) 3663 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk 3664 #define CAN_F6R1_FB13_Pos (13U) 3665 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) 3666 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk 3667 #define CAN_F6R1_FB14_Pos (14U) 3668 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) 3669 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk 3670 #define CAN_F6R1_FB15_Pos (15U) 3671 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) 3672 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk 3673 #define CAN_F6R1_FB16_Pos (16U) 3674 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) 3675 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk 3676 #define CAN_F6R1_FB17_Pos (17U) 3677 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) 3678 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk 3679 #define CAN_F6R1_FB18_Pos (18U) 3680 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) 3681 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk 3682 #define CAN_F6R1_FB19_Pos (19U) 3683 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) 3684 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk 3685 #define CAN_F6R1_FB20_Pos (20U) 3686 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) 3687 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk 3688 #define CAN_F6R1_FB21_Pos (21U) 3689 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) 3690 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk 3691 #define CAN_F6R1_FB22_Pos (22U) 3692 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) 3693 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk 3694 #define CAN_F6R1_FB23_Pos (23U) 3695 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) 3696 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk 3697 #define CAN_F6R1_FB24_Pos (24U) 3698 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) 3699 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk 3700 #define CAN_F6R1_FB25_Pos (25U) 3701 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) 3702 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk 3703 #define CAN_F6R1_FB26_Pos (26U) 3704 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) 3705 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk 3706 #define CAN_F6R1_FB27_Pos (27U) 3707 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) 3708 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk 3709 #define CAN_F6R1_FB28_Pos (28U) 3710 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) 3711 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk 3712 #define CAN_F6R1_FB29_Pos (29U) 3713 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) 3714 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk 3715 #define CAN_F6R1_FB30_Pos (30U) 3716 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) 3717 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk 3718 #define CAN_F6R1_FB31_Pos (31U) 3719 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) 3720 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk 3723 #define CAN_F7R1_FB0_Pos (0U) 3724 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) 3725 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk 3726 #define CAN_F7R1_FB1_Pos (1U) 3727 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) 3728 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk 3729 #define CAN_F7R1_FB2_Pos (2U) 3730 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) 3731 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk 3732 #define CAN_F7R1_FB3_Pos (3U) 3733 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) 3734 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk 3735 #define CAN_F7R1_FB4_Pos (4U) 3736 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) 3737 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk 3738 #define CAN_F7R1_FB5_Pos (5U) 3739 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) 3740 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk 3741 #define CAN_F7R1_FB6_Pos (6U) 3742 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) 3743 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk 3744 #define CAN_F7R1_FB7_Pos (7U) 3745 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) 3746 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk 3747 #define CAN_F7R1_FB8_Pos (8U) 3748 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) 3749 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk 3750 #define CAN_F7R1_FB9_Pos (9U) 3751 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) 3752 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk 3753 #define CAN_F7R1_FB10_Pos (10U) 3754 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) 3755 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk 3756 #define CAN_F7R1_FB11_Pos (11U) 3757 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) 3758 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk 3759 #define CAN_F7R1_FB12_Pos (12U) 3760 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) 3761 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk 3762 #define CAN_F7R1_FB13_Pos (13U) 3763 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) 3764 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk 3765 #define CAN_F7R1_FB14_Pos (14U) 3766 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) 3767 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk 3768 #define CAN_F7R1_FB15_Pos (15U) 3769 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) 3770 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk 3771 #define CAN_F7R1_FB16_Pos (16U) 3772 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) 3773 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk 3774 #define CAN_F7R1_FB17_Pos (17U) 3775 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) 3776 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk 3777 #define CAN_F7R1_FB18_Pos (18U) 3778 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) 3779 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk 3780 #define CAN_F7R1_FB19_Pos (19U) 3781 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) 3782 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk 3783 #define CAN_F7R1_FB20_Pos (20U) 3784 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) 3785 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk 3786 #define CAN_F7R1_FB21_Pos (21U) 3787 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) 3788 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk 3789 #define CAN_F7R1_FB22_Pos (22U) 3790 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) 3791 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk 3792 #define CAN_F7R1_FB23_Pos (23U) 3793 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) 3794 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk 3795 #define CAN_F7R1_FB24_Pos (24U) 3796 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) 3797 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk 3798 #define CAN_F7R1_FB25_Pos (25U) 3799 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) 3800 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk 3801 #define CAN_F7R1_FB26_Pos (26U) 3802 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) 3803 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk 3804 #define CAN_F7R1_FB27_Pos (27U) 3805 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) 3806 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk 3807 #define CAN_F7R1_FB28_Pos (28U) 3808 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) 3809 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk 3810 #define CAN_F7R1_FB29_Pos (29U) 3811 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) 3812 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk 3813 #define CAN_F7R1_FB30_Pos (30U) 3814 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) 3815 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk 3816 #define CAN_F7R1_FB31_Pos (31U) 3817 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) 3818 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk 3821 #define CAN_F8R1_FB0_Pos (0U) 3822 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) 3823 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk 3824 #define CAN_F8R1_FB1_Pos (1U) 3825 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) 3826 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk 3827 #define CAN_F8R1_FB2_Pos (2U) 3828 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) 3829 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk 3830 #define CAN_F8R1_FB3_Pos (3U) 3831 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) 3832 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk 3833 #define CAN_F8R1_FB4_Pos (4U) 3834 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) 3835 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk 3836 #define CAN_F8R1_FB5_Pos (5U) 3837 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) 3838 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk 3839 #define CAN_F8R1_FB6_Pos (6U) 3840 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) 3841 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk 3842 #define CAN_F8R1_FB7_Pos (7U) 3843 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) 3844 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk 3845 #define CAN_F8R1_FB8_Pos (8U) 3846 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) 3847 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk 3848 #define CAN_F8R1_FB9_Pos (9U) 3849 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) 3850 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk 3851 #define CAN_F8R1_FB10_Pos (10U) 3852 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) 3853 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk 3854 #define CAN_F8R1_FB11_Pos (11U) 3855 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) 3856 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk 3857 #define CAN_F8R1_FB12_Pos (12U) 3858 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) 3859 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk 3860 #define CAN_F8R1_FB13_Pos (13U) 3861 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) 3862 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk 3863 #define CAN_F8R1_FB14_Pos (14U) 3864 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) 3865 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk 3866 #define CAN_F8R1_FB15_Pos (15U) 3867 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) 3868 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk 3869 #define CAN_F8R1_FB16_Pos (16U) 3870 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) 3871 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk 3872 #define CAN_F8R1_FB17_Pos (17U) 3873 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) 3874 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk 3875 #define CAN_F8R1_FB18_Pos (18U) 3876 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) 3877 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk 3878 #define CAN_F8R1_FB19_Pos (19U) 3879 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) 3880 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk 3881 #define CAN_F8R1_FB20_Pos (20U) 3882 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) 3883 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk 3884 #define CAN_F8R1_FB21_Pos (21U) 3885 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) 3886 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk 3887 #define CAN_F8R1_FB22_Pos (22U) 3888 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) 3889 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk 3890 #define CAN_F8R1_FB23_Pos (23U) 3891 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) 3892 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk 3893 #define CAN_F8R1_FB24_Pos (24U) 3894 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) 3895 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk 3896 #define CAN_F8R1_FB25_Pos (25U) 3897 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) 3898 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk 3899 #define CAN_F8R1_FB26_Pos (26U) 3900 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) 3901 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk 3902 #define CAN_F8R1_FB27_Pos (27U) 3903 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) 3904 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk 3905 #define CAN_F8R1_FB28_Pos (28U) 3906 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) 3907 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk 3908 #define CAN_F8R1_FB29_Pos (29U) 3909 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) 3910 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk 3911 #define CAN_F8R1_FB30_Pos (30U) 3912 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) 3913 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk 3914 #define CAN_F8R1_FB31_Pos (31U) 3915 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) 3916 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk 3919 #define CAN_F9R1_FB0_Pos (0U) 3920 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) 3921 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk 3922 #define CAN_F9R1_FB1_Pos (1U) 3923 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) 3924 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk 3925 #define CAN_F9R1_FB2_Pos (2U) 3926 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) 3927 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk 3928 #define CAN_F9R1_FB3_Pos (3U) 3929 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) 3930 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk 3931 #define CAN_F9R1_FB4_Pos (4U) 3932 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) 3933 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk 3934 #define CAN_F9R1_FB5_Pos (5U) 3935 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) 3936 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk 3937 #define CAN_F9R1_FB6_Pos (6U) 3938 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) 3939 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk 3940 #define CAN_F9R1_FB7_Pos (7U) 3941 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) 3942 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk 3943 #define CAN_F9R1_FB8_Pos (8U) 3944 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) 3945 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk 3946 #define CAN_F9R1_FB9_Pos (9U) 3947 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) 3948 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk 3949 #define CAN_F9R1_FB10_Pos (10U) 3950 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) 3951 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk 3952 #define CAN_F9R1_FB11_Pos (11U) 3953 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) 3954 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk 3955 #define CAN_F9R1_FB12_Pos (12U) 3956 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) 3957 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk 3958 #define CAN_F9R1_FB13_Pos (13U) 3959 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) 3960 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk 3961 #define CAN_F9R1_FB14_Pos (14U) 3962 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) 3963 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk 3964 #define CAN_F9R1_FB15_Pos (15U) 3965 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) 3966 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk 3967 #define CAN_F9R1_FB16_Pos (16U) 3968 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) 3969 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk 3970 #define CAN_F9R1_FB17_Pos (17U) 3971 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) 3972 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk 3973 #define CAN_F9R1_FB18_Pos (18U) 3974 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) 3975 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk 3976 #define CAN_F9R1_FB19_Pos (19U) 3977 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) 3978 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk 3979 #define CAN_F9R1_FB20_Pos (20U) 3980 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) 3981 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk 3982 #define CAN_F9R1_FB21_Pos (21U) 3983 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) 3984 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk 3985 #define CAN_F9R1_FB22_Pos (22U) 3986 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) 3987 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk 3988 #define CAN_F9R1_FB23_Pos (23U) 3989 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) 3990 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk 3991 #define CAN_F9R1_FB24_Pos (24U) 3992 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) 3993 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk 3994 #define CAN_F9R1_FB25_Pos (25U) 3995 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) 3996 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk 3997 #define CAN_F9R1_FB26_Pos (26U) 3998 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) 3999 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk 4000 #define CAN_F9R1_FB27_Pos (27U) 4001 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) 4002 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk 4003 #define CAN_F9R1_FB28_Pos (28U) 4004 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) 4005 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk 4006 #define CAN_F9R1_FB29_Pos (29U) 4007 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) 4008 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk 4009 #define CAN_F9R1_FB30_Pos (30U) 4010 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) 4011 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk 4012 #define CAN_F9R1_FB31_Pos (31U) 4013 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) 4014 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk 4017 #define CAN_F10R1_FB0_Pos (0U) 4018 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) 4019 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk 4020 #define CAN_F10R1_FB1_Pos (1U) 4021 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) 4022 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk 4023 #define CAN_F10R1_FB2_Pos (2U) 4024 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) 4025 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk 4026 #define CAN_F10R1_FB3_Pos (3U) 4027 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) 4028 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk 4029 #define CAN_F10R1_FB4_Pos (4U) 4030 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) 4031 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk 4032 #define CAN_F10R1_FB5_Pos (5U) 4033 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) 4034 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk 4035 #define CAN_F10R1_FB6_Pos (6U) 4036 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) 4037 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk 4038 #define CAN_F10R1_FB7_Pos (7U) 4039 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) 4040 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk 4041 #define CAN_F10R1_FB8_Pos (8U) 4042 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) 4043 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk 4044 #define CAN_F10R1_FB9_Pos (9U) 4045 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) 4046 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk 4047 #define CAN_F10R1_FB10_Pos (10U) 4048 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) 4049 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk 4050 #define CAN_F10R1_FB11_Pos (11U) 4051 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) 4052 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk 4053 #define CAN_F10R1_FB12_Pos (12U) 4054 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) 4055 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk 4056 #define CAN_F10R1_FB13_Pos (13U) 4057 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) 4058 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk 4059 #define CAN_F10R1_FB14_Pos (14U) 4060 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) 4061 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk 4062 #define CAN_F10R1_FB15_Pos (15U) 4063 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) 4064 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk 4065 #define CAN_F10R1_FB16_Pos (16U) 4066 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) 4067 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk 4068 #define CAN_F10R1_FB17_Pos (17U) 4069 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) 4070 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk 4071 #define CAN_F10R1_FB18_Pos (18U) 4072 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) 4073 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk 4074 #define CAN_F10R1_FB19_Pos (19U) 4075 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) 4076 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk 4077 #define CAN_F10R1_FB20_Pos (20U) 4078 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) 4079 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk 4080 #define CAN_F10R1_FB21_Pos (21U) 4081 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) 4082 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk 4083 #define CAN_F10R1_FB22_Pos (22U) 4084 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) 4085 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk 4086 #define CAN_F10R1_FB23_Pos (23U) 4087 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) 4088 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk 4089 #define CAN_F10R1_FB24_Pos (24U) 4090 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) 4091 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk 4092 #define CAN_F10R1_FB25_Pos (25U) 4093 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) 4094 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk 4095 #define CAN_F10R1_FB26_Pos (26U) 4096 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) 4097 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk 4098 #define CAN_F10R1_FB27_Pos (27U) 4099 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) 4100 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk 4101 #define CAN_F10R1_FB28_Pos (28U) 4102 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) 4103 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk 4104 #define CAN_F10R1_FB29_Pos (29U) 4105 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) 4106 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk 4107 #define CAN_F10R1_FB30_Pos (30U) 4108 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) 4109 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk 4110 #define CAN_F10R1_FB31_Pos (31U) 4111 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) 4112 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk 4115 #define CAN_F11R1_FB0_Pos (0U) 4116 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) 4117 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk 4118 #define CAN_F11R1_FB1_Pos (1U) 4119 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) 4120 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk 4121 #define CAN_F11R1_FB2_Pos (2U) 4122 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) 4123 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk 4124 #define CAN_F11R1_FB3_Pos (3U) 4125 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) 4126 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk 4127 #define CAN_F11R1_FB4_Pos (4U) 4128 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) 4129 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk 4130 #define CAN_F11R1_FB5_Pos (5U) 4131 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) 4132 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk 4133 #define CAN_F11R1_FB6_Pos (6U) 4134 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) 4135 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk 4136 #define CAN_F11R1_FB7_Pos (7U) 4137 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) 4138 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk 4139 #define CAN_F11R1_FB8_Pos (8U) 4140 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) 4141 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk 4142 #define CAN_F11R1_FB9_Pos (9U) 4143 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) 4144 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk 4145 #define CAN_F11R1_FB10_Pos (10U) 4146 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) 4147 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk 4148 #define CAN_F11R1_FB11_Pos (11U) 4149 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) 4150 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk 4151 #define CAN_F11R1_FB12_Pos (12U) 4152 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) 4153 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk 4154 #define CAN_F11R1_FB13_Pos (13U) 4155 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) 4156 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk 4157 #define CAN_F11R1_FB14_Pos (14U) 4158 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) 4159 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk 4160 #define CAN_F11R1_FB15_Pos (15U) 4161 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) 4162 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk 4163 #define CAN_F11R1_FB16_Pos (16U) 4164 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) 4165 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk 4166 #define CAN_F11R1_FB17_Pos (17U) 4167 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) 4168 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk 4169 #define CAN_F11R1_FB18_Pos (18U) 4170 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) 4171 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk 4172 #define CAN_F11R1_FB19_Pos (19U) 4173 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) 4174 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk 4175 #define CAN_F11R1_FB20_Pos (20U) 4176 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) 4177 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk 4178 #define CAN_F11R1_FB21_Pos (21U) 4179 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) 4180 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk 4181 #define CAN_F11R1_FB22_Pos (22U) 4182 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) 4183 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk 4184 #define CAN_F11R1_FB23_Pos (23U) 4185 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) 4186 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk 4187 #define CAN_F11R1_FB24_Pos (24U) 4188 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) 4189 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk 4190 #define CAN_F11R1_FB25_Pos (25U) 4191 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) 4192 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk 4193 #define CAN_F11R1_FB26_Pos (26U) 4194 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) 4195 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk 4196 #define CAN_F11R1_FB27_Pos (27U) 4197 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) 4198 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk 4199 #define CAN_F11R1_FB28_Pos (28U) 4200 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) 4201 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk 4202 #define CAN_F11R1_FB29_Pos (29U) 4203 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) 4204 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk 4205 #define CAN_F11R1_FB30_Pos (30U) 4206 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) 4207 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk 4208 #define CAN_F11R1_FB31_Pos (31U) 4209 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) 4210 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk 4213 #define CAN_F12R1_FB0_Pos (0U) 4214 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) 4215 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk 4216 #define CAN_F12R1_FB1_Pos (1U) 4217 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) 4218 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk 4219 #define CAN_F12R1_FB2_Pos (2U) 4220 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) 4221 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk 4222 #define CAN_F12R1_FB3_Pos (3U) 4223 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) 4224 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk 4225 #define CAN_F12R1_FB4_Pos (4U) 4226 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) 4227 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk 4228 #define CAN_F12R1_FB5_Pos (5U) 4229 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) 4230 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk 4231 #define CAN_F12R1_FB6_Pos (6U) 4232 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) 4233 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk 4234 #define CAN_F12R1_FB7_Pos (7U) 4235 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) 4236 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk 4237 #define CAN_F12R1_FB8_Pos (8U) 4238 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) 4239 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk 4240 #define CAN_F12R1_FB9_Pos (9U) 4241 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) 4242 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk 4243 #define CAN_F12R1_FB10_Pos (10U) 4244 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) 4245 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk 4246 #define CAN_F12R1_FB11_Pos (11U) 4247 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) 4248 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk 4249 #define CAN_F12R1_FB12_Pos (12U) 4250 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) 4251 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk 4252 #define CAN_F12R1_FB13_Pos (13U) 4253 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) 4254 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk 4255 #define CAN_F12R1_FB14_Pos (14U) 4256 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) 4257 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk 4258 #define CAN_F12R1_FB15_Pos (15U) 4259 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) 4260 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk 4261 #define CAN_F12R1_FB16_Pos (16U) 4262 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) 4263 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk 4264 #define CAN_F12R1_FB17_Pos (17U) 4265 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) 4266 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk 4267 #define CAN_F12R1_FB18_Pos (18U) 4268 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) 4269 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk 4270 #define CAN_F12R1_FB19_Pos (19U) 4271 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) 4272 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk 4273 #define CAN_F12R1_FB20_Pos (20U) 4274 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) 4275 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk 4276 #define CAN_F12R1_FB21_Pos (21U) 4277 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) 4278 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk 4279 #define CAN_F12R1_FB22_Pos (22U) 4280 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) 4281 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk 4282 #define CAN_F12R1_FB23_Pos (23U) 4283 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) 4284 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk 4285 #define CAN_F12R1_FB24_Pos (24U) 4286 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) 4287 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk 4288 #define CAN_F12R1_FB25_Pos (25U) 4289 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) 4290 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk 4291 #define CAN_F12R1_FB26_Pos (26U) 4292 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) 4293 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk 4294 #define CAN_F12R1_FB27_Pos (27U) 4295 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) 4296 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk 4297 #define CAN_F12R1_FB28_Pos (28U) 4298 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) 4299 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk 4300 #define CAN_F12R1_FB29_Pos (29U) 4301 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) 4302 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk 4303 #define CAN_F12R1_FB30_Pos (30U) 4304 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) 4305 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk 4306 #define CAN_F12R1_FB31_Pos (31U) 4307 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) 4308 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk 4311 #define CAN_F13R1_FB0_Pos (0U) 4312 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) 4313 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk 4314 #define CAN_F13R1_FB1_Pos (1U) 4315 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) 4316 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk 4317 #define CAN_F13R1_FB2_Pos (2U) 4318 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) 4319 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk 4320 #define CAN_F13R1_FB3_Pos (3U) 4321 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) 4322 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk 4323 #define CAN_F13R1_FB4_Pos (4U) 4324 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) 4325 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk 4326 #define CAN_F13R1_FB5_Pos (5U) 4327 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) 4328 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk 4329 #define CAN_F13R1_FB6_Pos (6U) 4330 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) 4331 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk 4332 #define CAN_F13R1_FB7_Pos (7U) 4333 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) 4334 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk 4335 #define CAN_F13R1_FB8_Pos (8U) 4336 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) 4337 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk 4338 #define CAN_F13R1_FB9_Pos (9U) 4339 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) 4340 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk 4341 #define CAN_F13R1_FB10_Pos (10U) 4342 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) 4343 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk 4344 #define CAN_F13R1_FB11_Pos (11U) 4345 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) 4346 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk 4347 #define CAN_F13R1_FB12_Pos (12U) 4348 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) 4349 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk 4350 #define CAN_F13R1_FB13_Pos (13U) 4351 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) 4352 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk 4353 #define CAN_F13R1_FB14_Pos (14U) 4354 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) 4355 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk 4356 #define CAN_F13R1_FB15_Pos (15U) 4357 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) 4358 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk 4359 #define CAN_F13R1_FB16_Pos (16U) 4360 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) 4361 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk 4362 #define CAN_F13R1_FB17_Pos (17U) 4363 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) 4364 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk 4365 #define CAN_F13R1_FB18_Pos (18U) 4366 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) 4367 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk 4368 #define CAN_F13R1_FB19_Pos (19U) 4369 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) 4370 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk 4371 #define CAN_F13R1_FB20_Pos (20U) 4372 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) 4373 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk 4374 #define CAN_F13R1_FB21_Pos (21U) 4375 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) 4376 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk 4377 #define CAN_F13R1_FB22_Pos (22U) 4378 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) 4379 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk 4380 #define CAN_F13R1_FB23_Pos (23U) 4381 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) 4382 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk 4383 #define CAN_F13R1_FB24_Pos (24U) 4384 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) 4385 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk 4386 #define CAN_F13R1_FB25_Pos (25U) 4387 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) 4388 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk 4389 #define CAN_F13R1_FB26_Pos (26U) 4390 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) 4391 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk 4392 #define CAN_F13R1_FB27_Pos (27U) 4393 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) 4394 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk 4395 #define CAN_F13R1_FB28_Pos (28U) 4396 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) 4397 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk 4398 #define CAN_F13R1_FB29_Pos (29U) 4399 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) 4400 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk 4401 #define CAN_F13R1_FB30_Pos (30U) 4402 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) 4403 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk 4404 #define CAN_F13R1_FB31_Pos (31U) 4405 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) 4406 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk 4409 #define CAN_F0R2_FB0_Pos (0U) 4410 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) 4411 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk 4412 #define CAN_F0R2_FB1_Pos (1U) 4413 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) 4414 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk 4415 #define CAN_F0R2_FB2_Pos (2U) 4416 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) 4417 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk 4418 #define CAN_F0R2_FB3_Pos (3U) 4419 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) 4420 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk 4421 #define CAN_F0R2_FB4_Pos (4U) 4422 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) 4423 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk 4424 #define CAN_F0R2_FB5_Pos (5U) 4425 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) 4426 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk 4427 #define CAN_F0R2_FB6_Pos (6U) 4428 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) 4429 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk 4430 #define CAN_F0R2_FB7_Pos (7U) 4431 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) 4432 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk 4433 #define CAN_F0R2_FB8_Pos (8U) 4434 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) 4435 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk 4436 #define CAN_F0R2_FB9_Pos (9U) 4437 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) 4438 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk 4439 #define CAN_F0R2_FB10_Pos (10U) 4440 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) 4441 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk 4442 #define CAN_F0R2_FB11_Pos (11U) 4443 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) 4444 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk 4445 #define CAN_F0R2_FB12_Pos (12U) 4446 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) 4447 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk 4448 #define CAN_F0R2_FB13_Pos (13U) 4449 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) 4450 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk 4451 #define CAN_F0R2_FB14_Pos (14U) 4452 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) 4453 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk 4454 #define CAN_F0R2_FB15_Pos (15U) 4455 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) 4456 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk 4457 #define CAN_F0R2_FB16_Pos (16U) 4458 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) 4459 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk 4460 #define CAN_F0R2_FB17_Pos (17U) 4461 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) 4462 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk 4463 #define CAN_F0R2_FB18_Pos (18U) 4464 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) 4465 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk 4466 #define CAN_F0R2_FB19_Pos (19U) 4467 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) 4468 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk 4469 #define CAN_F0R2_FB20_Pos (20U) 4470 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) 4471 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk 4472 #define CAN_F0R2_FB21_Pos (21U) 4473 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) 4474 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk 4475 #define CAN_F0R2_FB22_Pos (22U) 4476 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) 4477 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk 4478 #define CAN_F0R2_FB23_Pos (23U) 4479 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) 4480 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk 4481 #define CAN_F0R2_FB24_Pos (24U) 4482 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) 4483 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk 4484 #define CAN_F0R2_FB25_Pos (25U) 4485 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) 4486 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk 4487 #define CAN_F0R2_FB26_Pos (26U) 4488 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) 4489 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk 4490 #define CAN_F0R2_FB27_Pos (27U) 4491 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) 4492 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk 4493 #define CAN_F0R2_FB28_Pos (28U) 4494 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) 4495 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk 4496 #define CAN_F0R2_FB29_Pos (29U) 4497 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) 4498 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk 4499 #define CAN_F0R2_FB30_Pos (30U) 4500 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) 4501 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk 4502 #define CAN_F0R2_FB31_Pos (31U) 4503 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) 4504 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk 4507 #define CAN_F1R2_FB0_Pos (0U) 4508 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) 4509 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk 4510 #define CAN_F1R2_FB1_Pos (1U) 4511 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) 4512 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk 4513 #define CAN_F1R2_FB2_Pos (2U) 4514 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) 4515 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk 4516 #define CAN_F1R2_FB3_Pos (3U) 4517 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) 4518 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk 4519 #define CAN_F1R2_FB4_Pos (4U) 4520 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) 4521 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk 4522 #define CAN_F1R2_FB5_Pos (5U) 4523 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) 4524 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk 4525 #define CAN_F1R2_FB6_Pos (6U) 4526 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) 4527 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk 4528 #define CAN_F1R2_FB7_Pos (7U) 4529 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) 4530 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk 4531 #define CAN_F1R2_FB8_Pos (8U) 4532 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) 4533 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk 4534 #define CAN_F1R2_FB9_Pos (9U) 4535 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) 4536 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk 4537 #define CAN_F1R2_FB10_Pos (10U) 4538 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) 4539 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk 4540 #define CAN_F1R2_FB11_Pos (11U) 4541 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) 4542 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk 4543 #define CAN_F1R2_FB12_Pos (12U) 4544 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) 4545 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk 4546 #define CAN_F1R2_FB13_Pos (13U) 4547 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) 4548 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk 4549 #define CAN_F1R2_FB14_Pos (14U) 4550 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) 4551 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk 4552 #define CAN_F1R2_FB15_Pos (15U) 4553 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) 4554 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk 4555 #define CAN_F1R2_FB16_Pos (16U) 4556 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) 4557 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk 4558 #define CAN_F1R2_FB17_Pos (17U) 4559 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) 4560 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk 4561 #define CAN_F1R2_FB18_Pos (18U) 4562 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) 4563 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk 4564 #define CAN_F1R2_FB19_Pos (19U) 4565 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) 4566 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk 4567 #define CAN_F1R2_FB20_Pos (20U) 4568 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) 4569 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk 4570 #define CAN_F1R2_FB21_Pos (21U) 4571 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) 4572 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk 4573 #define CAN_F1R2_FB22_Pos (22U) 4574 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) 4575 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk 4576 #define CAN_F1R2_FB23_Pos (23U) 4577 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) 4578 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk 4579 #define CAN_F1R2_FB24_Pos (24U) 4580 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) 4581 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk 4582 #define CAN_F1R2_FB25_Pos (25U) 4583 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) 4584 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk 4585 #define CAN_F1R2_FB26_Pos (26U) 4586 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) 4587 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk 4588 #define CAN_F1R2_FB27_Pos (27U) 4589 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) 4590 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk 4591 #define CAN_F1R2_FB28_Pos (28U) 4592 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) 4593 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk 4594 #define CAN_F1R2_FB29_Pos (29U) 4595 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) 4596 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk 4597 #define CAN_F1R2_FB30_Pos (30U) 4598 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) 4599 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk 4600 #define CAN_F1R2_FB31_Pos (31U) 4601 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) 4602 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk 4605 #define CAN_F2R2_FB0_Pos (0U) 4606 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) 4607 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk 4608 #define CAN_F2R2_FB1_Pos (1U) 4609 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) 4610 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk 4611 #define CAN_F2R2_FB2_Pos (2U) 4612 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) 4613 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk 4614 #define CAN_F2R2_FB3_Pos (3U) 4615 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) 4616 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk 4617 #define CAN_F2R2_FB4_Pos (4U) 4618 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) 4619 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk 4620 #define CAN_F2R2_FB5_Pos (5U) 4621 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) 4622 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk 4623 #define CAN_F2R2_FB6_Pos (6U) 4624 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) 4625 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk 4626 #define CAN_F2R2_FB7_Pos (7U) 4627 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) 4628 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk 4629 #define CAN_F2R2_FB8_Pos (8U) 4630 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) 4631 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk 4632 #define CAN_F2R2_FB9_Pos (9U) 4633 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) 4634 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk 4635 #define CAN_F2R2_FB10_Pos (10U) 4636 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) 4637 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk 4638 #define CAN_F2R2_FB11_Pos (11U) 4639 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) 4640 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk 4641 #define CAN_F2R2_FB12_Pos (12U) 4642 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) 4643 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk 4644 #define CAN_F2R2_FB13_Pos (13U) 4645 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) 4646 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk 4647 #define CAN_F2R2_FB14_Pos (14U) 4648 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) 4649 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk 4650 #define CAN_F2R2_FB15_Pos (15U) 4651 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) 4652 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk 4653 #define CAN_F2R2_FB16_Pos (16U) 4654 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) 4655 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk 4656 #define CAN_F2R2_FB17_Pos (17U) 4657 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) 4658 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk 4659 #define CAN_F2R2_FB18_Pos (18U) 4660 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) 4661 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk 4662 #define CAN_F2R2_FB19_Pos (19U) 4663 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) 4664 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk 4665 #define CAN_F2R2_FB20_Pos (20U) 4666 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) 4667 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk 4668 #define CAN_F2R2_FB21_Pos (21U) 4669 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) 4670 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk 4671 #define CAN_F2R2_FB22_Pos (22U) 4672 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) 4673 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk 4674 #define CAN_F2R2_FB23_Pos (23U) 4675 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) 4676 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk 4677 #define CAN_F2R2_FB24_Pos (24U) 4678 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) 4679 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk 4680 #define CAN_F2R2_FB25_Pos (25U) 4681 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) 4682 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk 4683 #define CAN_F2R2_FB26_Pos (26U) 4684 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) 4685 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk 4686 #define CAN_F2R2_FB27_Pos (27U) 4687 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) 4688 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk 4689 #define CAN_F2R2_FB28_Pos (28U) 4690 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) 4691 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk 4692 #define CAN_F2R2_FB29_Pos (29U) 4693 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) 4694 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk 4695 #define CAN_F2R2_FB30_Pos (30U) 4696 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) 4697 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk 4698 #define CAN_F2R2_FB31_Pos (31U) 4699 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) 4700 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk 4703 #define CAN_F3R2_FB0_Pos (0U) 4704 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) 4705 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk 4706 #define CAN_F3R2_FB1_Pos (1U) 4707 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) 4708 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk 4709 #define CAN_F3R2_FB2_Pos (2U) 4710 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) 4711 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk 4712 #define CAN_F3R2_FB3_Pos (3U) 4713 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) 4714 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk 4715 #define CAN_F3R2_FB4_Pos (4U) 4716 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) 4717 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk 4718 #define CAN_F3R2_FB5_Pos (5U) 4719 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) 4720 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk 4721 #define CAN_F3R2_FB6_Pos (6U) 4722 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) 4723 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk 4724 #define CAN_F3R2_FB7_Pos (7U) 4725 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) 4726 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk 4727 #define CAN_F3R2_FB8_Pos (8U) 4728 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) 4729 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk 4730 #define CAN_F3R2_FB9_Pos (9U) 4731 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) 4732 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk 4733 #define CAN_F3R2_FB10_Pos (10U) 4734 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) 4735 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk 4736 #define CAN_F3R2_FB11_Pos (11U) 4737 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) 4738 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk 4739 #define CAN_F3R2_FB12_Pos (12U) 4740 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) 4741 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk 4742 #define CAN_F3R2_FB13_Pos (13U) 4743 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) 4744 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk 4745 #define CAN_F3R2_FB14_Pos (14U) 4746 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) 4747 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk 4748 #define CAN_F3R2_FB15_Pos (15U) 4749 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) 4750 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk 4751 #define CAN_F3R2_FB16_Pos (16U) 4752 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) 4753 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk 4754 #define CAN_F3R2_FB17_Pos (17U) 4755 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) 4756 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk 4757 #define CAN_F3R2_FB18_Pos (18U) 4758 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) 4759 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk 4760 #define CAN_F3R2_FB19_Pos (19U) 4761 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) 4762 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk 4763 #define CAN_F3R2_FB20_Pos (20U) 4764 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) 4765 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk 4766 #define CAN_F3R2_FB21_Pos (21U) 4767 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) 4768 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk 4769 #define CAN_F3R2_FB22_Pos (22U) 4770 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) 4771 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk 4772 #define CAN_F3R2_FB23_Pos (23U) 4773 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) 4774 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk 4775 #define CAN_F3R2_FB24_Pos (24U) 4776 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) 4777 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk 4778 #define CAN_F3R2_FB25_Pos (25U) 4779 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) 4780 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk 4781 #define CAN_F3R2_FB26_Pos (26U) 4782 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) 4783 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk 4784 #define CAN_F3R2_FB27_Pos (27U) 4785 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) 4786 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk 4787 #define CAN_F3R2_FB28_Pos (28U) 4788 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) 4789 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk 4790 #define CAN_F3R2_FB29_Pos (29U) 4791 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) 4792 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk 4793 #define CAN_F3R2_FB30_Pos (30U) 4794 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) 4795 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk 4796 #define CAN_F3R2_FB31_Pos (31U) 4797 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) 4798 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk 4801 #define CAN_F4R2_FB0_Pos (0U) 4802 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) 4803 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk 4804 #define CAN_F4R2_FB1_Pos (1U) 4805 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) 4806 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk 4807 #define CAN_F4R2_FB2_Pos (2U) 4808 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) 4809 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk 4810 #define CAN_F4R2_FB3_Pos (3U) 4811 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) 4812 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk 4813 #define CAN_F4R2_FB4_Pos (4U) 4814 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) 4815 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk 4816 #define CAN_F4R2_FB5_Pos (5U) 4817 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) 4818 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk 4819 #define CAN_F4R2_FB6_Pos (6U) 4820 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) 4821 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk 4822 #define CAN_F4R2_FB7_Pos (7U) 4823 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) 4824 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk 4825 #define CAN_F4R2_FB8_Pos (8U) 4826 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) 4827 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk 4828 #define CAN_F4R2_FB9_Pos (9U) 4829 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) 4830 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk 4831 #define CAN_F4R2_FB10_Pos (10U) 4832 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) 4833 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk 4834 #define CAN_F4R2_FB11_Pos (11U) 4835 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) 4836 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk 4837 #define CAN_F4R2_FB12_Pos (12U) 4838 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) 4839 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk 4840 #define CAN_F4R2_FB13_Pos (13U) 4841 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) 4842 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk 4843 #define CAN_F4R2_FB14_Pos (14U) 4844 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) 4845 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk 4846 #define CAN_F4R2_FB15_Pos (15U) 4847 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) 4848 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk 4849 #define CAN_F4R2_FB16_Pos (16U) 4850 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) 4851 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk 4852 #define CAN_F4R2_FB17_Pos (17U) 4853 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) 4854 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk 4855 #define CAN_F4R2_FB18_Pos (18U) 4856 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) 4857 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk 4858 #define CAN_F4R2_FB19_Pos (19U) 4859 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) 4860 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk 4861 #define CAN_F4R2_FB20_Pos (20U) 4862 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) 4863 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk 4864 #define CAN_F4R2_FB21_Pos (21U) 4865 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) 4866 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk 4867 #define CAN_F4R2_FB22_Pos (22U) 4868 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) 4869 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk 4870 #define CAN_F4R2_FB23_Pos (23U) 4871 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) 4872 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk 4873 #define CAN_F4R2_FB24_Pos (24U) 4874 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) 4875 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk 4876 #define CAN_F4R2_FB25_Pos (25U) 4877 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) 4878 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk 4879 #define CAN_F4R2_FB26_Pos (26U) 4880 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) 4881 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk 4882 #define CAN_F4R2_FB27_Pos (27U) 4883 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) 4884 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk 4885 #define CAN_F4R2_FB28_Pos (28U) 4886 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) 4887 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk 4888 #define CAN_F4R2_FB29_Pos (29U) 4889 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) 4890 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk 4891 #define CAN_F4R2_FB30_Pos (30U) 4892 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) 4893 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk 4894 #define CAN_F4R2_FB31_Pos (31U) 4895 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) 4896 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk 4899 #define CAN_F5R2_FB0_Pos (0U) 4900 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) 4901 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk 4902 #define CAN_F5R2_FB1_Pos (1U) 4903 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) 4904 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk 4905 #define CAN_F5R2_FB2_Pos (2U) 4906 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) 4907 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk 4908 #define CAN_F5R2_FB3_Pos (3U) 4909 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) 4910 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk 4911 #define CAN_F5R2_FB4_Pos (4U) 4912 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) 4913 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk 4914 #define CAN_F5R2_FB5_Pos (5U) 4915 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) 4916 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk 4917 #define CAN_F5R2_FB6_Pos (6U) 4918 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) 4919 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk 4920 #define CAN_F5R2_FB7_Pos (7U) 4921 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) 4922 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk 4923 #define CAN_F5R2_FB8_Pos (8U) 4924 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) 4925 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk 4926 #define CAN_F5R2_FB9_Pos (9U) 4927 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) 4928 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk 4929 #define CAN_F5R2_FB10_Pos (10U) 4930 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) 4931 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk 4932 #define CAN_F5R2_FB11_Pos (11U) 4933 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) 4934 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk 4935 #define CAN_F5R2_FB12_Pos (12U) 4936 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) 4937 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk 4938 #define CAN_F5R2_FB13_Pos (13U) 4939 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) 4940 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk 4941 #define CAN_F5R2_FB14_Pos (14U) 4942 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) 4943 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk 4944 #define CAN_F5R2_FB15_Pos (15U) 4945 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) 4946 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk 4947 #define CAN_F5R2_FB16_Pos (16U) 4948 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) 4949 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk 4950 #define CAN_F5R2_FB17_Pos (17U) 4951 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) 4952 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk 4953 #define CAN_F5R2_FB18_Pos (18U) 4954 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) 4955 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk 4956 #define CAN_F5R2_FB19_Pos (19U) 4957 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) 4958 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk 4959 #define CAN_F5R2_FB20_Pos (20U) 4960 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) 4961 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk 4962 #define CAN_F5R2_FB21_Pos (21U) 4963 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) 4964 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk 4965 #define CAN_F5R2_FB22_Pos (22U) 4966 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) 4967 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk 4968 #define CAN_F5R2_FB23_Pos (23U) 4969 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) 4970 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk 4971 #define CAN_F5R2_FB24_Pos (24U) 4972 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) 4973 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk 4974 #define CAN_F5R2_FB25_Pos (25U) 4975 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) 4976 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk 4977 #define CAN_F5R2_FB26_Pos (26U) 4978 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) 4979 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk 4980 #define CAN_F5R2_FB27_Pos (27U) 4981 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) 4982 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk 4983 #define CAN_F5R2_FB28_Pos (28U) 4984 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) 4985 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk 4986 #define CAN_F5R2_FB29_Pos (29U) 4987 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) 4988 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk 4989 #define CAN_F5R2_FB30_Pos (30U) 4990 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) 4991 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk 4992 #define CAN_F5R2_FB31_Pos (31U) 4993 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) 4994 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk 4997 #define CAN_F6R2_FB0_Pos (0U) 4998 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) 4999 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk 5000 #define CAN_F6R2_FB1_Pos (1U) 5001 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) 5002 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk 5003 #define CAN_F6R2_FB2_Pos (2U) 5004 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) 5005 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk 5006 #define CAN_F6R2_FB3_Pos (3U) 5007 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) 5008 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk 5009 #define CAN_F6R2_FB4_Pos (4U) 5010 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) 5011 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk 5012 #define CAN_F6R2_FB5_Pos (5U) 5013 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) 5014 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk 5015 #define CAN_F6R2_FB6_Pos (6U) 5016 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) 5017 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk 5018 #define CAN_F6R2_FB7_Pos (7U) 5019 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) 5020 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk 5021 #define CAN_F6R2_FB8_Pos (8U) 5022 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) 5023 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk 5024 #define CAN_F6R2_FB9_Pos (9U) 5025 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) 5026 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk 5027 #define CAN_F6R2_FB10_Pos (10U) 5028 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) 5029 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk 5030 #define CAN_F6R2_FB11_Pos (11U) 5031 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) 5032 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk 5033 #define CAN_F6R2_FB12_Pos (12U) 5034 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) 5035 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk 5036 #define CAN_F6R2_FB13_Pos (13U) 5037 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) 5038 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk 5039 #define CAN_F6R2_FB14_Pos (14U) 5040 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) 5041 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk 5042 #define CAN_F6R2_FB15_Pos (15U) 5043 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) 5044 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk 5045 #define CAN_F6R2_FB16_Pos (16U) 5046 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) 5047 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk 5048 #define CAN_F6R2_FB17_Pos (17U) 5049 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) 5050 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk 5051 #define CAN_F6R2_FB18_Pos (18U) 5052 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) 5053 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk 5054 #define CAN_F6R2_FB19_Pos (19U) 5055 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) 5056 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk 5057 #define CAN_F6R2_FB20_Pos (20U) 5058 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) 5059 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk 5060 #define CAN_F6R2_FB21_Pos (21U) 5061 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) 5062 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk 5063 #define CAN_F6R2_FB22_Pos (22U) 5064 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) 5065 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk 5066 #define CAN_F6R2_FB23_Pos (23U) 5067 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) 5068 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk 5069 #define CAN_F6R2_FB24_Pos (24U) 5070 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) 5071 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk 5072 #define CAN_F6R2_FB25_Pos (25U) 5073 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) 5074 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk 5075 #define CAN_F6R2_FB26_Pos (26U) 5076 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) 5077 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk 5078 #define CAN_F6R2_FB27_Pos (27U) 5079 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) 5080 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk 5081 #define CAN_F6R2_FB28_Pos (28U) 5082 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) 5083 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk 5084 #define CAN_F6R2_FB29_Pos (29U) 5085 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) 5086 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk 5087 #define CAN_F6R2_FB30_Pos (30U) 5088 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) 5089 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk 5090 #define CAN_F6R2_FB31_Pos (31U) 5091 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) 5092 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk 5095 #define CAN_F7R2_FB0_Pos (0U) 5096 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) 5097 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk 5098 #define CAN_F7R2_FB1_Pos (1U) 5099 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) 5100 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk 5101 #define CAN_F7R2_FB2_Pos (2U) 5102 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) 5103 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk 5104 #define CAN_F7R2_FB3_Pos (3U) 5105 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) 5106 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk 5107 #define CAN_F7R2_FB4_Pos (4U) 5108 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) 5109 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk 5110 #define CAN_F7R2_FB5_Pos (5U) 5111 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) 5112 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk 5113 #define CAN_F7R2_FB6_Pos (6U) 5114 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) 5115 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk 5116 #define CAN_F7R2_FB7_Pos (7U) 5117 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) 5118 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk 5119 #define CAN_F7R2_FB8_Pos (8U) 5120 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) 5121 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk 5122 #define CAN_F7R2_FB9_Pos (9U) 5123 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) 5124 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk 5125 #define CAN_F7R2_FB10_Pos (10U) 5126 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) 5127 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk 5128 #define CAN_F7R2_FB11_Pos (11U) 5129 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) 5130 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk 5131 #define CAN_F7R2_FB12_Pos (12U) 5132 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) 5133 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk 5134 #define CAN_F7R2_FB13_Pos (13U) 5135 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) 5136 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk 5137 #define CAN_F7R2_FB14_Pos (14U) 5138 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) 5139 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk 5140 #define CAN_F7R2_FB15_Pos (15U) 5141 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) 5142 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk 5143 #define CAN_F7R2_FB16_Pos (16U) 5144 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) 5145 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk 5146 #define CAN_F7R2_FB17_Pos (17U) 5147 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) 5148 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk 5149 #define CAN_F7R2_FB18_Pos (18U) 5150 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) 5151 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk 5152 #define CAN_F7R2_FB19_Pos (19U) 5153 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) 5154 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk 5155 #define CAN_F7R2_FB20_Pos (20U) 5156 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) 5157 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk 5158 #define CAN_F7R2_FB21_Pos (21U) 5159 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) 5160 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk 5161 #define CAN_F7R2_FB22_Pos (22U) 5162 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) 5163 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk 5164 #define CAN_F7R2_FB23_Pos (23U) 5165 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) 5166 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk 5167 #define CAN_F7R2_FB24_Pos (24U) 5168 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) 5169 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk 5170 #define CAN_F7R2_FB25_Pos (25U) 5171 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) 5172 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk 5173 #define CAN_F7R2_FB26_Pos (26U) 5174 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) 5175 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk 5176 #define CAN_F7R2_FB27_Pos (27U) 5177 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) 5178 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk 5179 #define CAN_F7R2_FB28_Pos (28U) 5180 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) 5181 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk 5182 #define CAN_F7R2_FB29_Pos (29U) 5183 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) 5184 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk 5185 #define CAN_F7R2_FB30_Pos (30U) 5186 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) 5187 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk 5188 #define CAN_F7R2_FB31_Pos (31U) 5189 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) 5190 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk 5193 #define CAN_F8R2_FB0_Pos (0U) 5194 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) 5195 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk 5196 #define CAN_F8R2_FB1_Pos (1U) 5197 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) 5198 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk 5199 #define CAN_F8R2_FB2_Pos (2U) 5200 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) 5201 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk 5202 #define CAN_F8R2_FB3_Pos (3U) 5203 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) 5204 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk 5205 #define CAN_F8R2_FB4_Pos (4U) 5206 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) 5207 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk 5208 #define CAN_F8R2_FB5_Pos (5U) 5209 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) 5210 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk 5211 #define CAN_F8R2_FB6_Pos (6U) 5212 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) 5213 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk 5214 #define CAN_F8R2_FB7_Pos (7U) 5215 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) 5216 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk 5217 #define CAN_F8R2_FB8_Pos (8U) 5218 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) 5219 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk 5220 #define CAN_F8R2_FB9_Pos (9U) 5221 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) 5222 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk 5223 #define CAN_F8R2_FB10_Pos (10U) 5224 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) 5225 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk 5226 #define CAN_F8R2_FB11_Pos (11U) 5227 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) 5228 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk 5229 #define CAN_F8R2_FB12_Pos (12U) 5230 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) 5231 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk 5232 #define CAN_F8R2_FB13_Pos (13U) 5233 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) 5234 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk 5235 #define CAN_F8R2_FB14_Pos (14U) 5236 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) 5237 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk 5238 #define CAN_F8R2_FB15_Pos (15U) 5239 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) 5240 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk 5241 #define CAN_F8R2_FB16_Pos (16U) 5242 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) 5243 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk 5244 #define CAN_F8R2_FB17_Pos (17U) 5245 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) 5246 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk 5247 #define CAN_F8R2_FB18_Pos (18U) 5248 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) 5249 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk 5250 #define CAN_F8R2_FB19_Pos (19U) 5251 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) 5252 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk 5253 #define CAN_F8R2_FB20_Pos (20U) 5254 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) 5255 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk 5256 #define CAN_F8R2_FB21_Pos (21U) 5257 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) 5258 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk 5259 #define CAN_F8R2_FB22_Pos (22U) 5260 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) 5261 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk 5262 #define CAN_F8R2_FB23_Pos (23U) 5263 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) 5264 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk 5265 #define CAN_F8R2_FB24_Pos (24U) 5266 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) 5267 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk 5268 #define CAN_F8R2_FB25_Pos (25U) 5269 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) 5270 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk 5271 #define CAN_F8R2_FB26_Pos (26U) 5272 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) 5273 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk 5274 #define CAN_F8R2_FB27_Pos (27U) 5275 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) 5276 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk 5277 #define CAN_F8R2_FB28_Pos (28U) 5278 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) 5279 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk 5280 #define CAN_F8R2_FB29_Pos (29U) 5281 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) 5282 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk 5283 #define CAN_F8R2_FB30_Pos (30U) 5284 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) 5285 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk 5286 #define CAN_F8R2_FB31_Pos (31U) 5287 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) 5288 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk 5291 #define CAN_F9R2_FB0_Pos (0U) 5292 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) 5293 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk 5294 #define CAN_F9R2_FB1_Pos (1U) 5295 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) 5296 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk 5297 #define CAN_F9R2_FB2_Pos (2U) 5298 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) 5299 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk 5300 #define CAN_F9R2_FB3_Pos (3U) 5301 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) 5302 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk 5303 #define CAN_F9R2_FB4_Pos (4U) 5304 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) 5305 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk 5306 #define CAN_F9R2_FB5_Pos (5U) 5307 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) 5308 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk 5309 #define CAN_F9R2_FB6_Pos (6U) 5310 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) 5311 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk 5312 #define CAN_F9R2_FB7_Pos (7U) 5313 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) 5314 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk 5315 #define CAN_F9R2_FB8_Pos (8U) 5316 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) 5317 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk 5318 #define CAN_F9R2_FB9_Pos (9U) 5319 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) 5320 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk 5321 #define CAN_F9R2_FB10_Pos (10U) 5322 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) 5323 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk 5324 #define CAN_F9R2_FB11_Pos (11U) 5325 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) 5326 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk 5327 #define CAN_F9R2_FB12_Pos (12U) 5328 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) 5329 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk 5330 #define CAN_F9R2_FB13_Pos (13U) 5331 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) 5332 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk 5333 #define CAN_F9R2_FB14_Pos (14U) 5334 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) 5335 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk 5336 #define CAN_F9R2_FB15_Pos (15U) 5337 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) 5338 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk 5339 #define CAN_F9R2_FB16_Pos (16U) 5340 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) 5341 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk 5342 #define CAN_F9R2_FB17_Pos (17U) 5343 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) 5344 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk 5345 #define CAN_F9R2_FB18_Pos (18U) 5346 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) 5347 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk 5348 #define CAN_F9R2_FB19_Pos (19U) 5349 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) 5350 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk 5351 #define CAN_F9R2_FB20_Pos (20U) 5352 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) 5353 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk 5354 #define CAN_F9R2_FB21_Pos (21U) 5355 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) 5356 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk 5357 #define CAN_F9R2_FB22_Pos (22U) 5358 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) 5359 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk 5360 #define CAN_F9R2_FB23_Pos (23U) 5361 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) 5362 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk 5363 #define CAN_F9R2_FB24_Pos (24U) 5364 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) 5365 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk 5366 #define CAN_F9R2_FB25_Pos (25U) 5367 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) 5368 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk 5369 #define CAN_F9R2_FB26_Pos (26U) 5370 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) 5371 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk 5372 #define CAN_F9R2_FB27_Pos (27U) 5373 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) 5374 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk 5375 #define CAN_F9R2_FB28_Pos (28U) 5376 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) 5377 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk 5378 #define CAN_F9R2_FB29_Pos (29U) 5379 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) 5380 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk 5381 #define CAN_F9R2_FB30_Pos (30U) 5382 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) 5383 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk 5384 #define CAN_F9R2_FB31_Pos (31U) 5385 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) 5386 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk 5389 #define CAN_F10R2_FB0_Pos (0U) 5390 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) 5391 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk 5392 #define CAN_F10R2_FB1_Pos (1U) 5393 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) 5394 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk 5395 #define CAN_F10R2_FB2_Pos (2U) 5396 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) 5397 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk 5398 #define CAN_F10R2_FB3_Pos (3U) 5399 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) 5400 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk 5401 #define CAN_F10R2_FB4_Pos (4U) 5402 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) 5403 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk 5404 #define CAN_F10R2_FB5_Pos (5U) 5405 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) 5406 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk 5407 #define CAN_F10R2_FB6_Pos (6U) 5408 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) 5409 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk 5410 #define CAN_F10R2_FB7_Pos (7U) 5411 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) 5412 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk 5413 #define CAN_F10R2_FB8_Pos (8U) 5414 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) 5415 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk 5416 #define CAN_F10R2_FB9_Pos (9U) 5417 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) 5418 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk 5419 #define CAN_F10R2_FB10_Pos (10U) 5420 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) 5421 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk 5422 #define CAN_F10R2_FB11_Pos (11U) 5423 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) 5424 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk 5425 #define CAN_F10R2_FB12_Pos (12U) 5426 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) 5427 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk 5428 #define CAN_F10R2_FB13_Pos (13U) 5429 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) 5430 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk 5431 #define CAN_F10R2_FB14_Pos (14U) 5432 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) 5433 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk 5434 #define CAN_F10R2_FB15_Pos (15U) 5435 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) 5436 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk 5437 #define CAN_F10R2_FB16_Pos (16U) 5438 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) 5439 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk 5440 #define CAN_F10R2_FB17_Pos (17U) 5441 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) 5442 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk 5443 #define CAN_F10R2_FB18_Pos (18U) 5444 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) 5445 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk 5446 #define CAN_F10R2_FB19_Pos (19U) 5447 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) 5448 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk 5449 #define CAN_F10R2_FB20_Pos (20U) 5450 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) 5451 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk 5452 #define CAN_F10R2_FB21_Pos (21U) 5453 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) 5454 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk 5455 #define CAN_F10R2_FB22_Pos (22U) 5456 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) 5457 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk 5458 #define CAN_F10R2_FB23_Pos (23U) 5459 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) 5460 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk 5461 #define CAN_F10R2_FB24_Pos (24U) 5462 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) 5463 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk 5464 #define CAN_F10R2_FB25_Pos (25U) 5465 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) 5466 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk 5467 #define CAN_F10R2_FB26_Pos (26U) 5468 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) 5469 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk 5470 #define CAN_F10R2_FB27_Pos (27U) 5471 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) 5472 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk 5473 #define CAN_F10R2_FB28_Pos (28U) 5474 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) 5475 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk 5476 #define CAN_F10R2_FB29_Pos (29U) 5477 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) 5478 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk 5479 #define CAN_F10R2_FB30_Pos (30U) 5480 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) 5481 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk 5482 #define CAN_F10R2_FB31_Pos (31U) 5483 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) 5484 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk 5487 #define CAN_F11R2_FB0_Pos (0U) 5488 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) 5489 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk 5490 #define CAN_F11R2_FB1_Pos (1U) 5491 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) 5492 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk 5493 #define CAN_F11R2_FB2_Pos (2U) 5494 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) 5495 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk 5496 #define CAN_F11R2_FB3_Pos (3U) 5497 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) 5498 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk 5499 #define CAN_F11R2_FB4_Pos (4U) 5500 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) 5501 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk 5502 #define CAN_F11R2_FB5_Pos (5U) 5503 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) 5504 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk 5505 #define CAN_F11R2_FB6_Pos (6U) 5506 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) 5507 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk 5508 #define CAN_F11R2_FB7_Pos (7U) 5509 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) 5510 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk 5511 #define CAN_F11R2_FB8_Pos (8U) 5512 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) 5513 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk 5514 #define CAN_F11R2_FB9_Pos (9U) 5515 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) 5516 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk 5517 #define CAN_F11R2_FB10_Pos (10U) 5518 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) 5519 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk 5520 #define CAN_F11R2_FB11_Pos (11U) 5521 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) 5522 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk 5523 #define CAN_F11R2_FB12_Pos (12U) 5524 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) 5525 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk 5526 #define CAN_F11R2_FB13_Pos (13U) 5527 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) 5528 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk 5529 #define CAN_F11R2_FB14_Pos (14U) 5530 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) 5531 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk 5532 #define CAN_F11R2_FB15_Pos (15U) 5533 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) 5534 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk 5535 #define CAN_F11R2_FB16_Pos (16U) 5536 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) 5537 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk 5538 #define CAN_F11R2_FB17_Pos (17U) 5539 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) 5540 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk 5541 #define CAN_F11R2_FB18_Pos (18U) 5542 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) 5543 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk 5544 #define CAN_F11R2_FB19_Pos (19U) 5545 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) 5546 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk 5547 #define CAN_F11R2_FB20_Pos (20U) 5548 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) 5549 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk 5550 #define CAN_F11R2_FB21_Pos (21U) 5551 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) 5552 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk 5553 #define CAN_F11R2_FB22_Pos (22U) 5554 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) 5555 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk 5556 #define CAN_F11R2_FB23_Pos (23U) 5557 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) 5558 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk 5559 #define CAN_F11R2_FB24_Pos (24U) 5560 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) 5561 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk 5562 #define CAN_F11R2_FB25_Pos (25U) 5563 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) 5564 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk 5565 #define CAN_F11R2_FB26_Pos (26U) 5566 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) 5567 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk 5568 #define CAN_F11R2_FB27_Pos (27U) 5569 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) 5570 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk 5571 #define CAN_F11R2_FB28_Pos (28U) 5572 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) 5573 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk 5574 #define CAN_F11R2_FB29_Pos (29U) 5575 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) 5576 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk 5577 #define CAN_F11R2_FB30_Pos (30U) 5578 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) 5579 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk 5580 #define CAN_F11R2_FB31_Pos (31U) 5581 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) 5582 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk 5585 #define CAN_F12R2_FB0_Pos (0U) 5586 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) 5587 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk 5588 #define CAN_F12R2_FB1_Pos (1U) 5589 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) 5590 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk 5591 #define CAN_F12R2_FB2_Pos (2U) 5592 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) 5593 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk 5594 #define CAN_F12R2_FB3_Pos (3U) 5595 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) 5596 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk 5597 #define CAN_F12R2_FB4_Pos (4U) 5598 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) 5599 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk 5600 #define CAN_F12R2_FB5_Pos (5U) 5601 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) 5602 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk 5603 #define CAN_F12R2_FB6_Pos (6U) 5604 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) 5605 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk 5606 #define CAN_F12R2_FB7_Pos (7U) 5607 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) 5608 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk 5609 #define CAN_F12R2_FB8_Pos (8U) 5610 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) 5611 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk 5612 #define CAN_F12R2_FB9_Pos (9U) 5613 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) 5614 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk 5615 #define CAN_F12R2_FB10_Pos (10U) 5616 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) 5617 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk 5618 #define CAN_F12R2_FB11_Pos (11U) 5619 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) 5620 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk 5621 #define CAN_F12R2_FB12_Pos (12U) 5622 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) 5623 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk 5624 #define CAN_F12R2_FB13_Pos (13U) 5625 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) 5626 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk 5627 #define CAN_F12R2_FB14_Pos (14U) 5628 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) 5629 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk 5630 #define CAN_F12R2_FB15_Pos (15U) 5631 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) 5632 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk 5633 #define CAN_F12R2_FB16_Pos (16U) 5634 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) 5635 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk 5636 #define CAN_F12R2_FB17_Pos (17U) 5637 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) 5638 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk 5639 #define CAN_F12R2_FB18_Pos (18U) 5640 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) 5641 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk 5642 #define CAN_F12R2_FB19_Pos (19U) 5643 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) 5644 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk 5645 #define CAN_F12R2_FB20_Pos (20U) 5646 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) 5647 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk 5648 #define CAN_F12R2_FB21_Pos (21U) 5649 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) 5650 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk 5651 #define CAN_F12R2_FB22_Pos (22U) 5652 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) 5653 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk 5654 #define CAN_F12R2_FB23_Pos (23U) 5655 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) 5656 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk 5657 #define CAN_F12R2_FB24_Pos (24U) 5658 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) 5659 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk 5660 #define CAN_F12R2_FB25_Pos (25U) 5661 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) 5662 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk 5663 #define CAN_F12R2_FB26_Pos (26U) 5664 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) 5665 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk 5666 #define CAN_F12R2_FB27_Pos (27U) 5667 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) 5668 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk 5669 #define CAN_F12R2_FB28_Pos (28U) 5670 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) 5671 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk 5672 #define CAN_F12R2_FB29_Pos (29U) 5673 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) 5674 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk 5675 #define CAN_F12R2_FB30_Pos (30U) 5676 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) 5677 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk 5678 #define CAN_F12R2_FB31_Pos (31U) 5679 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) 5680 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk 5683 #define CAN_F13R2_FB0_Pos (0U) 5684 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) 5685 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk 5686 #define CAN_F13R2_FB1_Pos (1U) 5687 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) 5688 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk 5689 #define CAN_F13R2_FB2_Pos (2U) 5690 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) 5691 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk 5692 #define CAN_F13R2_FB3_Pos (3U) 5693 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) 5694 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk 5695 #define CAN_F13R2_FB4_Pos (4U) 5696 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) 5697 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk 5698 #define CAN_F13R2_FB5_Pos (5U) 5699 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) 5700 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk 5701 #define CAN_F13R2_FB6_Pos (6U) 5702 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) 5703 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk 5704 #define CAN_F13R2_FB7_Pos (7U) 5705 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) 5706 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk 5707 #define CAN_F13R2_FB8_Pos (8U) 5708 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) 5709 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk 5710 #define CAN_F13R2_FB9_Pos (9U) 5711 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) 5712 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk 5713 #define CAN_F13R2_FB10_Pos (10U) 5714 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) 5715 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk 5716 #define CAN_F13R2_FB11_Pos (11U) 5717 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) 5718 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk 5719 #define CAN_F13R2_FB12_Pos (12U) 5720 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) 5721 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk 5722 #define CAN_F13R2_FB13_Pos (13U) 5723 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) 5724 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk 5725 #define CAN_F13R2_FB14_Pos (14U) 5726 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) 5727 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk 5728 #define CAN_F13R2_FB15_Pos (15U) 5729 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) 5730 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk 5731 #define CAN_F13R2_FB16_Pos (16U) 5732 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) 5733 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk 5734 #define CAN_F13R2_FB17_Pos (17U) 5735 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) 5736 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk 5737 #define CAN_F13R2_FB18_Pos (18U) 5738 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) 5739 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk 5740 #define CAN_F13R2_FB19_Pos (19U) 5741 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) 5742 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk 5743 #define CAN_F13R2_FB20_Pos (20U) 5744 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) 5745 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk 5746 #define CAN_F13R2_FB21_Pos (21U) 5747 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) 5748 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk 5749 #define CAN_F13R2_FB22_Pos (22U) 5750 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) 5751 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk 5752 #define CAN_F13R2_FB23_Pos (23U) 5753 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) 5754 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk 5755 #define CAN_F13R2_FB24_Pos (24U) 5756 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) 5757 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk 5758 #define CAN_F13R2_FB25_Pos (25U) 5759 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) 5760 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk 5761 #define CAN_F13R2_FB26_Pos (26U) 5762 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) 5763 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk 5764 #define CAN_F13R2_FB27_Pos (27U) 5765 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) 5766 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk 5767 #define CAN_F13R2_FB28_Pos (28U) 5768 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) 5769 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk 5770 #define CAN_F13R2_FB29_Pos (29U) 5771 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) 5772 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk 5773 #define CAN_F13R2_FB30_Pos (30U) 5774 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) 5775 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk 5776 #define CAN_F13R2_FB31_Pos (31U) 5777 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) 5778 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk 5787 #define CEC_CR_CECEN_Pos (0U) 5788 #define CEC_CR_CECEN_Msk (0x1U << CEC_CR_CECEN_Pos) 5789 #define CEC_CR_CECEN CEC_CR_CECEN_Msk 5790 #define CEC_CR_TXSOM_Pos (1U) 5791 #define CEC_CR_TXSOM_Msk (0x1U << CEC_CR_TXSOM_Pos) 5792 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk 5793 #define CEC_CR_TXEOM_Pos (2U) 5794 #define CEC_CR_TXEOM_Msk (0x1U << CEC_CR_TXEOM_Pos) 5795 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk 5798 #define CEC_CFGR_SFT_Pos (0U) 5799 #define CEC_CFGR_SFT_Msk (0x7U << CEC_CFGR_SFT_Pos) 5800 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk 5801 #define CEC_CFGR_RXTOL_Pos (3U) 5802 #define CEC_CFGR_RXTOL_Msk (0x1U << CEC_CFGR_RXTOL_Pos) 5803 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk 5804 #define CEC_CFGR_BRESTP_Pos (4U) 5805 #define CEC_CFGR_BRESTP_Msk (0x1U << CEC_CFGR_BRESTP_Pos) 5806 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk 5807 #define CEC_CFGR_BREGEN_Pos (5U) 5808 #define CEC_CFGR_BREGEN_Msk (0x1U << CEC_CFGR_BREGEN_Pos) 5809 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk 5810 #define CEC_CFGR_LBPEGEN_Pos (6U) 5811 #define CEC_CFGR_LBPEGEN_Msk (0x1U << CEC_CFGR_LBPEGEN_Pos) 5812 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk 5813 #define CEC_CFGR_BRDNOGEN_Pos (7U) 5814 #define CEC_CFGR_BRDNOGEN_Msk (0x1U << CEC_CFGR_BRDNOGEN_Pos) 5815 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk 5816 #define CEC_CFGR_SFTOPT_Pos (8U) 5817 #define CEC_CFGR_SFTOPT_Msk (0x1U << CEC_CFGR_SFTOPT_Pos) 5818 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk 5819 #define CEC_CFGR_OAR_Pos (16U) 5820 #define CEC_CFGR_OAR_Msk (0x7FFFU << CEC_CFGR_OAR_Pos) 5821 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk 5822 #define CEC_CFGR_LSTN_Pos (31U) 5823 #define CEC_CFGR_LSTN_Msk (0x1U << CEC_CFGR_LSTN_Pos) 5824 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk 5827 #define CEC_TXDR_TXD_Pos (0U) 5828 #define CEC_TXDR_TXD_Msk (0xFFU << CEC_TXDR_TXD_Pos) 5829 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk 5832 #define CEC_TXDR_RXD_Pos (0U) 5833 #define CEC_TXDR_RXD_Msk (0xFFU << CEC_TXDR_RXD_Pos) 5834 #define CEC_TXDR_RXD CEC_TXDR_RXD_Msk 5837 #define CEC_ISR_RXBR_Pos (0U) 5838 #define CEC_ISR_RXBR_Msk (0x1U << CEC_ISR_RXBR_Pos) 5839 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk 5840 #define CEC_ISR_RXEND_Pos (1U) 5841 #define CEC_ISR_RXEND_Msk (0x1U << CEC_ISR_RXEND_Pos) 5842 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk 5843 #define CEC_ISR_RXOVR_Pos (2U) 5844 #define CEC_ISR_RXOVR_Msk (0x1U << CEC_ISR_RXOVR_Pos) 5845 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk 5846 #define CEC_ISR_BRE_Pos (3U) 5847 #define CEC_ISR_BRE_Msk (0x1U << CEC_ISR_BRE_Pos) 5848 #define CEC_ISR_BRE CEC_ISR_BRE_Msk 5849 #define CEC_ISR_SBPE_Pos (4U) 5850 #define CEC_ISR_SBPE_Msk (0x1U << CEC_ISR_SBPE_Pos) 5851 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk 5852 #define CEC_ISR_LBPE_Pos (5U) 5853 #define CEC_ISR_LBPE_Msk (0x1U << CEC_ISR_LBPE_Pos) 5854 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk 5855 #define CEC_ISR_RXACKE_Pos (6U) 5856 #define CEC_ISR_RXACKE_Msk (0x1U << CEC_ISR_RXACKE_Pos) 5857 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk 5858 #define CEC_ISR_ARBLST_Pos (7U) 5859 #define CEC_ISR_ARBLST_Msk (0x1U << CEC_ISR_ARBLST_Pos) 5860 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk 5861 #define CEC_ISR_TXBR_Pos (8U) 5862 #define CEC_ISR_TXBR_Msk (0x1U << CEC_ISR_TXBR_Pos) 5863 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk 5864 #define CEC_ISR_TXEND_Pos (9U) 5865 #define CEC_ISR_TXEND_Msk (0x1U << CEC_ISR_TXEND_Pos) 5866 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk 5867 #define CEC_ISR_TXUDR_Pos (10U) 5868 #define CEC_ISR_TXUDR_Msk (0x1U << CEC_ISR_TXUDR_Pos) 5869 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk 5870 #define CEC_ISR_TXERR_Pos (11U) 5871 #define CEC_ISR_TXERR_Msk (0x1U << CEC_ISR_TXERR_Pos) 5872 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk 5873 #define CEC_ISR_TXACKE_Pos (12U) 5874 #define CEC_ISR_TXACKE_Msk (0x1U << CEC_ISR_TXACKE_Pos) 5875 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk 5878 #define CEC_IER_RXBRIE_Pos (0U) 5879 #define CEC_IER_RXBRIE_Msk (0x1U << CEC_IER_RXBRIE_Pos) 5880 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk 5881 #define CEC_IER_RXENDIE_Pos (1U) 5882 #define CEC_IER_RXENDIE_Msk (0x1U << CEC_IER_RXENDIE_Pos) 5883 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk 5884 #define CEC_IER_RXOVRIE_Pos (2U) 5885 #define CEC_IER_RXOVRIE_Msk (0x1U << CEC_IER_RXOVRIE_Pos) 5886 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk 5887 #define CEC_IER_BREIE_Pos (3U) 5888 #define CEC_IER_BREIE_Msk (0x1U << CEC_IER_BREIE_Pos) 5889 #define CEC_IER_BREIE CEC_IER_BREIE_Msk 5890 #define CEC_IER_SBPEIE_Pos (4U) 5891 #define CEC_IER_SBPEIE_Msk (0x1U << CEC_IER_SBPEIE_Pos) 5892 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk 5893 #define CEC_IER_LBPEIE_Pos (5U) 5894 #define CEC_IER_LBPEIE_Msk (0x1U << CEC_IER_LBPEIE_Pos) 5895 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk 5896 #define CEC_IER_RXACKEIE_Pos (6U) 5897 #define CEC_IER_RXACKEIE_Msk (0x1U << CEC_IER_RXACKEIE_Pos) 5898 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk 5899 #define CEC_IER_ARBLSTIE_Pos (7U) 5900 #define CEC_IER_ARBLSTIE_Msk (0x1U << CEC_IER_ARBLSTIE_Pos) 5901 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk 5902 #define CEC_IER_TXBRIE_Pos (8U) 5903 #define CEC_IER_TXBRIE_Msk (0x1U << CEC_IER_TXBRIE_Pos) 5904 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk 5905 #define CEC_IER_TXENDIE_Pos (9U) 5906 #define CEC_IER_TXENDIE_Msk (0x1U << CEC_IER_TXENDIE_Pos) 5907 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk 5908 #define CEC_IER_TXUDRIE_Pos (10U) 5909 #define CEC_IER_TXUDRIE_Msk (0x1U << CEC_IER_TXUDRIE_Pos) 5910 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk 5911 #define CEC_IER_TXERRIE_Pos (11U) 5912 #define CEC_IER_TXERRIE_Msk (0x1U << CEC_IER_TXERRIE_Pos) 5913 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk 5914 #define CEC_IER_TXACKEIE_Pos (12U) 5915 #define CEC_IER_TXACKEIE_Msk (0x1U << CEC_IER_TXACKEIE_Pos) 5916 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk 5924 #define CRC_DR_DR_Pos (0U) 5925 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) 5926 #define CRC_DR_DR CRC_DR_DR_Msk 5929 #define CRC_IDR_IDR_Pos (0U) 5930 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) 5931 #define CRC_IDR_IDR CRC_IDR_IDR_Msk 5934 #define CRC_CR_RESET_Pos (0U) 5935 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) 5936 #define CRC_CR_RESET CRC_CR_RESET_Msk 5937 #define CRC_CR_POLYSIZE_Pos (3U) 5938 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) 5939 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk 5940 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) 5941 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) 5942 #define CRC_CR_REV_IN_Pos (5U) 5943 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) 5944 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk 5945 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) 5946 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) 5947 #define CRC_CR_REV_OUT_Pos (7U) 5948 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) 5949 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk 5952 #define CRC_INIT_INIT_Pos (0U) 5953 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) 5954 #define CRC_INIT_INIT CRC_INIT_INIT_Msk 5957 #define CRC_POL_POL_Pos (0U) 5958 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) 5959 #define CRC_POL_POL CRC_POL_POL_Msk 5968 #define DAC_CR_EN1_Pos (0U) 5969 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) 5970 #define DAC_CR_EN1 DAC_CR_EN1_Msk 5971 #define DAC_CR_BOFF1_Pos (1U) 5972 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) 5973 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk 5974 #define DAC_CR_TEN1_Pos (2U) 5975 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) 5976 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk 5977 #define DAC_CR_TSEL1_Pos (3U) 5978 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) 5979 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk 5980 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) 5981 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) 5982 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) 5983 #define DAC_CR_WAVE1_Pos (6U) 5984 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) 5985 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk 5986 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) 5987 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) 5988 #define DAC_CR_MAMP1_Pos (8U) 5989 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) 5990 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk 5991 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) 5992 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) 5993 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) 5994 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) 5995 #define DAC_CR_DMAEN1_Pos (12U) 5996 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) 5997 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk 5998 #define DAC_CR_DMAUDRIE1_Pos (13U) 5999 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) 6000 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk 6001 #define DAC_CR_EN2_Pos (16U) 6002 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) 6003 #define DAC_CR_EN2 DAC_CR_EN2_Msk 6004 #define DAC_CR_BOFF2_Pos (17U) 6005 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) 6006 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk 6007 #define DAC_CR_TEN2_Pos (18U) 6008 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) 6009 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk 6010 #define DAC_CR_TSEL2_Pos (19U) 6011 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) 6012 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk 6013 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) 6014 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) 6015 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) 6016 #define DAC_CR_WAVE2_Pos (22U) 6017 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) 6018 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk 6019 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) 6020 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) 6021 #define DAC_CR_MAMP2_Pos (24U) 6022 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) 6023 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk 6024 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) 6025 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) 6026 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) 6027 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) 6028 #define DAC_CR_DMAEN2_Pos (28U) 6029 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) 6030 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk 6031 #define DAC_CR_DMAUDRIE2_Pos (29U) 6032 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) 6033 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk 6036 #define DAC_SWTRIGR_SWTRIG1_Pos (0U) 6037 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) 6038 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk 6039 #define DAC_SWTRIGR_SWTRIG2_Pos (1U) 6040 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) 6041 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk 6044 #define DAC_DHR12R1_DACC1DHR_Pos (0U) 6045 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) 6046 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk 6049 #define DAC_DHR12L1_DACC1DHR_Pos (4U) 6050 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) 6051 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk 6054 #define DAC_DHR8R1_DACC1DHR_Pos (0U) 6055 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) 6056 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk 6059 #define DAC_DHR12R2_DACC2DHR_Pos (0U) 6060 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) 6061 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk 6064 #define DAC_DHR12L2_DACC2DHR_Pos (4U) 6065 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) 6066 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk 6069 #define DAC_DHR8R2_DACC2DHR_Pos (0U) 6070 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) 6071 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk 6074 #define DAC_DHR12RD_DACC1DHR_Pos (0U) 6075 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) 6076 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk 6077 #define DAC_DHR12RD_DACC2DHR_Pos (16U) 6078 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) 6079 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk 6082 #define DAC_DHR12LD_DACC1DHR_Pos (4U) 6083 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) 6084 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk 6085 #define DAC_DHR12LD_DACC2DHR_Pos (20U) 6086 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) 6087 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk 6090 #define DAC_DHR8RD_DACC1DHR_Pos (0U) 6091 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) 6092 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk 6093 #define DAC_DHR8RD_DACC2DHR_Pos (8U) 6094 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) 6095 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk 6098 #define DAC_DOR1_DACC1DOR_Pos (0U) 6099 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) 6100 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk 6103 #define DAC_DOR2_DACC2DOR_Pos (0U) 6104 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) 6105 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk 6108 #define DAC_SR_DMAUDR1_Pos (13U) 6109 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) 6110 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk 6111 #define DAC_SR_DMAUDR2_Pos (29U) 6112 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) 6113 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk 6124 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U) 6125 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) 6126 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk 6127 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U) 6128 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) 6129 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk 6130 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U) 6131 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) 6132 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk 6133 #define DFSDM_CHCFGR1_DATPACK_Pos (14U) 6134 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) 6135 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk 6136 #define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) 6137 #define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) 6138 #define DFSDM_CHCFGR1_DATMPX_Pos (12U) 6139 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) 6140 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk 6141 #define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) 6142 #define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) 6143 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U) 6144 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) 6145 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk 6146 #define DFSDM_CHCFGR1_CHEN_Pos (7U) 6147 #define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) 6148 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk 6149 #define DFSDM_CHCFGR1_CKABEN_Pos (6U) 6150 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) 6151 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk 6152 #define DFSDM_CHCFGR1_SCDEN_Pos (5U) 6153 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) 6154 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk 6155 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U) 6156 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) 6157 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk 6158 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) 6159 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) 6160 #define DFSDM_CHCFGR1_SITP_Pos (0U) 6161 #define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) 6162 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk 6163 #define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) 6164 #define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) 6167 #define DFSDM_CHCFGR2_OFFSET_Pos (8U) 6168 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) 6169 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk 6170 #define DFSDM_CHCFGR2_DTRBS_Pos (3U) 6171 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) 6172 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk 6175 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U) 6176 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) 6177 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk 6178 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) 6179 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) 6180 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U) 6181 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) 6182 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk 6183 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U) 6184 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) 6185 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk 6186 #define DFSDM_CHAWSCDR_SCDT_Pos (0U) 6187 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) 6188 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk 6191 #define DFSDM_CHWDATR_WDATA_Pos (0U) 6192 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) 6193 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk 6196 #define DFSDM_CHDATINR_INDAT0_Pos (0U) 6197 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) 6198 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk 6199 #define DFSDM_CHDATINR_INDAT1_Pos (16U) 6200 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) 6201 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk 6206 #define DFSDM_FLTCR1_AWFSEL_Pos (30U) 6207 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) 6208 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk 6209 #define DFSDM_FLTCR1_FAST_Pos (29U) 6210 #define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) 6211 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk 6212 #define DFSDM_FLTCR1_RCH_Pos (24U) 6213 #define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) 6214 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk 6215 #define DFSDM_FLTCR1_RDMAEN_Pos (21U) 6216 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) 6217 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk 6218 #define DFSDM_FLTCR1_RSYNC_Pos (19U) 6219 #define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) 6220 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk 6221 #define DFSDM_FLTCR1_RCONT_Pos (18U) 6222 #define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) 6223 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk 6224 #define DFSDM_FLTCR1_RSWSTART_Pos (17U) 6225 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) 6226 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk 6227 #define DFSDM_FLTCR1_JEXTEN_Pos (13U) 6228 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) 6229 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk 6230 #define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) 6231 #define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) 6232 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U) 6233 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FU << DFSDM_FLTCR1_JEXTSEL_Pos) 6234 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk 6235 #define DFSDM_FLTCR1_JEXTSEL_0 (0x01U << DFSDM_FLTCR1_JEXTSEL_Pos) 6236 #define DFSDM_FLTCR1_JEXTSEL_1 (0x02U << DFSDM_FLTCR1_JEXTSEL_Pos) 6237 #define DFSDM_FLTCR1_JEXTSEL_2 (0x04U << DFSDM_FLTCR1_JEXTSEL_Pos) 6238 #define DFSDM_FLTCR1_JEXTSEL_3 (0x08U << DFSDM_FLTCR1_JEXTSEL_Pos) 6239 #define DFSDM_FLTCR1_JEXTSEL_4 (0x10U << DFSDM_FLTCR1_JEXTSEL_Pos) 6240 #define DFSDM_FLTCR1_JDMAEN_Pos (5U) 6241 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) 6242 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk 6243 #define DFSDM_FLTCR1_JSCAN_Pos (4U) 6244 #define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) 6245 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk 6246 #define DFSDM_FLTCR1_JSYNC_Pos (3U) 6247 #define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) 6248 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk 6249 #define DFSDM_FLTCR1_JSWSTART_Pos (1U) 6250 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) 6251 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk 6252 #define DFSDM_FLTCR1_DFEN_Pos (0U) 6253 #define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) 6254 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk 6257 #define DFSDM_FLTCR2_AWDCH_Pos (16U) 6258 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) 6259 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk 6260 #define DFSDM_FLTCR2_EXCH_Pos (8U) 6261 #define DFSDM_FLTCR2_EXCH_Msk (0xFFU << DFSDM_FLTCR2_EXCH_Pos) 6262 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk 6263 #define DFSDM_FLTCR2_CKABIE_Pos (6U) 6264 #define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) 6265 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk 6266 #define DFSDM_FLTCR2_SCDIE_Pos (5U) 6267 #define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) 6268 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk 6269 #define DFSDM_FLTCR2_AWDIE_Pos (4U) 6270 #define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) 6271 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk 6272 #define DFSDM_FLTCR2_ROVRIE_Pos (3U) 6273 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) 6274 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk 6275 #define DFSDM_FLTCR2_JOVRIE_Pos (2U) 6276 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) 6277 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk 6278 #define DFSDM_FLTCR2_REOCIE_Pos (1U) 6279 #define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) 6280 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk 6281 #define DFSDM_FLTCR2_JEOCIE_Pos (0U) 6282 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) 6283 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk 6286 #define DFSDM_FLTISR_SCDF_Pos (24U) 6287 #define DFSDM_FLTISR_SCDF_Msk (0xFFU << DFSDM_FLTISR_SCDF_Pos) 6288 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk 6289 #define DFSDM_FLTISR_CKABF_Pos (16U) 6290 #define DFSDM_FLTISR_CKABF_Msk (0xFFU << DFSDM_FLTISR_CKABF_Pos) 6291 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk 6292 #define DFSDM_FLTISR_RCIP_Pos (14U) 6293 #define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) 6294 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk 6295 #define DFSDM_FLTISR_JCIP_Pos (13U) 6296 #define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) 6297 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk 6298 #define DFSDM_FLTISR_AWDF_Pos (4U) 6299 #define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) 6300 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk 6301 #define DFSDM_FLTISR_ROVRF_Pos (3U) 6302 #define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) 6303 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk 6304 #define DFSDM_FLTISR_JOVRF_Pos (2U) 6305 #define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) 6306 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk 6307 #define DFSDM_FLTISR_REOCF_Pos (1U) 6308 #define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) 6309 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk 6310 #define DFSDM_FLTISR_JEOCF_Pos (0U) 6311 #define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) 6312 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk 6315 #define DFSDM_FLTICR_CLRSCSDF_Pos (24U) 6316 #define DFSDM_FLTICR_CLRSCSDF_Msk (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos) 6317 #define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk 6318 #define DFSDM_FLTICR_CLRCKABF_Pos (16U) 6319 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) 6320 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk 6321 #define DFSDM_FLTICR_CLRROVRF_Pos (3U) 6322 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) 6323 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk 6324 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U) 6325 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) 6326 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk 6329 #define DFSDM_FLTJCHGR_JCHG_Pos (0U) 6330 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) 6331 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk 6334 #define DFSDM_FLTFCR_FORD_Pos (29U) 6335 #define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) 6336 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk 6337 #define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) 6338 #define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) 6339 #define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) 6340 #define DFSDM_FLTFCR_FOSR_Pos (16U) 6341 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) 6342 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk 6343 #define DFSDM_FLTFCR_IOSR_Pos (0U) 6344 #define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) 6345 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk 6348 #define DFSDM_FLTJDATAR_JDATA_Pos (8U) 6349 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) 6350 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk 6351 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U) 6352 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) 6353 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk 6356 #define DFSDM_FLTRDATAR_RDATA_Pos (8U) 6357 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) 6358 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk 6359 #define DFSDM_FLTRDATAR_RPEND_Pos (4U) 6360 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) 6361 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk 6362 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U) 6363 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) 6364 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk 6367 #define DFSDM_FLTAWHTR_AWHT_Pos (8U) 6368 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) 6369 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk 6370 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U) 6371 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) 6372 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk 6375 #define DFSDM_FLTAWLTR_AWLT_Pos (8U) 6376 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) 6377 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk 6378 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U) 6379 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) 6380 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk 6383 #define DFSDM_FLTAWSR_AWHTF_Pos (8U) 6384 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) 6385 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk 6386 #define DFSDM_FLTAWSR_AWLTF_Pos (0U) 6387 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) 6388 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk 6391 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U) 6392 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) 6393 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk 6394 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U) 6395 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) 6396 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk 6399 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U) 6400 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) 6401 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk 6402 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U) 6403 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) 6404 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk 6407 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U) 6408 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) 6409 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk 6410 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U) 6411 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) 6412 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk 6415 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U) 6416 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) 6417 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk 6431 #define DCMI_CR_CAPTURE_Pos (0U) 6432 #define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) 6433 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk 6434 #define DCMI_CR_CM_Pos (1U) 6435 #define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) 6436 #define DCMI_CR_CM DCMI_CR_CM_Msk 6437 #define DCMI_CR_CROP_Pos (2U) 6438 #define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) 6439 #define DCMI_CR_CROP DCMI_CR_CROP_Msk 6440 #define DCMI_CR_JPEG_Pos (3U) 6441 #define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) 6442 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk 6443 #define DCMI_CR_ESS_Pos (4U) 6444 #define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) 6445 #define DCMI_CR_ESS DCMI_CR_ESS_Msk 6446 #define DCMI_CR_PCKPOL_Pos (5U) 6447 #define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) 6448 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk 6449 #define DCMI_CR_HSPOL_Pos (6U) 6450 #define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) 6451 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk 6452 #define DCMI_CR_VSPOL_Pos (7U) 6453 #define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) 6454 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk 6455 #define DCMI_CR_FCRC_0 0x00000100U 6456 #define DCMI_CR_FCRC_1 0x00000200U 6457 #define DCMI_CR_EDM_0 0x00000400U 6458 #define DCMI_CR_EDM_1 0x00000800U 6459 #define DCMI_CR_CRE_Pos (12U) 6460 #define DCMI_CR_CRE_Msk (0x1U << DCMI_CR_CRE_Pos) 6461 #define DCMI_CR_CRE DCMI_CR_CRE_Msk 6462 #define DCMI_CR_ENABLE_Pos (14U) 6463 #define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) 6464 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk 6465 #define DCMI_CR_BSM_Pos (16U) 6466 #define DCMI_CR_BSM_Msk (0x3U << DCMI_CR_BSM_Pos) 6467 #define DCMI_CR_BSM DCMI_CR_BSM_Msk 6468 #define DCMI_CR_BSM_0 (0x1U << DCMI_CR_BSM_Pos) 6469 #define DCMI_CR_BSM_1 (0x2U << DCMI_CR_BSM_Pos) 6470 #define DCMI_CR_OEBS_Pos (18U) 6471 #define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) 6472 #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk 6473 #define DCMI_CR_LSM_Pos (19U) 6474 #define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) 6475 #define DCMI_CR_LSM DCMI_CR_LSM_Msk 6476 #define DCMI_CR_OELS_Pos (20U) 6477 #define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) 6478 #define DCMI_CR_OELS DCMI_CR_OELS_Msk 6481 #define DCMI_SR_HSYNC_Pos (0U) 6482 #define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) 6483 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk 6484 #define DCMI_SR_VSYNC_Pos (1U) 6485 #define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) 6486 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk 6487 #define DCMI_SR_FNE_Pos (2U) 6488 #define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) 6489 #define DCMI_SR_FNE DCMI_SR_FNE_Msk 6492 #define DCMI_RIS_FRAME_RIS_Pos (0U) 6493 #define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) 6494 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk 6495 #define DCMI_RIS_OVR_RIS_Pos (1U) 6496 #define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) 6497 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk 6498 #define DCMI_RIS_ERR_RIS_Pos (2U) 6499 #define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) 6500 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk 6501 #define DCMI_RIS_VSYNC_RIS_Pos (3U) 6502 #define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) 6503 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk 6504 #define DCMI_RIS_LINE_RIS_Pos (4U) 6505 #define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) 6506 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk 6509 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS 6510 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS 6511 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS 6512 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS 6513 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS 6516 #define DCMI_IER_FRAME_IE_Pos (0U) 6517 #define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) 6518 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk 6519 #define DCMI_IER_OVR_IE_Pos (1U) 6520 #define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) 6521 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk 6522 #define DCMI_IER_ERR_IE_Pos (2U) 6523 #define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) 6524 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk 6525 #define DCMI_IER_VSYNC_IE_Pos (3U) 6526 #define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) 6527 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk 6528 #define DCMI_IER_LINE_IE_Pos (4U) 6529 #define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) 6530 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk 6534 #define DCMI_MIS_FRAME_MIS_Pos (0U) 6535 #define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) 6536 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk 6537 #define DCMI_MIS_OVR_MIS_Pos (1U) 6538 #define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) 6539 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk 6540 #define DCMI_MIS_ERR_MIS_Pos (2U) 6541 #define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) 6542 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk 6543 #define DCMI_MIS_VSYNC_MIS_Pos (3U) 6544 #define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) 6545 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk 6546 #define DCMI_MIS_LINE_MIS_Pos (4U) 6547 #define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) 6548 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk 6552 #define DCMI_ICR_FRAME_ISC_Pos (0U) 6553 #define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) 6554 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk 6555 #define DCMI_ICR_OVR_ISC_Pos (1U) 6556 #define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) 6557 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk 6558 #define DCMI_ICR_ERR_ISC_Pos (2U) 6559 #define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) 6560 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk 6561 #define DCMI_ICR_VSYNC_ISC_Pos (3U) 6562 #define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) 6563 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk 6564 #define DCMI_ICR_LINE_ISC_Pos (4U) 6565 #define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) 6566 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk 6570 #define DCMI_ESCR_FSC_Pos (0U) 6571 #define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) 6572 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk 6573 #define DCMI_ESCR_LSC_Pos (8U) 6574 #define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) 6575 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk 6576 #define DCMI_ESCR_LEC_Pos (16U) 6577 #define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) 6578 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk 6579 #define DCMI_ESCR_FEC_Pos (24U) 6580 #define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) 6581 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk 6584 #define DCMI_ESUR_FSU_Pos (0U) 6585 #define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) 6586 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk 6587 #define DCMI_ESUR_LSU_Pos (8U) 6588 #define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) 6589 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk 6590 #define DCMI_ESUR_LEU_Pos (16U) 6591 #define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) 6592 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk 6593 #define DCMI_ESUR_FEU_Pos (24U) 6594 #define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) 6595 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk 6598 #define DCMI_CWSTRT_HOFFCNT_Pos (0U) 6599 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) 6600 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk 6601 #define DCMI_CWSTRT_VST_Pos (16U) 6602 #define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) 6603 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk 6606 #define DCMI_CWSIZE_CAPCNT_Pos (0U) 6607 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) 6608 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk 6609 #define DCMI_CWSIZE_VLINE_Pos (16U) 6610 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) 6611 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk 6614 #define DCMI_DR_BYTE0_Pos (0U) 6615 #define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) 6616 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk 6617 #define DCMI_DR_BYTE1_Pos (8U) 6618 #define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) 6619 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk 6620 #define DCMI_DR_BYTE2_Pos (16U) 6621 #define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) 6622 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk 6623 #define DCMI_DR_BYTE3_Pos (24U) 6624 #define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) 6625 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk 6633 #define DMA_SxCR_CHSEL_Pos (25U) 6634 #define DMA_SxCR_CHSEL_Msk (0xFU << DMA_SxCR_CHSEL_Pos) 6635 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk 6636 #define DMA_SxCR_CHSEL_0 (0x1U << DMA_SxCR_CHSEL_Pos) 6637 #define DMA_SxCR_CHSEL_1 (0x2U << DMA_SxCR_CHSEL_Pos) 6638 #define DMA_SxCR_CHSEL_2 (0x4U << DMA_SxCR_CHSEL_Pos) 6639 #define DMA_SxCR_CHSEL_3 (0x8U << DMA_SxCR_CHSEL_Pos) 6640 #define DMA_SxCR_MBURST_Pos (23U) 6641 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) 6642 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk 6643 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) 6644 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) 6645 #define DMA_SxCR_PBURST_Pos (21U) 6646 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) 6647 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk 6648 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) 6649 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) 6650 #define DMA_SxCR_CT_Pos (19U) 6651 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) 6652 #define DMA_SxCR_CT DMA_SxCR_CT_Msk 6653 #define DMA_SxCR_DBM_Pos (18U) 6654 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) 6655 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk 6656 #define DMA_SxCR_PL_Pos (16U) 6657 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) 6658 #define DMA_SxCR_PL DMA_SxCR_PL_Msk 6659 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) 6660 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) 6661 #define DMA_SxCR_PINCOS_Pos (15U) 6662 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) 6663 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk 6664 #define DMA_SxCR_MSIZE_Pos (13U) 6665 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) 6666 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk 6667 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) 6668 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) 6669 #define DMA_SxCR_PSIZE_Pos (11U) 6670 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) 6671 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk 6672 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) 6673 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) 6674 #define DMA_SxCR_MINC_Pos (10U) 6675 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) 6676 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk 6677 #define DMA_SxCR_PINC_Pos (9U) 6678 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) 6679 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk 6680 #define DMA_SxCR_CIRC_Pos (8U) 6681 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) 6682 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk 6683 #define DMA_SxCR_DIR_Pos (6U) 6684 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) 6685 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk 6686 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) 6687 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) 6688 #define DMA_SxCR_PFCTRL_Pos (5U) 6689 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) 6690 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk 6691 #define DMA_SxCR_TCIE_Pos (4U) 6692 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) 6693 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk 6694 #define DMA_SxCR_HTIE_Pos (3U) 6695 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) 6696 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk 6697 #define DMA_SxCR_TEIE_Pos (2U) 6698 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) 6699 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk 6700 #define DMA_SxCR_DMEIE_Pos (1U) 6701 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) 6702 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk 6703 #define DMA_SxCR_EN_Pos (0U) 6704 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) 6705 #define DMA_SxCR_EN DMA_SxCR_EN_Msk 6708 #define DMA_SxNDT_Pos (0U) 6709 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) 6710 #define DMA_SxNDT DMA_SxNDT_Msk 6711 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) 6712 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) 6713 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) 6714 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) 6715 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) 6716 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) 6717 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) 6718 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) 6719 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) 6720 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) 6721 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) 6722 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) 6723 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) 6724 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) 6725 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) 6726 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) 6729 #define DMA_SxFCR_FEIE_Pos (7U) 6730 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) 6731 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk 6732 #define DMA_SxFCR_FS_Pos (3U) 6733 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) 6734 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk 6735 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) 6736 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) 6737 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) 6738 #define DMA_SxFCR_DMDIS_Pos (2U) 6739 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) 6740 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk 6741 #define DMA_SxFCR_FTH_Pos (0U) 6742 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) 6743 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk 6744 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) 6745 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) 6748 #define DMA_LISR_TCIF3_Pos (27U) 6749 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) 6750 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk 6751 #define DMA_LISR_HTIF3_Pos (26U) 6752 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) 6753 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk 6754 #define DMA_LISR_TEIF3_Pos (25U) 6755 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) 6756 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk 6757 #define DMA_LISR_DMEIF3_Pos (24U) 6758 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) 6759 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk 6760 #define DMA_LISR_FEIF3_Pos (22U) 6761 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) 6762 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk 6763 #define DMA_LISR_TCIF2_Pos (21U) 6764 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) 6765 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk 6766 #define DMA_LISR_HTIF2_Pos (20U) 6767 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) 6768 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk 6769 #define DMA_LISR_TEIF2_Pos (19U) 6770 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) 6771 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk 6772 #define DMA_LISR_DMEIF2_Pos (18U) 6773 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) 6774 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk 6775 #define DMA_LISR_FEIF2_Pos (16U) 6776 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) 6777 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk 6778 #define DMA_LISR_TCIF1_Pos (11U) 6779 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) 6780 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk 6781 #define DMA_LISR_HTIF1_Pos (10U) 6782 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) 6783 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk 6784 #define DMA_LISR_TEIF1_Pos (9U) 6785 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) 6786 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk 6787 #define DMA_LISR_DMEIF1_Pos (8U) 6788 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) 6789 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk 6790 #define DMA_LISR_FEIF1_Pos (6U) 6791 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) 6792 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk 6793 #define DMA_LISR_TCIF0_Pos (5U) 6794 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) 6795 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk 6796 #define DMA_LISR_HTIF0_Pos (4U) 6797 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) 6798 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk 6799 #define DMA_LISR_TEIF0_Pos (3U) 6800 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) 6801 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk 6802 #define DMA_LISR_DMEIF0_Pos (2U) 6803 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) 6804 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk 6805 #define DMA_LISR_FEIF0_Pos (0U) 6806 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) 6807 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk 6810 #define DMA_HISR_TCIF7_Pos (27U) 6811 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) 6812 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk 6813 #define DMA_HISR_HTIF7_Pos (26U) 6814 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) 6815 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk 6816 #define DMA_HISR_TEIF7_Pos (25U) 6817 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) 6818 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk 6819 #define DMA_HISR_DMEIF7_Pos (24U) 6820 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) 6821 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk 6822 #define DMA_HISR_FEIF7_Pos (22U) 6823 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) 6824 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk 6825 #define DMA_HISR_TCIF6_Pos (21U) 6826 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) 6827 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk 6828 #define DMA_HISR_HTIF6_Pos (20U) 6829 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) 6830 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk 6831 #define DMA_HISR_TEIF6_Pos (19U) 6832 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) 6833 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk 6834 #define DMA_HISR_DMEIF6_Pos (18U) 6835 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) 6836 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk 6837 #define DMA_HISR_FEIF6_Pos (16U) 6838 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) 6839 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk 6840 #define DMA_HISR_TCIF5_Pos (11U) 6841 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) 6842 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk 6843 #define DMA_HISR_HTIF5_Pos (10U) 6844 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) 6845 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk 6846 #define DMA_HISR_TEIF5_Pos (9U) 6847 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) 6848 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk 6849 #define DMA_HISR_DMEIF5_Pos (8U) 6850 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) 6851 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk 6852 #define DMA_HISR_FEIF5_Pos (6U) 6853 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) 6854 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk 6855 #define DMA_HISR_TCIF4_Pos (5U) 6856 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) 6857 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk 6858 #define DMA_HISR_HTIF4_Pos (4U) 6859 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) 6860 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk 6861 #define DMA_HISR_TEIF4_Pos (3U) 6862 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) 6863 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk 6864 #define DMA_HISR_DMEIF4_Pos (2U) 6865 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) 6866 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk 6867 #define DMA_HISR_FEIF4_Pos (0U) 6868 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) 6869 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk 6872 #define DMA_LIFCR_CTCIF3_Pos (27U) 6873 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) 6874 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk 6875 #define DMA_LIFCR_CHTIF3_Pos (26U) 6876 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) 6877 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk 6878 #define DMA_LIFCR_CTEIF3_Pos (25U) 6879 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) 6880 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk 6881 #define DMA_LIFCR_CDMEIF3_Pos (24U) 6882 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) 6883 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk 6884 #define DMA_LIFCR_CFEIF3_Pos (22U) 6885 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) 6886 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk 6887 #define DMA_LIFCR_CTCIF2_Pos (21U) 6888 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) 6889 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk 6890 #define DMA_LIFCR_CHTIF2_Pos (20U) 6891 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) 6892 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk 6893 #define DMA_LIFCR_CTEIF2_Pos (19U) 6894 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) 6895 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk 6896 #define DMA_LIFCR_CDMEIF2_Pos (18U) 6897 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) 6898 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk 6899 #define DMA_LIFCR_CFEIF2_Pos (16U) 6900 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) 6901 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk 6902 #define DMA_LIFCR_CTCIF1_Pos (11U) 6903 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) 6904 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk 6905 #define DMA_LIFCR_CHTIF1_Pos (10U) 6906 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) 6907 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk 6908 #define DMA_LIFCR_CTEIF1_Pos (9U) 6909 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) 6910 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk 6911 #define DMA_LIFCR_CDMEIF1_Pos (8U) 6912 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) 6913 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk 6914 #define DMA_LIFCR_CFEIF1_Pos (6U) 6915 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) 6916 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk 6917 #define DMA_LIFCR_CTCIF0_Pos (5U) 6918 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) 6919 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk 6920 #define DMA_LIFCR_CHTIF0_Pos (4U) 6921 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) 6922 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk 6923 #define DMA_LIFCR_CTEIF0_Pos (3U) 6924 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) 6925 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk 6926 #define DMA_LIFCR_CDMEIF0_Pos (2U) 6927 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) 6928 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk 6929 #define DMA_LIFCR_CFEIF0_Pos (0U) 6930 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) 6931 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk 6934 #define DMA_HIFCR_CTCIF7_Pos (27U) 6935 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) 6936 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk 6937 #define DMA_HIFCR_CHTIF7_Pos (26U) 6938 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) 6939 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk 6940 #define DMA_HIFCR_CTEIF7_Pos (25U) 6941 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) 6942 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk 6943 #define DMA_HIFCR_CDMEIF7_Pos (24U) 6944 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) 6945 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk 6946 #define DMA_HIFCR_CFEIF7_Pos (22U) 6947 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) 6948 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk 6949 #define DMA_HIFCR_CTCIF6_Pos (21U) 6950 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) 6951 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk 6952 #define DMA_HIFCR_CHTIF6_Pos (20U) 6953 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) 6954 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk 6955 #define DMA_HIFCR_CTEIF6_Pos (19U) 6956 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) 6957 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk 6958 #define DMA_HIFCR_CDMEIF6_Pos (18U) 6959 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) 6960 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk 6961 #define DMA_HIFCR_CFEIF6_Pos (16U) 6962 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) 6963 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk 6964 #define DMA_HIFCR_CTCIF5_Pos (11U) 6965 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) 6966 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk 6967 #define DMA_HIFCR_CHTIF5_Pos (10U) 6968 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) 6969 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk 6970 #define DMA_HIFCR_CTEIF5_Pos (9U) 6971 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) 6972 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk 6973 #define DMA_HIFCR_CDMEIF5_Pos (8U) 6974 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) 6975 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk 6976 #define DMA_HIFCR_CFEIF5_Pos (6U) 6977 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) 6978 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk 6979 #define DMA_HIFCR_CTCIF4_Pos (5U) 6980 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) 6981 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk 6982 #define DMA_HIFCR_CHTIF4_Pos (4U) 6983 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) 6984 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk 6985 #define DMA_HIFCR_CTEIF4_Pos (3U) 6986 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) 6987 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk 6988 #define DMA_HIFCR_CDMEIF4_Pos (2U) 6989 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) 6990 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk 6991 #define DMA_HIFCR_CFEIF4_Pos (0U) 6992 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) 6993 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk 6996 #define DMA_SxPAR_PA_Pos (0U) 6997 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) 6998 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk 7001 #define DMA_SxM0AR_M0A_Pos (0U) 7002 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) 7003 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk 7006 #define DMA_SxM1AR_M1A_Pos (0U) 7007 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) 7008 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk 7018 #define DMA2D_ALPHA_INV_RB_SWAP_SUPPORT 7021 #define DMA2D_CR_START_Pos (0U) 7022 #define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) 7023 #define DMA2D_CR_START DMA2D_CR_START_Msk 7024 #define DMA2D_CR_SUSP_Pos (1U) 7025 #define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) 7026 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk 7027 #define DMA2D_CR_ABORT_Pos (2U) 7028 #define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) 7029 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk 7030 #define DMA2D_CR_TEIE_Pos (8U) 7031 #define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) 7032 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk 7033 #define DMA2D_CR_TCIE_Pos (9U) 7034 #define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) 7035 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk 7036 #define DMA2D_CR_TWIE_Pos (10U) 7037 #define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) 7038 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk 7039 #define DMA2D_CR_CAEIE_Pos (11U) 7040 #define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) 7041 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk 7042 #define DMA2D_CR_CTCIE_Pos (12U) 7043 #define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) 7044 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk 7045 #define DMA2D_CR_CEIE_Pos (13U) 7046 #define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) 7047 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk 7048 #define DMA2D_CR_MODE_Pos (16U) 7049 #define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) 7050 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk 7051 #define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) 7052 #define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) 7056 #define DMA2D_ISR_TEIF_Pos (0U) 7057 #define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) 7058 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk 7059 #define DMA2D_ISR_TCIF_Pos (1U) 7060 #define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) 7061 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk 7062 #define DMA2D_ISR_TWIF_Pos (2U) 7063 #define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) 7064 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk 7065 #define DMA2D_ISR_CAEIF_Pos (3U) 7066 #define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) 7067 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk 7068 #define DMA2D_ISR_CTCIF_Pos (4U) 7069 #define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) 7070 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk 7071 #define DMA2D_ISR_CEIF_Pos (5U) 7072 #define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) 7073 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk 7077 #define DMA2D_IFCR_CTEIF_Pos (0U) 7078 #define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) 7079 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk 7080 #define DMA2D_IFCR_CTCIF_Pos (1U) 7081 #define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) 7082 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk 7083 #define DMA2D_IFCR_CTWIF_Pos (2U) 7084 #define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) 7085 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk 7086 #define DMA2D_IFCR_CAECIF_Pos (3U) 7087 #define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) 7088 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk 7089 #define DMA2D_IFCR_CCTCIF_Pos (4U) 7090 #define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) 7091 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk 7092 #define DMA2D_IFCR_CCEIF_Pos (5U) 7093 #define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) 7094 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk 7097 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF 7098 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF 7099 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF 7100 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF 7101 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF 7102 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF 7106 #define DMA2D_FGMAR_MA_Pos (0U) 7107 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) 7108 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk 7112 #define DMA2D_FGOR_LO_Pos (0U) 7113 #define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) 7114 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk 7118 #define DMA2D_BGMAR_MA_Pos (0U) 7119 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) 7120 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk 7124 #define DMA2D_BGOR_LO_Pos (0U) 7125 #define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) 7126 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk 7130 #define DMA2D_FGPFCCR_CM_Pos (0U) 7131 #define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) 7132 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk 7133 #define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) 7134 #define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) 7135 #define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) 7136 #define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) 7137 #define DMA2D_FGPFCCR_CCM_Pos (4U) 7138 #define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) 7139 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk 7140 #define DMA2D_FGPFCCR_START_Pos (5U) 7141 #define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) 7142 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk 7143 #define DMA2D_FGPFCCR_CS_Pos (8U) 7144 #define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) 7145 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk 7146 #define DMA2D_FGPFCCR_AM_Pos (16U) 7147 #define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) 7148 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk 7149 #define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) 7150 #define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) 7151 #define DMA2D_FGPFCCR_AI_Pos (20U) 7152 #define DMA2D_FGPFCCR_AI_Msk (0x1U << DMA2D_FGPFCCR_AI_Pos) 7153 #define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk 7154 #define DMA2D_FGPFCCR_RBS_Pos (21U) 7155 #define DMA2D_FGPFCCR_RBS_Msk (0x1U << DMA2D_FGPFCCR_RBS_Pos) 7156 #define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk 7157 #define DMA2D_FGPFCCR_ALPHA_Pos (24U) 7158 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) 7159 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk 7163 #define DMA2D_FGCOLR_BLUE_Pos (0U) 7164 #define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) 7165 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk 7166 #define DMA2D_FGCOLR_GREEN_Pos (8U) 7167 #define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) 7168 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk 7169 #define DMA2D_FGCOLR_RED_Pos (16U) 7170 #define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) 7171 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk 7175 #define DMA2D_BGPFCCR_CM_Pos (0U) 7176 #define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) 7177 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk 7178 #define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) 7179 #define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) 7180 #define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) 7181 #define DMA2D_BGPFCCR_CM_3 0x00000008U 7182 #define DMA2D_BGPFCCR_CCM_Pos (4U) 7183 #define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) 7184 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk 7185 #define DMA2D_BGPFCCR_START_Pos (5U) 7186 #define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) 7187 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk 7188 #define DMA2D_BGPFCCR_CS_Pos (8U) 7189 #define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) 7190 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk 7191 #define DMA2D_BGPFCCR_AM_Pos (16U) 7192 #define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) 7193 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk 7194 #define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) 7195 #define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) 7196 #define DMA2D_BGPFCCR_AI_Pos (20U) 7197 #define DMA2D_BGPFCCR_AI_Msk (0x1U << DMA2D_BGPFCCR_AI_Pos) 7198 #define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk 7199 #define DMA2D_BGPFCCR_RBS_Pos (21U) 7200 #define DMA2D_BGPFCCR_RBS_Msk (0x1U << DMA2D_BGPFCCR_RBS_Pos) 7201 #define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk 7202 #define DMA2D_BGPFCCR_ALPHA_Pos (24U) 7203 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) 7204 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk 7208 #define DMA2D_BGCOLR_BLUE_Pos (0U) 7209 #define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) 7210 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk 7211 #define DMA2D_BGCOLR_GREEN_Pos (8U) 7212 #define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) 7213 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk 7214 #define DMA2D_BGCOLR_RED_Pos (16U) 7215 #define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) 7216 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk 7220 #define DMA2D_FGCMAR_MA_Pos (0U) 7221 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) 7222 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk 7226 #define DMA2D_BGCMAR_MA_Pos (0U) 7227 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) 7228 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk 7232 #define DMA2D_OPFCCR_CM_Pos (0U) 7233 #define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) 7234 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk 7235 #define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) 7236 #define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) 7237 #define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) 7238 #define DMA2D_OPFCCR_AI_Pos (20U) 7239 #define DMA2D_OPFCCR_AI_Msk (0x1U << DMA2D_OPFCCR_AI_Pos) 7240 #define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk 7241 #define DMA2D_OPFCCR_RBS_Pos (21U) 7242 #define DMA2D_OPFCCR_RBS_Msk (0x1U << DMA2D_OPFCCR_RBS_Pos) 7243 #define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk 7249 #define DMA2D_OCOLR_BLUE_1 0x000000FFU 7250 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U 7251 #define DMA2D_OCOLR_RED_1 0x00FF0000U 7252 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U 7255 #define DMA2D_OCOLR_BLUE_2 0x0000001FU 7256 #define DMA2D_OCOLR_GREEN_2 0x000007E0U 7257 #define DMA2D_OCOLR_RED_2 0x0000F800U 7260 #define DMA2D_OCOLR_BLUE_3 0x0000001FU 7261 #define DMA2D_OCOLR_GREEN_3 0x000003E0U 7262 #define DMA2D_OCOLR_RED_3 0x00007C00U 7263 #define DMA2D_OCOLR_ALPHA_3 0x00008000U 7266 #define DMA2D_OCOLR_BLUE_4 0x0000000FU 7267 #define DMA2D_OCOLR_GREEN_4 0x000000F0U 7268 #define DMA2D_OCOLR_RED_4 0x00000F00U 7269 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U 7273 #define DMA2D_OMAR_MA_Pos (0U) 7274 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) 7275 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk 7279 #define DMA2D_OOR_LO_Pos (0U) 7280 #define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) 7281 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk 7285 #define DMA2D_NLR_NL_Pos (0U) 7286 #define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) 7287 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk 7288 #define DMA2D_NLR_PL_Pos (16U) 7289 #define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) 7290 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk 7294 #define DMA2D_LWR_LW_Pos (0U) 7295 #define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) 7296 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk 7300 #define DMA2D_AMTCR_EN_Pos (0U) 7301 #define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) 7302 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk 7303 #define DMA2D_AMTCR_DT_Pos (8U) 7304 #define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) 7305 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk 7318 #define EXTI_IMR_MR0_Pos (0U) 7319 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) 7320 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk 7321 #define EXTI_IMR_MR1_Pos (1U) 7322 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) 7323 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk 7324 #define EXTI_IMR_MR2_Pos (2U) 7325 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) 7326 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk 7327 #define EXTI_IMR_MR3_Pos (3U) 7328 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) 7329 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk 7330 #define EXTI_IMR_MR4_Pos (4U) 7331 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) 7332 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk 7333 #define EXTI_IMR_MR5_Pos (5U) 7334 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) 7335 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk 7336 #define EXTI_IMR_MR6_Pos (6U) 7337 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) 7338 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk 7339 #define EXTI_IMR_MR7_Pos (7U) 7340 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) 7341 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk 7342 #define EXTI_IMR_MR8_Pos (8U) 7343 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) 7344 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk 7345 #define EXTI_IMR_MR9_Pos (9U) 7346 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) 7347 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk 7348 #define EXTI_IMR_MR10_Pos (10U) 7349 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) 7350 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk 7351 #define EXTI_IMR_MR11_Pos (11U) 7352 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) 7353 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk 7354 #define EXTI_IMR_MR12_Pos (12U) 7355 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) 7356 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk 7357 #define EXTI_IMR_MR13_Pos (13U) 7358 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) 7359 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk 7360 #define EXTI_IMR_MR14_Pos (14U) 7361 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) 7362 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk 7363 #define EXTI_IMR_MR15_Pos (15U) 7364 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) 7365 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk 7366 #define EXTI_IMR_MR16_Pos (16U) 7367 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) 7368 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk 7369 #define EXTI_IMR_MR17_Pos (17U) 7370 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) 7371 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk 7372 #define EXTI_IMR_MR18_Pos (18U) 7373 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) 7374 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk 7375 #define EXTI_IMR_MR19_Pos (19U) 7376 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) 7377 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk 7378 #define EXTI_IMR_MR20_Pos (20U) 7379 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) 7380 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk 7381 #define EXTI_IMR_MR21_Pos (21U) 7382 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) 7383 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk 7384 #define EXTI_IMR_MR22_Pos (22U) 7385 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) 7386 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk 7387 #define EXTI_IMR_MR23_Pos (23U) 7388 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) 7389 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk 7390 #define EXTI_IMR_MR24_Pos (24U) 7391 #define EXTI_IMR_MR24_Msk (0x1U << EXTI_IMR_MR24_Pos) 7392 #define EXTI_IMR_MR24 EXTI_IMR_MR24_Msk 7395 #define EXTI_IMR_IM0 EXTI_IMR_MR0 7396 #define EXTI_IMR_IM1 EXTI_IMR_MR1 7397 #define EXTI_IMR_IM2 EXTI_IMR_MR2 7398 #define EXTI_IMR_IM3 EXTI_IMR_MR3 7399 #define EXTI_IMR_IM4 EXTI_IMR_MR4 7400 #define EXTI_IMR_IM5 EXTI_IMR_MR5 7401 #define EXTI_IMR_IM6 EXTI_IMR_MR6 7402 #define EXTI_IMR_IM7 EXTI_IMR_MR7 7403 #define EXTI_IMR_IM8 EXTI_IMR_MR8 7404 #define EXTI_IMR_IM9 EXTI_IMR_MR9 7405 #define EXTI_IMR_IM10 EXTI_IMR_MR10 7406 #define EXTI_IMR_IM11 EXTI_IMR_MR11 7407 #define EXTI_IMR_IM12 EXTI_IMR_MR12 7408 #define EXTI_IMR_IM13 EXTI_IMR_MR13 7409 #define EXTI_IMR_IM14 EXTI_IMR_MR14 7410 #define EXTI_IMR_IM15 EXTI_IMR_MR15 7411 #define EXTI_IMR_IM16 EXTI_IMR_MR16 7412 #define EXTI_IMR_IM17 EXTI_IMR_MR17 7413 #define EXTI_IMR_IM18 EXTI_IMR_MR18 7414 #define EXTI_IMR_IM19 EXTI_IMR_MR19 7415 #define EXTI_IMR_IM20 EXTI_IMR_MR20 7416 #define EXTI_IMR_IM21 EXTI_IMR_MR21 7417 #define EXTI_IMR_IM22 EXTI_IMR_MR22 7418 #define EXTI_IMR_IM23 EXTI_IMR_MR23 7419 #define EXTI_IMR_IM24 EXTI_IMR_MR24 7421 #define EXTI_IMR_IM_Pos (0U) 7422 #define EXTI_IMR_IM_Msk (0x1FFFFFFU << EXTI_IMR_IM_Pos) 7423 #define EXTI_IMR_IM EXTI_IMR_IM_Msk 7426 #define EXTI_EMR_MR0_Pos (0U) 7427 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) 7428 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk 7429 #define EXTI_EMR_MR1_Pos (1U) 7430 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) 7431 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk 7432 #define EXTI_EMR_MR2_Pos (2U) 7433 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) 7434 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk 7435 #define EXTI_EMR_MR3_Pos (3U) 7436 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) 7437 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk 7438 #define EXTI_EMR_MR4_Pos (4U) 7439 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) 7440 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk 7441 #define EXTI_EMR_MR5_Pos (5U) 7442 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) 7443 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk 7444 #define EXTI_EMR_MR6_Pos (6U) 7445 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) 7446 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk 7447 #define EXTI_EMR_MR7_Pos (7U) 7448 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) 7449 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk 7450 #define EXTI_EMR_MR8_Pos (8U) 7451 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) 7452 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk 7453 #define EXTI_EMR_MR9_Pos (9U) 7454 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) 7455 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk 7456 #define EXTI_EMR_MR10_Pos (10U) 7457 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) 7458 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk 7459 #define EXTI_EMR_MR11_Pos (11U) 7460 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) 7461 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk 7462 #define EXTI_EMR_MR12_Pos (12U) 7463 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) 7464 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk 7465 #define EXTI_EMR_MR13_Pos (13U) 7466 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) 7467 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk 7468 #define EXTI_EMR_MR14_Pos (14U) 7469 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) 7470 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk 7471 #define EXTI_EMR_MR15_Pos (15U) 7472 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) 7473 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk 7474 #define EXTI_EMR_MR16_Pos (16U) 7475 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) 7476 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk 7477 #define EXTI_EMR_MR17_Pos (17U) 7478 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) 7479 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk 7480 #define EXTI_EMR_MR18_Pos (18U) 7481 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) 7482 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk 7483 #define EXTI_EMR_MR19_Pos (19U) 7484 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) 7485 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk 7486 #define EXTI_EMR_MR20_Pos (20U) 7487 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) 7488 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk 7489 #define EXTI_EMR_MR21_Pos (21U) 7490 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) 7491 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk 7492 #define EXTI_EMR_MR22_Pos (22U) 7493 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) 7494 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk 7495 #define EXTI_EMR_MR23_Pos (23U) 7496 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) 7497 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk 7498 #define EXTI_EMR_MR24_Pos (24U) 7499 #define EXTI_EMR_MR24_Msk (0x1U << EXTI_EMR_MR24_Pos) 7500 #define EXTI_EMR_MR24 EXTI_EMR_MR24_Msk 7503 #define EXTI_EMR_EM0 EXTI_EMR_MR0 7504 #define EXTI_EMR_EM1 EXTI_EMR_MR1 7505 #define EXTI_EMR_EM2 EXTI_EMR_MR2 7506 #define EXTI_EMR_EM3 EXTI_EMR_MR3 7507 #define EXTI_EMR_EM4 EXTI_EMR_MR4 7508 #define EXTI_EMR_EM5 EXTI_EMR_MR5 7509 #define EXTI_EMR_EM6 EXTI_EMR_MR6 7510 #define EXTI_EMR_EM7 EXTI_EMR_MR7 7511 #define EXTI_EMR_EM8 EXTI_EMR_MR8 7512 #define EXTI_EMR_EM9 EXTI_EMR_MR9 7513 #define EXTI_EMR_EM10 EXTI_EMR_MR10 7514 #define EXTI_EMR_EM11 EXTI_EMR_MR11 7515 #define EXTI_EMR_EM12 EXTI_EMR_MR12 7516 #define EXTI_EMR_EM13 EXTI_EMR_MR13 7517 #define EXTI_EMR_EM14 EXTI_EMR_MR14 7518 #define EXTI_EMR_EM15 EXTI_EMR_MR15 7519 #define EXTI_EMR_EM16 EXTI_EMR_MR16 7520 #define EXTI_EMR_EM17 EXTI_EMR_MR17 7521 #define EXTI_EMR_EM18 EXTI_EMR_MR18 7522 #define EXTI_EMR_EM19 EXTI_EMR_MR19 7523 #define EXTI_EMR_EM20 EXTI_EMR_MR20 7524 #define EXTI_EMR_EM21 EXTI_EMR_MR21 7525 #define EXTI_EMR_EM22 EXTI_EMR_MR22 7526 #define EXTI_EMR_EM23 EXTI_EMR_MR23 7527 #define EXTI_EMR_EM24 EXTI_EMR_MR24 7531 #define EXTI_RTSR_TR0_Pos (0U) 7532 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) 7533 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk 7534 #define EXTI_RTSR_TR1_Pos (1U) 7535 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) 7536 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk 7537 #define EXTI_RTSR_TR2_Pos (2U) 7538 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) 7539 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk 7540 #define EXTI_RTSR_TR3_Pos (3U) 7541 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) 7542 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk 7543 #define EXTI_RTSR_TR4_Pos (4U) 7544 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) 7545 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk 7546 #define EXTI_RTSR_TR5_Pos (5U) 7547 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) 7548 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk 7549 #define EXTI_RTSR_TR6_Pos (6U) 7550 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) 7551 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk 7552 #define EXTI_RTSR_TR7_Pos (7U) 7553 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) 7554 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk 7555 #define EXTI_RTSR_TR8_Pos (8U) 7556 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) 7557 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk 7558 #define EXTI_RTSR_TR9_Pos (9U) 7559 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) 7560 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk 7561 #define EXTI_RTSR_TR10_Pos (10U) 7562 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) 7563 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk 7564 #define EXTI_RTSR_TR11_Pos (11U) 7565 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) 7566 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk 7567 #define EXTI_RTSR_TR12_Pos (12U) 7568 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) 7569 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk 7570 #define EXTI_RTSR_TR13_Pos (13U) 7571 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) 7572 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk 7573 #define EXTI_RTSR_TR14_Pos (14U) 7574 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) 7575 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk 7576 #define EXTI_RTSR_TR15_Pos (15U) 7577 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) 7578 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk 7579 #define EXTI_RTSR_TR16_Pos (16U) 7580 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) 7581 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk 7582 #define EXTI_RTSR_TR17_Pos (17U) 7583 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) 7584 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk 7585 #define EXTI_RTSR_TR18_Pos (18U) 7586 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) 7587 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk 7588 #define EXTI_RTSR_TR19_Pos (19U) 7589 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) 7590 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk 7591 #define EXTI_RTSR_TR20_Pos (20U) 7592 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) 7593 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk 7594 #define EXTI_RTSR_TR21_Pos (21U) 7595 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) 7596 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk 7597 #define EXTI_RTSR_TR22_Pos (22U) 7598 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) 7599 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk 7600 #define EXTI_RTSR_TR23_Pos (23U) 7601 #define EXTI_RTSR_TR23_Msk (0x1U << EXTI_RTSR_TR23_Pos) 7602 #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk 7603 #define EXTI_RTSR_TR24_Pos (24U) 7604 #define EXTI_RTSR_TR24_Msk (0x1U << EXTI_RTSR_TR24_Pos) 7605 #define EXTI_RTSR_TR24 EXTI_RTSR_TR24_Msk 7608 #define EXTI_FTSR_TR0_Pos (0U) 7609 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) 7610 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk 7611 #define EXTI_FTSR_TR1_Pos (1U) 7612 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) 7613 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk 7614 #define EXTI_FTSR_TR2_Pos (2U) 7615 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) 7616 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk 7617 #define EXTI_FTSR_TR3_Pos (3U) 7618 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) 7619 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk 7620 #define EXTI_FTSR_TR4_Pos (4U) 7621 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) 7622 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk 7623 #define EXTI_FTSR_TR5_Pos (5U) 7624 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) 7625 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk 7626 #define EXTI_FTSR_TR6_Pos (6U) 7627 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) 7628 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk 7629 #define EXTI_FTSR_TR7_Pos (7U) 7630 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) 7631 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk 7632 #define EXTI_FTSR_TR8_Pos (8U) 7633 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) 7634 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk 7635 #define EXTI_FTSR_TR9_Pos (9U) 7636 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) 7637 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk 7638 #define EXTI_FTSR_TR10_Pos (10U) 7639 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) 7640 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk 7641 #define EXTI_FTSR_TR11_Pos (11U) 7642 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) 7643 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk 7644 #define EXTI_FTSR_TR12_Pos (12U) 7645 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) 7646 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk 7647 #define EXTI_FTSR_TR13_Pos (13U) 7648 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) 7649 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk 7650 #define EXTI_FTSR_TR14_Pos (14U) 7651 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) 7652 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk 7653 #define EXTI_FTSR_TR15_Pos (15U) 7654 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) 7655 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk 7656 #define EXTI_FTSR_TR16_Pos (16U) 7657 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) 7658 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk 7659 #define EXTI_FTSR_TR17_Pos (17U) 7660 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) 7661 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk 7662 #define EXTI_FTSR_TR18_Pos (18U) 7663 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) 7664 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk 7665 #define EXTI_FTSR_TR19_Pos (19U) 7666 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) 7667 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk 7668 #define EXTI_FTSR_TR20_Pos (20U) 7669 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) 7670 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk 7671 #define EXTI_FTSR_TR21_Pos (21U) 7672 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) 7673 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk 7674 #define EXTI_FTSR_TR22_Pos (22U) 7675 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) 7676 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk 7677 #define EXTI_FTSR_TR23_Pos (23U) 7678 #define EXTI_FTSR_TR23_Msk (0x1U << EXTI_FTSR_TR23_Pos) 7679 #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk 7680 #define EXTI_FTSR_TR24_Pos (24U) 7681 #define EXTI_FTSR_TR24_Msk (0x1U << EXTI_FTSR_TR24_Pos) 7682 #define EXTI_FTSR_TR24 EXTI_FTSR_TR24_Msk 7685 #define EXTI_SWIER_SWIER0_Pos (0U) 7686 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) 7687 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk 7688 #define EXTI_SWIER_SWIER1_Pos (1U) 7689 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) 7690 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk 7691 #define EXTI_SWIER_SWIER2_Pos (2U) 7692 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) 7693 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk 7694 #define EXTI_SWIER_SWIER3_Pos (3U) 7695 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) 7696 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk 7697 #define EXTI_SWIER_SWIER4_Pos (4U) 7698 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) 7699 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk 7700 #define EXTI_SWIER_SWIER5_Pos (5U) 7701 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) 7702 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk 7703 #define EXTI_SWIER_SWIER6_Pos (6U) 7704 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) 7705 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk 7706 #define EXTI_SWIER_SWIER7_Pos (7U) 7707 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) 7708 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk 7709 #define EXTI_SWIER_SWIER8_Pos (8U) 7710 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) 7711 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk 7712 #define EXTI_SWIER_SWIER9_Pos (9U) 7713 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) 7714 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk 7715 #define EXTI_SWIER_SWIER10_Pos (10U) 7716 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) 7717 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk 7718 #define EXTI_SWIER_SWIER11_Pos (11U) 7719 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) 7720 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk 7721 #define EXTI_SWIER_SWIER12_Pos (12U) 7722 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) 7723 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk 7724 #define EXTI_SWIER_SWIER13_Pos (13U) 7725 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) 7726 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk 7727 #define EXTI_SWIER_SWIER14_Pos (14U) 7728 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) 7729 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk 7730 #define EXTI_SWIER_SWIER15_Pos (15U) 7731 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) 7732 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk 7733 #define EXTI_SWIER_SWIER16_Pos (16U) 7734 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) 7735 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk 7736 #define EXTI_SWIER_SWIER17_Pos (17U) 7737 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) 7738 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk 7739 #define EXTI_SWIER_SWIER18_Pos (18U) 7740 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) 7741 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk 7742 #define EXTI_SWIER_SWIER19_Pos (19U) 7743 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) 7744 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk 7745 #define EXTI_SWIER_SWIER20_Pos (20U) 7746 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) 7747 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk 7748 #define EXTI_SWIER_SWIER21_Pos (21U) 7749 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) 7750 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk 7751 #define EXTI_SWIER_SWIER22_Pos (22U) 7752 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) 7753 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk 7754 #define EXTI_SWIER_SWIER23_Pos (23U) 7755 #define EXTI_SWIER_SWIER23_Msk (0x1U << EXTI_SWIER_SWIER23_Pos) 7756 #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk 7757 #define EXTI_SWIER_SWIER24_Pos (24U) 7758 #define EXTI_SWIER_SWIER24_Msk (0x1U << EXTI_SWIER_SWIER24_Pos) 7759 #define EXTI_SWIER_SWIER24 EXTI_SWIER_SWIER24_Msk 7762 #define EXTI_PR_PR0_Pos (0U) 7763 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) 7764 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk 7765 #define EXTI_PR_PR1_Pos (1U) 7766 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) 7767 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk 7768 #define EXTI_PR_PR2_Pos (2U) 7769 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) 7770 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk 7771 #define EXTI_PR_PR3_Pos (3U) 7772 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) 7773 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk 7774 #define EXTI_PR_PR4_Pos (4U) 7775 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) 7776 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk 7777 #define EXTI_PR_PR5_Pos (5U) 7778 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) 7779 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk 7780 #define EXTI_PR_PR6_Pos (6U) 7781 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) 7782 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk 7783 #define EXTI_PR_PR7_Pos (7U) 7784 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) 7785 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk 7786 #define EXTI_PR_PR8_Pos (8U) 7787 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) 7788 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk 7789 #define EXTI_PR_PR9_Pos (9U) 7790 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) 7791 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk 7792 #define EXTI_PR_PR10_Pos (10U) 7793 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) 7794 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk 7795 #define EXTI_PR_PR11_Pos (11U) 7796 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) 7797 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk 7798 #define EXTI_PR_PR12_Pos (12U) 7799 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) 7800 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk 7801 #define EXTI_PR_PR13_Pos (13U) 7802 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) 7803 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk 7804 #define EXTI_PR_PR14_Pos (14U) 7805 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) 7806 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk 7807 #define EXTI_PR_PR15_Pos (15U) 7808 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) 7809 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk 7810 #define EXTI_PR_PR16_Pos (16U) 7811 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) 7812 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk 7813 #define EXTI_PR_PR17_Pos (17U) 7814 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) 7815 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk 7816 #define EXTI_PR_PR18_Pos (18U) 7817 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) 7818 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk 7819 #define EXTI_PR_PR19_Pos (19U) 7820 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) 7821 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk 7822 #define EXTI_PR_PR20_Pos (20U) 7823 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) 7824 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk 7825 #define EXTI_PR_PR21_Pos (21U) 7826 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) 7827 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk 7828 #define EXTI_PR_PR22_Pos (22U) 7829 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) 7830 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk 7831 #define EXTI_PR_PR23_Pos (23U) 7832 #define EXTI_PR_PR23_Msk (0x1U << EXTI_PR_PR23_Pos) 7833 #define EXTI_PR_PR23 EXTI_PR_PR23_Msk 7834 #define EXTI_PR_PR24_Pos (24U) 7835 #define EXTI_PR_PR24_Msk (0x1U << EXTI_PR_PR24_Pos) 7836 #define EXTI_PR_PR24 EXTI_PR_PR24_Msk 7846 #define FLASH_SECTOR_TOTAL 24 7849 #define FLASH_ACR_LATENCY_Pos (0U) 7850 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) 7851 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk 7852 #define FLASH_ACR_LATENCY_0WS 0x00000000U 7853 #define FLASH_ACR_LATENCY_1WS 0x00000001U 7854 #define FLASH_ACR_LATENCY_2WS 0x00000002U 7855 #define FLASH_ACR_LATENCY_3WS 0x00000003U 7856 #define FLASH_ACR_LATENCY_4WS 0x00000004U 7857 #define FLASH_ACR_LATENCY_5WS 0x00000005U 7858 #define FLASH_ACR_LATENCY_6WS 0x00000006U 7859 #define FLASH_ACR_LATENCY_7WS 0x00000007U 7860 #define FLASH_ACR_LATENCY_8WS 0x00000008U 7861 #define FLASH_ACR_LATENCY_9WS 0x00000009U 7862 #define FLASH_ACR_LATENCY_10WS 0x0000000AU 7863 #define FLASH_ACR_LATENCY_11WS 0x0000000BU 7864 #define FLASH_ACR_LATENCY_12WS 0x0000000CU 7865 #define FLASH_ACR_LATENCY_13WS 0x0000000DU 7866 #define FLASH_ACR_LATENCY_14WS 0x0000000EU 7867 #define FLASH_ACR_LATENCY_15WS 0x0000000FU 7868 #define FLASH_ACR_PRFTEN_Pos (8U) 7869 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) 7870 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk 7871 #define FLASH_ACR_ARTEN_Pos (9U) 7872 #define FLASH_ACR_ARTEN_Msk (0x1U << FLASH_ACR_ARTEN_Pos) 7873 #define FLASH_ACR_ARTEN FLASH_ACR_ARTEN_Msk 7874 #define FLASH_ACR_ARTRST_Pos (11U) 7875 #define FLASH_ACR_ARTRST_Msk (0x1U << FLASH_ACR_ARTRST_Pos) 7876 #define FLASH_ACR_ARTRST FLASH_ACR_ARTRST_Msk 7879 #define FLASH_SR_EOP_Pos (0U) 7880 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) 7881 #define FLASH_SR_EOP FLASH_SR_EOP_Msk 7882 #define FLASH_SR_OPERR_Pos (1U) 7883 #define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) 7884 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk 7885 #define FLASH_SR_WRPERR_Pos (4U) 7886 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) 7887 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk 7888 #define FLASH_SR_PGAERR_Pos (5U) 7889 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) 7890 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk 7891 #define FLASH_SR_PGPERR_Pos (6U) 7892 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) 7893 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk 7894 #define FLASH_SR_ERSERR_Pos (7U) 7895 #define FLASH_SR_ERSERR_Msk (0x1U << FLASH_SR_ERSERR_Pos) 7896 #define FLASH_SR_ERSERR FLASH_SR_ERSERR_Msk 7897 #define FLASH_SR_BSY_Pos (16U) 7898 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) 7899 #define FLASH_SR_BSY FLASH_SR_BSY_Msk 7902 #define FLASH_CR_PG_Pos (0U) 7903 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) 7904 #define FLASH_CR_PG FLASH_CR_PG_Msk 7905 #define FLASH_CR_SER_Pos (1U) 7906 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) 7907 #define FLASH_CR_SER FLASH_CR_SER_Msk 7908 #define FLASH_CR_MER_Pos (2U) 7909 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) 7910 #define FLASH_CR_MER FLASH_CR_MER_Msk 7911 #define FLASH_CR_MER1 FLASH_CR_MER 7912 #define FLASH_CR_SNB_Pos (3U) 7913 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) 7914 #define FLASH_CR_SNB FLASH_CR_SNB_Msk 7915 #define FLASH_CR_SNB_0 0x00000008U 7916 #define FLASH_CR_SNB_1 0x00000010U 7917 #define FLASH_CR_SNB_2 0x00000020U 7918 #define FLASH_CR_SNB_3 0x00000040U 7919 #define FLASH_CR_SNB_4 0x00000080U 7920 #define FLASH_CR_PSIZE_Pos (8U) 7921 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) 7922 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk 7923 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) 7924 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) 7925 #define FLASH_CR_MER2_Pos (15U) 7926 #define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) 7927 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk 7928 #define FLASH_CR_STRT_Pos (16U) 7929 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) 7930 #define FLASH_CR_STRT FLASH_CR_STRT_Msk 7931 #define FLASH_CR_EOPIE_Pos (24U) 7932 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) 7933 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk 7934 #define FLASH_CR_ERRIE_Pos (25U) 7935 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) 7936 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk 7937 #define FLASH_CR_LOCK_Pos (31U) 7938 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) 7939 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk 7942 #define FLASH_OPTCR_OPTLOCK_Pos (0U) 7943 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) 7944 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk 7945 #define FLASH_OPTCR_OPTSTRT_Pos (1U) 7946 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) 7947 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk 7948 #define FLASH_OPTCR_BOR_LEV_Pos (2U) 7949 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) 7950 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk 7951 #define FLASH_OPTCR_BOR_LEV_0 (0x1U << FLASH_OPTCR_BOR_LEV_Pos) 7952 #define FLASH_OPTCR_BOR_LEV_1 (0x2U << FLASH_OPTCR_BOR_LEV_Pos) 7953 #define FLASH_OPTCR_WWDG_SW_Pos (4U) 7954 #define FLASH_OPTCR_WWDG_SW_Msk (0x1U << FLASH_OPTCR_WWDG_SW_Pos) 7955 #define FLASH_OPTCR_WWDG_SW FLASH_OPTCR_WWDG_SW_Msk 7956 #define FLASH_OPTCR_IWDG_SW_Pos (5U) 7957 #define FLASH_OPTCR_IWDG_SW_Msk (0x1U << FLASH_OPTCR_IWDG_SW_Pos) 7958 #define FLASH_OPTCR_IWDG_SW FLASH_OPTCR_IWDG_SW_Msk 7959 #define FLASH_OPTCR_nRST_STOP_Pos (6U) 7960 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) 7961 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk 7962 #define FLASH_OPTCR_nRST_STDBY_Pos (7U) 7963 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) 7964 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk 7965 #define FLASH_OPTCR_RDP_Pos (8U) 7966 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) 7967 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk 7968 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) 7969 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) 7970 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) 7971 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) 7972 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) 7973 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) 7974 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) 7975 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) 7976 #define FLASH_OPTCR_nWRP_Pos (16U) 7977 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) 7978 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk 7979 #define FLASH_OPTCR_nWRP_0 0x00010000U 7980 #define FLASH_OPTCR_nWRP_1 0x00020000U 7981 #define FLASH_OPTCR_nWRP_2 0x00040000U 7982 #define FLASH_OPTCR_nWRP_3 0x00080000U 7983 #define FLASH_OPTCR_nWRP_4 0x00100000U 7984 #define FLASH_OPTCR_nWRP_5 0x00200000U 7985 #define FLASH_OPTCR_nWRP_6 0x00400000U 7986 #define FLASH_OPTCR_nWRP_7 0x00800000U 7987 #define FLASH_OPTCR_nWRP_8 0x01000000U 7988 #define FLASH_OPTCR_nWRP_9 0x02000000U 7989 #define FLASH_OPTCR_nWRP_10 0x04000000U 7990 #define FLASH_OPTCR_nWRP_11 0x08000000U 7991 #define FLASH_OPTCR_nDBOOT_Pos (28U) 7992 #define FLASH_OPTCR_nDBOOT_Msk (0x1U << FLASH_OPTCR_nDBOOT_Pos) 7993 #define FLASH_OPTCR_nDBOOT FLASH_OPTCR_nDBOOT_Msk 7994 #define FLASH_OPTCR_nDBANK_Pos (29U) 7995 #define FLASH_OPTCR_nDBANK_Msk (0x1U << FLASH_OPTCR_nDBANK_Pos) 7996 #define FLASH_OPTCR_nDBANK FLASH_OPTCR_nDBANK_Msk 7997 #define FLASH_OPTCR_IWDG_STDBY_Pos (30U) 7998 #define FLASH_OPTCR_IWDG_STDBY_Msk (0x1U << FLASH_OPTCR_IWDG_STDBY_Pos) 7999 #define FLASH_OPTCR_IWDG_STDBY FLASH_OPTCR_IWDG_STDBY_Msk 8000 #define FLASH_OPTCR_IWDG_STOP_Pos (31U) 8001 #define FLASH_OPTCR_IWDG_STOP_Msk (0x1U << FLASH_OPTCR_IWDG_STOP_Pos) 8002 #define FLASH_OPTCR_IWDG_STOP FLASH_OPTCR_IWDG_STOP_Msk 8005 #define FLASH_OPTCR1_BOOT_ADD0_Pos (0U) 8006 #define FLASH_OPTCR1_BOOT_ADD0_Msk (0xFFFFU << FLASH_OPTCR1_BOOT_ADD0_Pos) 8007 #define FLASH_OPTCR1_BOOT_ADD0 FLASH_OPTCR1_BOOT_ADD0_Msk 8008 #define FLASH_OPTCR1_BOOT_ADD1_Pos (16U) 8009 #define FLASH_OPTCR1_BOOT_ADD1_Msk (0xFFFFU << FLASH_OPTCR1_BOOT_ADD1_Pos) 8010 #define FLASH_OPTCR1_BOOT_ADD1 FLASH_OPTCR1_BOOT_ADD1_Msk 8019 #define FMC_BCR1_MBKEN_Pos (0U) 8020 #define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) 8021 #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk 8022 #define FMC_BCR1_MUXEN_Pos (1U) 8023 #define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) 8024 #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk 8025 #define FMC_BCR1_MTYP_Pos (2U) 8026 #define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) 8027 #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk 8028 #define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) 8029 #define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) 8030 #define FMC_BCR1_MWID_Pos (4U) 8031 #define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) 8032 #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk 8033 #define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) 8034 #define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) 8035 #define FMC_BCR1_FACCEN_Pos (6U) 8036 #define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) 8037 #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk 8038 #define FMC_BCR1_BURSTEN_Pos (8U) 8039 #define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) 8040 #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk 8041 #define FMC_BCR1_WAITPOL_Pos (9U) 8042 #define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) 8043 #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk 8044 #define FMC_BCR1_WRAPMOD_Pos (10U) 8045 #define FMC_BCR1_WRAPMOD_Msk (0x1U << FMC_BCR1_WRAPMOD_Pos) 8046 #define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk 8047 #define FMC_BCR1_WAITCFG_Pos (11U) 8048 #define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) 8049 #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk 8050 #define FMC_BCR1_WREN_Pos (12U) 8051 #define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) 8052 #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk 8053 #define FMC_BCR1_WAITEN_Pos (13U) 8054 #define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) 8055 #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk 8056 #define FMC_BCR1_EXTMOD_Pos (14U) 8057 #define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) 8058 #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk 8059 #define FMC_BCR1_ASYNCWAIT_Pos (15U) 8060 #define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) 8061 #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk 8062 #define FMC_BCR1_CPSIZE_Pos (16U) 8063 #define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) 8064 #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk 8065 #define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) 8066 #define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) 8067 #define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) 8068 #define FMC_BCR1_CBURSTRW_Pos (19U) 8069 #define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) 8070 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk 8071 #define FMC_BCR1_CCLKEN_Pos (20U) 8072 #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) 8073 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk 8074 #define FMC_BCR1_WFDIS_Pos (21U) 8075 #define FMC_BCR1_WFDIS_Msk (0x1U << FMC_BCR1_WFDIS_Pos) 8076 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk 8079 #define FMC_BCR2_MBKEN_Pos (0U) 8080 #define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) 8081 #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk 8082 #define FMC_BCR2_MUXEN_Pos (1U) 8083 #define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) 8084 #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk 8085 #define FMC_BCR2_MTYP_Pos (2U) 8086 #define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) 8087 #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk 8088 #define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) 8089 #define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) 8090 #define FMC_BCR2_MWID_Pos (4U) 8091 #define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) 8092 #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk 8093 #define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) 8094 #define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) 8095 #define FMC_BCR2_FACCEN_Pos (6U) 8096 #define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) 8097 #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk 8098 #define FMC_BCR2_BURSTEN_Pos (8U) 8099 #define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) 8100 #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk 8101 #define FMC_BCR2_WAITPOL_Pos (9U) 8102 #define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) 8103 #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk 8104 #define FMC_BCR2_WRAPMOD_Pos (10U) 8105 #define FMC_BCR2_WRAPMOD_Msk (0x1U << FMC_BCR2_WRAPMOD_Pos) 8106 #define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk 8107 #define FMC_BCR2_WAITCFG_Pos (11U) 8108 #define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) 8109 #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk 8110 #define FMC_BCR2_WREN_Pos (12U) 8111 #define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) 8112 #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk 8113 #define FMC_BCR2_WAITEN_Pos (13U) 8114 #define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) 8115 #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk 8116 #define FMC_BCR2_EXTMOD_Pos (14U) 8117 #define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) 8118 #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk 8119 #define FMC_BCR2_ASYNCWAIT_Pos (15U) 8120 #define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) 8121 #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk 8122 #define FMC_BCR2_CPSIZE_Pos (16U) 8123 #define FMC_BCR2_CPSIZE_Msk (0x7U << FMC_BCR2_CPSIZE_Pos) 8124 #define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk 8125 #define FMC_BCR2_CPSIZE_0 (0x1U << FMC_BCR2_CPSIZE_Pos) 8126 #define FMC_BCR2_CPSIZE_1 (0x2U << FMC_BCR2_CPSIZE_Pos) 8127 #define FMC_BCR2_CPSIZE_2 (0x4U << FMC_BCR2_CPSIZE_Pos) 8128 #define FMC_BCR2_CBURSTRW_Pos (19U) 8129 #define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) 8130 #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk 8133 #define FMC_BCR3_MBKEN_Pos (0U) 8134 #define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) 8135 #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk 8136 #define FMC_BCR3_MUXEN_Pos (1U) 8137 #define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) 8138 #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk 8139 #define FMC_BCR3_MTYP_Pos (2U) 8140 #define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) 8141 #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk 8142 #define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) 8143 #define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) 8144 #define FMC_BCR3_MWID_Pos (4U) 8145 #define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) 8146 #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk 8147 #define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) 8148 #define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) 8149 #define FMC_BCR3_FACCEN_Pos (6U) 8150 #define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) 8151 #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk 8152 #define FMC_BCR3_BURSTEN_Pos (8U) 8153 #define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) 8154 #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk 8155 #define FMC_BCR3_WAITPOL_Pos (9U) 8156 #define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) 8157 #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk 8158 #define FMC_BCR3_WRAPMOD_Pos (10U) 8159 #define FMC_BCR3_WRAPMOD_Msk (0x1U << FMC_BCR3_WRAPMOD_Pos) 8160 #define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk 8161 #define FMC_BCR3_WAITCFG_Pos (11U) 8162 #define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) 8163 #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk 8164 #define FMC_BCR3_WREN_Pos (12U) 8165 #define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) 8166 #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk 8167 #define FMC_BCR3_WAITEN_Pos (13U) 8168 #define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) 8169 #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk 8170 #define FMC_BCR3_EXTMOD_Pos (14U) 8171 #define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) 8172 #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk 8173 #define FMC_BCR3_ASYNCWAIT_Pos (15U) 8174 #define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) 8175 #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk 8176 #define FMC_BCR3_CPSIZE_Pos (16U) 8177 #define FMC_BCR3_CPSIZE_Msk (0x7U << FMC_BCR3_CPSIZE_Pos) 8178 #define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk 8179 #define FMC_BCR3_CPSIZE_0 (0x1U << FMC_BCR3_CPSIZE_Pos) 8180 #define FMC_BCR3_CPSIZE_1 (0x2U << FMC_BCR3_CPSIZE_Pos) 8181 #define FMC_BCR3_CPSIZE_2 (0x4U << FMC_BCR3_CPSIZE_Pos) 8182 #define FMC_BCR3_CBURSTRW_Pos (19U) 8183 #define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) 8184 #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk 8187 #define FMC_BCR4_MBKEN_Pos (0U) 8188 #define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) 8189 #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk 8190 #define FMC_BCR4_MUXEN_Pos (1U) 8191 #define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) 8192 #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk 8193 #define FMC_BCR4_MTYP_Pos (2U) 8194 #define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) 8195 #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk 8196 #define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) 8197 #define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) 8198 #define FMC_BCR4_MWID_Pos (4U) 8199 #define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) 8200 #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk 8201 #define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) 8202 #define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) 8203 #define FMC_BCR4_FACCEN_Pos (6U) 8204 #define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) 8205 #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk 8206 #define FMC_BCR4_BURSTEN_Pos (8U) 8207 #define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) 8208 #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk 8209 #define FMC_BCR4_WAITPOL_Pos (9U) 8210 #define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) 8211 #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk 8212 #define FMC_BCR4_WRAPMOD_Pos (10U) 8213 #define FMC_BCR4_WRAPMOD_Msk (0x1U << FMC_BCR4_WRAPMOD_Pos) 8214 #define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk 8215 #define FMC_BCR4_WAITCFG_Pos (11U) 8216 #define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) 8217 #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk 8218 #define FMC_BCR4_WREN_Pos (12U) 8219 #define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) 8220 #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk 8221 #define FMC_BCR4_WAITEN_Pos (13U) 8222 #define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) 8223 #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk 8224 #define FMC_BCR4_EXTMOD_Pos (14U) 8225 #define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) 8226 #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk 8227 #define FMC_BCR4_ASYNCWAIT_Pos (15U) 8228 #define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) 8229 #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk 8230 #define FMC_BCR4_CPSIZE_Pos (16U) 8231 #define FMC_BCR4_CPSIZE_Msk (0x7U << FMC_BCR4_CPSIZE_Pos) 8232 #define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk 8233 #define FMC_BCR4_CPSIZE_0 (0x1U << FMC_BCR4_CPSIZE_Pos) 8234 #define FMC_BCR4_CPSIZE_1 (0x2U << FMC_BCR4_CPSIZE_Pos) 8235 #define FMC_BCR4_CPSIZE_2 (0x4U << FMC_BCR4_CPSIZE_Pos) 8236 #define FMC_BCR4_CBURSTRW_Pos (19U) 8237 #define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) 8238 #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk 8241 #define FMC_BTR1_ADDSET_Pos (0U) 8242 #define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) 8243 #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk 8244 #define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) 8245 #define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) 8246 #define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) 8247 #define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) 8248 #define FMC_BTR1_ADDHLD_Pos (4U) 8249 #define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) 8250 #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk 8251 #define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) 8252 #define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) 8253 #define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) 8254 #define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) 8255 #define FMC_BTR1_DATAST_Pos (8U) 8256 #define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) 8257 #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk 8258 #define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) 8259 #define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) 8260 #define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) 8261 #define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) 8262 #define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) 8263 #define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) 8264 #define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) 8265 #define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) 8266 #define FMC_BTR1_BUSTURN_Pos (16U) 8267 #define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) 8268 #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk 8269 #define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) 8270 #define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) 8271 #define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) 8272 #define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) 8273 #define FMC_BTR1_CLKDIV_Pos (20U) 8274 #define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) 8275 #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk 8276 #define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) 8277 #define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) 8278 #define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) 8279 #define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) 8280 #define FMC_BTR1_DATLAT_Pos (24U) 8281 #define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) 8282 #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk 8283 #define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) 8284 #define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) 8285 #define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) 8286 #define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) 8287 #define FMC_BTR1_ACCMOD_Pos (28U) 8288 #define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) 8289 #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk 8290 #define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) 8291 #define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) 8294 #define FMC_BTR2_ADDSET_Pos (0U) 8295 #define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) 8296 #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk 8297 #define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) 8298 #define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) 8299 #define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) 8300 #define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) 8301 #define FMC_BTR2_ADDHLD_Pos (4U) 8302 #define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) 8303 #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk 8304 #define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) 8305 #define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) 8306 #define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) 8307 #define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) 8308 #define FMC_BTR2_DATAST_Pos (8U) 8309 #define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) 8310 #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk 8311 #define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) 8312 #define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) 8313 #define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) 8314 #define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) 8315 #define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) 8316 #define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) 8317 #define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) 8318 #define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) 8319 #define FMC_BTR2_BUSTURN_Pos (16U) 8320 #define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) 8321 #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk 8322 #define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) 8323 #define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) 8324 #define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) 8325 #define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) 8326 #define FMC_BTR2_CLKDIV_Pos (20U) 8327 #define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) 8328 #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk 8329 #define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) 8330 #define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) 8331 #define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) 8332 #define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) 8333 #define FMC_BTR2_DATLAT_Pos (24U) 8334 #define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) 8335 #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk 8336 #define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) 8337 #define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) 8338 #define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) 8339 #define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) 8340 #define FMC_BTR2_ACCMOD_Pos (28U) 8341 #define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) 8342 #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk 8343 #define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) 8344 #define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) 8347 #define FMC_BTR3_ADDSET_Pos (0U) 8348 #define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) 8349 #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk 8350 #define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) 8351 #define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) 8352 #define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) 8353 #define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) 8354 #define FMC_BTR3_ADDHLD_Pos (4U) 8355 #define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) 8356 #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk 8357 #define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) 8358 #define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) 8359 #define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) 8360 #define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) 8361 #define FMC_BTR3_DATAST_Pos (8U) 8362 #define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) 8363 #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk 8364 #define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) 8365 #define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) 8366 #define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) 8367 #define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) 8368 #define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) 8369 #define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) 8370 #define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) 8371 #define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) 8372 #define FMC_BTR3_BUSTURN_Pos (16U) 8373 #define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) 8374 #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk 8375 #define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) 8376 #define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) 8377 #define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) 8378 #define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) 8379 #define FMC_BTR3_CLKDIV_Pos (20U) 8380 #define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) 8381 #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk 8382 #define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) 8383 #define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) 8384 #define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) 8385 #define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) 8386 #define FMC_BTR3_DATLAT_Pos (24U) 8387 #define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) 8388 #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk 8389 #define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) 8390 #define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) 8391 #define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) 8392 #define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) 8393 #define FMC_BTR3_ACCMOD_Pos (28U) 8394 #define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) 8395 #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk 8396 #define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) 8397 #define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) 8400 #define FMC_BTR4_ADDSET_Pos (0U) 8401 #define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) 8402 #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk 8403 #define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) 8404 #define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) 8405 #define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) 8406 #define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) 8407 #define FMC_BTR4_ADDHLD_Pos (4U) 8408 #define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) 8409 #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk 8410 #define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) 8411 #define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) 8412 #define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) 8413 #define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) 8414 #define FMC_BTR4_DATAST_Pos (8U) 8415 #define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) 8416 #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk 8417 #define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) 8418 #define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) 8419 #define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) 8420 #define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) 8421 #define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) 8422 #define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) 8423 #define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) 8424 #define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) 8425 #define FMC_BTR4_BUSTURN_Pos (16U) 8426 #define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) 8427 #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk 8428 #define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) 8429 #define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) 8430 #define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) 8431 #define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) 8432 #define FMC_BTR4_CLKDIV_Pos (20U) 8433 #define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) 8434 #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk 8435 #define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) 8436 #define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) 8437 #define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) 8438 #define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) 8439 #define FMC_BTR4_DATLAT_Pos (24U) 8440 #define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) 8441 #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk 8442 #define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) 8443 #define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) 8444 #define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) 8445 #define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) 8446 #define FMC_BTR4_ACCMOD_Pos (28U) 8447 #define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) 8448 #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk 8449 #define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) 8450 #define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) 8453 #define FMC_BWTR1_ADDSET_Pos (0U) 8454 #define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) 8455 #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk 8456 #define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) 8457 #define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) 8458 #define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) 8459 #define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) 8460 #define FMC_BWTR1_ADDHLD_Pos (4U) 8461 #define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) 8462 #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk 8463 #define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) 8464 #define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) 8465 #define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) 8466 #define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) 8467 #define FMC_BWTR1_DATAST_Pos (8U) 8468 #define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) 8469 #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk 8470 #define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) 8471 #define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) 8472 #define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) 8473 #define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) 8474 #define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) 8475 #define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) 8476 #define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) 8477 #define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) 8478 #define FMC_BWTR1_BUSTURN_Pos (16U) 8479 #define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) 8480 #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk 8481 #define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) 8482 #define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) 8483 #define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) 8484 #define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) 8485 #define FMC_BWTR1_ACCMOD_Pos (28U) 8486 #define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) 8487 #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk 8488 #define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) 8489 #define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) 8492 #define FMC_BWTR2_ADDSET_Pos (0U) 8493 #define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) 8494 #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk 8495 #define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) 8496 #define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) 8497 #define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) 8498 #define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) 8499 #define FMC_BWTR2_ADDHLD_Pos (4U) 8500 #define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) 8501 #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk 8502 #define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) 8503 #define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) 8504 #define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) 8505 #define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) 8506 #define FMC_BWTR2_DATAST_Pos (8U) 8507 #define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) 8508 #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk 8509 #define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) 8510 #define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) 8511 #define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) 8512 #define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) 8513 #define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) 8514 #define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) 8515 #define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) 8516 #define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) 8517 #define FMC_BWTR2_BUSTURN_Pos (16U) 8518 #define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) 8519 #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk 8520 #define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) 8521 #define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) 8522 #define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) 8523 #define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) 8524 #define FMC_BWTR2_ACCMOD_Pos (28U) 8525 #define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) 8526 #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk 8527 #define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) 8528 #define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) 8531 #define FMC_BWTR3_ADDSET_Pos (0U) 8532 #define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) 8533 #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk 8534 #define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) 8535 #define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) 8536 #define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) 8537 #define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) 8538 #define FMC_BWTR3_ADDHLD_Pos (4U) 8539 #define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) 8540 #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk 8541 #define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) 8542 #define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) 8543 #define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) 8544 #define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) 8545 #define FMC_BWTR3_DATAST_Pos (8U) 8546 #define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) 8547 #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk 8548 #define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) 8549 #define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) 8550 #define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) 8551 #define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) 8552 #define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) 8553 #define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) 8554 #define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) 8555 #define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) 8556 #define FMC_BWTR3_BUSTURN_Pos (16U) 8557 #define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) 8558 #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk 8559 #define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) 8560 #define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) 8561 #define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) 8562 #define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) 8563 #define FMC_BWTR3_ACCMOD_Pos (28U) 8564 #define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) 8565 #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk 8566 #define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) 8567 #define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) 8570 #define FMC_BWTR4_ADDSET_Pos (0U) 8571 #define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) 8572 #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk 8573 #define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) 8574 #define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) 8575 #define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) 8576 #define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) 8577 #define FMC_BWTR4_ADDHLD_Pos (4U) 8578 #define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) 8579 #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk 8580 #define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) 8581 #define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) 8582 #define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) 8583 #define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) 8584 #define FMC_BWTR4_DATAST_Pos (8U) 8585 #define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) 8586 #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk 8587 #define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) 8588 #define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) 8589 #define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) 8590 #define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) 8591 #define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) 8592 #define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) 8593 #define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) 8594 #define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) 8595 #define FMC_BWTR4_BUSTURN_Pos (16U) 8596 #define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) 8597 #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk 8598 #define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) 8599 #define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) 8600 #define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) 8601 #define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) 8602 #define FMC_BWTR4_ACCMOD_Pos (28U) 8603 #define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) 8604 #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk 8605 #define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) 8606 #define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) 8609 #define FMC_PCR_PWAITEN_Pos (1U) 8610 #define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) 8611 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk 8612 #define FMC_PCR_PBKEN_Pos (2U) 8613 #define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) 8614 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk 8615 #define FMC_PCR_PTYP_Pos (3U) 8616 #define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) 8617 #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk 8618 #define FMC_PCR_PWID_Pos (4U) 8619 #define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) 8620 #define FMC_PCR_PWID FMC_PCR_PWID_Msk 8621 #define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) 8622 #define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) 8623 #define FMC_PCR_ECCEN_Pos (6U) 8624 #define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) 8625 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk 8626 #define FMC_PCR_TCLR_Pos (9U) 8627 #define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) 8628 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk 8629 #define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) 8630 #define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) 8631 #define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) 8632 #define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) 8633 #define FMC_PCR_TAR_Pos (13U) 8634 #define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) 8635 #define FMC_PCR_TAR FMC_PCR_TAR_Msk 8636 #define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) 8637 #define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) 8638 #define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) 8639 #define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) 8640 #define FMC_PCR_ECCPS_Pos (17U) 8641 #define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) 8642 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk 8643 #define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) 8644 #define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) 8645 #define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) 8648 #define FMC_SR_IRS_Pos (0U) 8649 #define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) 8650 #define FMC_SR_IRS FMC_SR_IRS_Msk 8651 #define FMC_SR_ILS_Pos (1U) 8652 #define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) 8653 #define FMC_SR_ILS FMC_SR_ILS_Msk 8654 #define FMC_SR_IFS_Pos (2U) 8655 #define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) 8656 #define FMC_SR_IFS FMC_SR_IFS_Msk 8657 #define FMC_SR_IREN_Pos (3U) 8658 #define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) 8659 #define FMC_SR_IREN FMC_SR_IREN_Msk 8660 #define FMC_SR_ILEN_Pos (4U) 8661 #define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) 8662 #define FMC_SR_ILEN FMC_SR_ILEN_Msk 8663 #define FMC_SR_IFEN_Pos (5U) 8664 #define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) 8665 #define FMC_SR_IFEN FMC_SR_IFEN_Msk 8666 #define FMC_SR_FEMPT_Pos (6U) 8667 #define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) 8668 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk 8671 #define FMC_PMEM_MEMSET3_Pos (0U) 8672 #define FMC_PMEM_MEMSET3_Msk (0xFFU << FMC_PMEM_MEMSET3_Pos) 8673 #define FMC_PMEM_MEMSET3 FMC_PMEM_MEMSET3_Msk 8674 #define FMC_PMEM_MEMSET3_0 (0x01U << FMC_PMEM_MEMSET3_Pos) 8675 #define FMC_PMEM_MEMSET3_1 (0x02U << FMC_PMEM_MEMSET3_Pos) 8676 #define FMC_PMEM_MEMSET3_2 (0x04U << FMC_PMEM_MEMSET3_Pos) 8677 #define FMC_PMEM_MEMSET3_3 (0x08U << FMC_PMEM_MEMSET3_Pos) 8678 #define FMC_PMEM_MEMSET3_4 (0x10U << FMC_PMEM_MEMSET3_Pos) 8679 #define FMC_PMEM_MEMSET3_5 (0x20U << FMC_PMEM_MEMSET3_Pos) 8680 #define FMC_PMEM_MEMSET3_6 (0x40U << FMC_PMEM_MEMSET3_Pos) 8681 #define FMC_PMEM_MEMSET3_7 (0x80U << FMC_PMEM_MEMSET3_Pos) 8682 #define FMC_PMEM_MEMWAIT3_Pos (8U) 8683 #define FMC_PMEM_MEMWAIT3_Msk (0xFFU << FMC_PMEM_MEMWAIT3_Pos) 8684 #define FMC_PMEM_MEMWAIT3 FMC_PMEM_MEMWAIT3_Msk 8685 #define FMC_PMEM_MEMWAIT3_0 (0x01U << FMC_PMEM_MEMWAIT3_Pos) 8686 #define FMC_PMEM_MEMWAIT3_1 (0x02U << FMC_PMEM_MEMWAIT3_Pos) 8687 #define FMC_PMEM_MEMWAIT3_2 (0x04U << FMC_PMEM_MEMWAIT3_Pos) 8688 #define FMC_PMEM_MEMWAIT3_3 (0x08U << FMC_PMEM_MEMWAIT3_Pos) 8689 #define FMC_PMEM_MEMWAIT3_4 (0x10U << FMC_PMEM_MEMWAIT3_Pos) 8690 #define FMC_PMEM_MEMWAIT3_5 (0x20U << FMC_PMEM_MEMWAIT3_Pos) 8691 #define FMC_PMEM_MEMWAIT3_6 (0x40U << FMC_PMEM_MEMWAIT3_Pos) 8692 #define FMC_PMEM_MEMWAIT3_7 (0x80U << FMC_PMEM_MEMWAIT3_Pos) 8693 #define FMC_PMEM_MEMHOLD3_Pos (16U) 8694 #define FMC_PMEM_MEMHOLD3_Msk (0xFFU << FMC_PMEM_MEMHOLD3_Pos) 8695 #define FMC_PMEM_MEMHOLD3 FMC_PMEM_MEMHOLD3_Msk 8696 #define FMC_PMEM_MEMHOLD3_0 (0x01U << FMC_PMEM_MEMHOLD3_Pos) 8697 #define FMC_PMEM_MEMHOLD3_1 (0x02U << FMC_PMEM_MEMHOLD3_Pos) 8698 #define FMC_PMEM_MEMHOLD3_2 (0x04U << FMC_PMEM_MEMHOLD3_Pos) 8699 #define FMC_PMEM_MEMHOLD3_3 (0x08U << FMC_PMEM_MEMHOLD3_Pos) 8700 #define FMC_PMEM_MEMHOLD3_4 (0x10U << FMC_PMEM_MEMHOLD3_Pos) 8701 #define FMC_PMEM_MEMHOLD3_5 (0x20U << FMC_PMEM_MEMHOLD3_Pos) 8702 #define FMC_PMEM_MEMHOLD3_6 (0x40U << FMC_PMEM_MEMHOLD3_Pos) 8703 #define FMC_PMEM_MEMHOLD3_7 (0x80U << FMC_PMEM_MEMHOLD3_Pos) 8704 #define FMC_PMEM_MEMHIZ3_Pos (24U) 8705 #define FMC_PMEM_MEMHIZ3_Msk (0xFFU << FMC_PMEM_MEMHIZ3_Pos) 8706 #define FMC_PMEM_MEMHIZ3 FMC_PMEM_MEMHIZ3_Msk 8707 #define FMC_PMEM_MEMHIZ3_0 (0x01U << FMC_PMEM_MEMHIZ3_Pos) 8708 #define FMC_PMEM_MEMHIZ3_1 (0x02U << FMC_PMEM_MEMHIZ3_Pos) 8709 #define FMC_PMEM_MEMHIZ3_2 (0x04U << FMC_PMEM_MEMHIZ3_Pos) 8710 #define FMC_PMEM_MEMHIZ3_3 (0x08U << FMC_PMEM_MEMHIZ3_Pos) 8711 #define FMC_PMEM_MEMHIZ3_4 (0x10U << FMC_PMEM_MEMHIZ3_Pos) 8712 #define FMC_PMEM_MEMHIZ3_5 (0x20U << FMC_PMEM_MEMHIZ3_Pos) 8713 #define FMC_PMEM_MEMHIZ3_6 (0x40U << FMC_PMEM_MEMHIZ3_Pos) 8714 #define FMC_PMEM_MEMHIZ3_7 (0x80U << FMC_PMEM_MEMHIZ3_Pos) 8717 #define FMC_PATT_ATTSET3_Pos (0U) 8718 #define FMC_PATT_ATTSET3_Msk (0xFFU << FMC_PATT_ATTSET3_Pos) 8719 #define FMC_PATT_ATTSET3 FMC_PATT_ATTSET3_Msk 8720 #define FMC_PATT_ATTSET3_0 (0x01U << FMC_PATT_ATTSET3_Pos) 8721 #define FMC_PATT_ATTSET3_1 (0x02U << FMC_PATT_ATTSET3_Pos) 8722 #define FMC_PATT_ATTSET3_2 (0x04U << FMC_PATT_ATTSET3_Pos) 8723 #define FMC_PATT_ATTSET3_3 (0x08U << FMC_PATT_ATTSET3_Pos) 8724 #define FMC_PATT_ATTSET3_4 (0x10U << FMC_PATT_ATTSET3_Pos) 8725 #define FMC_PATT_ATTSET3_5 (0x20U << FMC_PATT_ATTSET3_Pos) 8726 #define FMC_PATT_ATTSET3_6 (0x40U << FMC_PATT_ATTSET3_Pos) 8727 #define FMC_PATT_ATTSET3_7 (0x80U << FMC_PATT_ATTSET3_Pos) 8728 #define FMC_PATT_ATTWAIT3_Pos (8U) 8729 #define FMC_PATT_ATTWAIT3_Msk (0xFFU << FMC_PATT_ATTWAIT3_Pos) 8730 #define FMC_PATT_ATTWAIT3 FMC_PATT_ATTWAIT3_Msk 8731 #define FMC_PATT_ATTWAIT3_0 (0x01U << FMC_PATT_ATTWAIT3_Pos) 8732 #define FMC_PATT_ATTWAIT3_1 (0x02U << FMC_PATT_ATTWAIT3_Pos) 8733 #define FMC_PATT_ATTWAIT3_2 (0x04U << FMC_PATT_ATTWAIT3_Pos) 8734 #define FMC_PATT_ATTWAIT3_3 (0x08U << FMC_PATT_ATTWAIT3_Pos) 8735 #define FMC_PATT_ATTWAIT3_4 (0x10U << FMC_PATT_ATTWAIT3_Pos) 8736 #define FMC_PATT_ATTWAIT3_5 (0x20U << FMC_PATT_ATTWAIT3_Pos) 8737 #define FMC_PATT_ATTWAIT3_6 (0x40U << FMC_PATT_ATTWAIT3_Pos) 8738 #define FMC_PATT_ATTWAIT3_7 (0x80U << FMC_PATT_ATTWAIT3_Pos) 8739 #define FMC_PATT_ATTHOLD3_Pos (16U) 8740 #define FMC_PATT_ATTHOLD3_Msk (0xFFU << FMC_PATT_ATTHOLD3_Pos) 8741 #define FMC_PATT_ATTHOLD3 FMC_PATT_ATTHOLD3_Msk 8742 #define FMC_PATT_ATTHOLD3_0 (0x01U << FMC_PATT_ATTHOLD3_Pos) 8743 #define FMC_PATT_ATTHOLD3_1 (0x02U << FMC_PATT_ATTHOLD3_Pos) 8744 #define FMC_PATT_ATTHOLD3_2 (0x04U << FMC_PATT_ATTHOLD3_Pos) 8745 #define FMC_PATT_ATTHOLD3_3 (0x08U << FMC_PATT_ATTHOLD3_Pos) 8746 #define FMC_PATT_ATTHOLD3_4 (0x10U << FMC_PATT_ATTHOLD3_Pos) 8747 #define FMC_PATT_ATTHOLD3_5 (0x20U << FMC_PATT_ATTHOLD3_Pos) 8748 #define FMC_PATT_ATTHOLD3_6 (0x40U << FMC_PATT_ATTHOLD3_Pos) 8749 #define FMC_PATT_ATTHOLD3_7 (0x80U << FMC_PATT_ATTHOLD3_Pos) 8750 #define FMC_PATT_ATTHIZ3_Pos (24U) 8751 #define FMC_PATT_ATTHIZ3_Msk (0xFFU << FMC_PATT_ATTHIZ3_Pos) 8752 #define FMC_PATT_ATTHIZ3 FMC_PATT_ATTHIZ3_Msk 8753 #define FMC_PATT_ATTHIZ3_0 (0x01U << FMC_PATT_ATTHIZ3_Pos) 8754 #define FMC_PATT_ATTHIZ3_1 (0x02U << FMC_PATT_ATTHIZ3_Pos) 8755 #define FMC_PATT_ATTHIZ3_2 (0x04U << FMC_PATT_ATTHIZ3_Pos) 8756 #define FMC_PATT_ATTHIZ3_3 (0x08U << FMC_PATT_ATTHIZ3_Pos) 8757 #define FMC_PATT_ATTHIZ3_4 (0x10U << FMC_PATT_ATTHIZ3_Pos) 8758 #define FMC_PATT_ATTHIZ3_5 (0x20U << FMC_PATT_ATTHIZ3_Pos) 8759 #define FMC_PATT_ATTHIZ3_6 (0x40U << FMC_PATT_ATTHIZ3_Pos) 8760 #define FMC_PATT_ATTHIZ3_7 (0x80U << FMC_PATT_ATTHIZ3_Pos) 8763 #define FMC_ECCR_ECC3_Pos (0U) 8764 #define FMC_ECCR_ECC3_Msk (0xFFFFFFFFU << FMC_ECCR_ECC3_Pos) 8765 #define FMC_ECCR_ECC3 FMC_ECCR_ECC3_Msk 8768 #define FMC_SDCR1_NC_Pos (0U) 8769 #define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) 8770 #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk 8771 #define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) 8772 #define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) 8773 #define FMC_SDCR1_NR_Pos (2U) 8774 #define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) 8775 #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk 8776 #define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) 8777 #define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) 8778 #define FMC_SDCR1_MWID_Pos (4U) 8779 #define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) 8780 #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk 8781 #define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) 8782 #define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) 8783 #define FMC_SDCR1_NB_Pos (6U) 8784 #define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) 8785 #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk 8786 #define FMC_SDCR1_CAS_Pos (7U) 8787 #define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) 8788 #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk 8789 #define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) 8790 #define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) 8791 #define FMC_SDCR1_WP_Pos (9U) 8792 #define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) 8793 #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk 8794 #define FMC_SDCR1_SDCLK_Pos (10U) 8795 #define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) 8796 #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk 8797 #define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) 8798 #define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) 8799 #define FMC_SDCR1_RBURST_Pos (12U) 8800 #define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) 8801 #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk 8802 #define FMC_SDCR1_RPIPE_Pos (13U) 8803 #define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) 8804 #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk 8805 #define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) 8806 #define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) 8809 #define FMC_SDCR2_NC_Pos (0U) 8810 #define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) 8811 #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk 8812 #define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) 8813 #define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) 8814 #define FMC_SDCR2_NR_Pos (2U) 8815 #define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) 8816 #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk 8817 #define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) 8818 #define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) 8819 #define FMC_SDCR2_MWID_Pos (4U) 8820 #define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) 8821 #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk 8822 #define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) 8823 #define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) 8824 #define FMC_SDCR2_NB_Pos (6U) 8825 #define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) 8826 #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk 8827 #define FMC_SDCR2_CAS_Pos (7U) 8828 #define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) 8829 #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk 8830 #define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) 8831 #define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) 8832 #define FMC_SDCR2_WP_Pos (9U) 8833 #define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) 8834 #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk 8835 #define FMC_SDCR2_SDCLK_Pos (10U) 8836 #define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) 8837 #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk 8838 #define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) 8839 #define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) 8840 #define FMC_SDCR2_RBURST_Pos (12U) 8841 #define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) 8842 #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk 8843 #define FMC_SDCR2_RPIPE_Pos (13U) 8844 #define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) 8845 #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk 8846 #define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) 8847 #define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) 8850 #define FMC_SDTR1_TMRD_Pos (0U) 8851 #define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) 8852 #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk 8853 #define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) 8854 #define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) 8855 #define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) 8856 #define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) 8857 #define FMC_SDTR1_TXSR_Pos (4U) 8858 #define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) 8859 #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk 8860 #define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) 8861 #define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) 8862 #define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) 8863 #define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) 8864 #define FMC_SDTR1_TRAS_Pos (8U) 8865 #define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) 8866 #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk 8867 #define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) 8868 #define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) 8869 #define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) 8870 #define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) 8871 #define FMC_SDTR1_TRC_Pos (12U) 8872 #define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) 8873 #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk 8874 #define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) 8875 #define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) 8876 #define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) 8877 #define FMC_SDTR1_TWR_Pos (16U) 8878 #define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) 8879 #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk 8880 #define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) 8881 #define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) 8882 #define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) 8883 #define FMC_SDTR1_TRP_Pos (20U) 8884 #define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) 8885 #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk 8886 #define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) 8887 #define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) 8888 #define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) 8889 #define FMC_SDTR1_TRCD_Pos (24U) 8890 #define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) 8891 #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk 8892 #define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) 8893 #define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) 8894 #define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) 8897 #define FMC_SDTR2_TMRD_Pos (0U) 8898 #define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) 8899 #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk 8900 #define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) 8901 #define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) 8902 #define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) 8903 #define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) 8904 #define FMC_SDTR2_TXSR_Pos (4U) 8905 #define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) 8906 #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk 8907 #define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) 8908 #define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) 8909 #define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) 8910 #define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) 8911 #define FMC_SDTR2_TRAS_Pos (8U) 8912 #define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) 8913 #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk 8914 #define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) 8915 #define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) 8916 #define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) 8917 #define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) 8918 #define FMC_SDTR2_TRC_Pos (12U) 8919 #define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) 8920 #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk 8921 #define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) 8922 #define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) 8923 #define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) 8924 #define FMC_SDTR2_TWR_Pos (16U) 8925 #define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) 8926 #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk 8927 #define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) 8928 #define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) 8929 #define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) 8930 #define FMC_SDTR2_TRP_Pos (20U) 8931 #define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) 8932 #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk 8933 #define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) 8934 #define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) 8935 #define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) 8936 #define FMC_SDTR2_TRCD_Pos (24U) 8937 #define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) 8938 #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk 8939 #define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) 8940 #define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) 8941 #define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) 8944 #define FMC_SDCMR_MODE_Pos (0U) 8945 #define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) 8946 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk 8947 #define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) 8948 #define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) 8949 #define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) 8950 #define FMC_SDCMR_CTB2_Pos (3U) 8951 #define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) 8952 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk 8953 #define FMC_SDCMR_CTB1_Pos (4U) 8954 #define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) 8955 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk 8956 #define FMC_SDCMR_NRFS_Pos (5U) 8957 #define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) 8958 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk 8959 #define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) 8960 #define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) 8961 #define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) 8962 #define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) 8963 #define FMC_SDCMR_MRD_Pos (9U) 8964 #define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) 8965 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk 8968 #define FMC_SDRTR_CRE_Pos (0U) 8969 #define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) 8970 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk 8971 #define FMC_SDRTR_COUNT_Pos (1U) 8972 #define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) 8973 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk 8974 #define FMC_SDRTR_REIE_Pos (14U) 8975 #define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) 8976 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk 8979 #define FMC_SDSR_RE_Pos (0U) 8980 #define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) 8981 #define FMC_SDSR_RE FMC_SDSR_RE_Msk 8982 #define FMC_SDSR_MODES1_Pos (1U) 8983 #define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) 8984 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk 8985 #define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) 8986 #define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) 8987 #define FMC_SDSR_MODES2_Pos (3U) 8988 #define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) 8989 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk 8990 #define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) 8991 #define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) 8992 #define FMC_SDSR_BUSY_Pos (5U) 8993 #define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) 8994 #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk 9002 #define GPIO_MODER_MODER0_Pos (0U) 9003 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) 9004 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk 9005 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) 9006 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) 9007 #define GPIO_MODER_MODER1_Pos (2U) 9008 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) 9009 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk 9010 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) 9011 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) 9012 #define GPIO_MODER_MODER2_Pos (4U) 9013 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) 9014 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk 9015 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) 9016 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) 9017 #define GPIO_MODER_MODER3_Pos (6U) 9018 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) 9019 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk 9020 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) 9021 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) 9022 #define GPIO_MODER_MODER4_Pos (8U) 9023 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) 9024 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk 9025 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) 9026 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) 9027 #define GPIO_MODER_MODER5_Pos (10U) 9028 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) 9029 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk 9030 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) 9031 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) 9032 #define GPIO_MODER_MODER6_Pos (12U) 9033 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) 9034 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk 9035 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) 9036 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) 9037 #define GPIO_MODER_MODER7_Pos (14U) 9038 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) 9039 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk 9040 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) 9041 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) 9042 #define GPIO_MODER_MODER8_Pos (16U) 9043 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) 9044 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk 9045 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) 9046 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) 9047 #define GPIO_MODER_MODER9_Pos (18U) 9048 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) 9049 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk 9050 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) 9051 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) 9052 #define GPIO_MODER_MODER10_Pos (20U) 9053 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) 9054 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk 9055 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) 9056 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) 9057 #define GPIO_MODER_MODER11_Pos (22U) 9058 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) 9059 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk 9060 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) 9061 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) 9062 #define GPIO_MODER_MODER12_Pos (24U) 9063 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) 9064 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk 9065 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) 9066 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) 9067 #define GPIO_MODER_MODER13_Pos (26U) 9068 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) 9069 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk 9070 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) 9071 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) 9072 #define GPIO_MODER_MODER14_Pos (28U) 9073 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) 9074 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk 9075 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) 9076 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) 9077 #define GPIO_MODER_MODER15_Pos (30U) 9078 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) 9079 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk 9080 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) 9081 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) 9084 #define GPIO_OTYPER_OT_0 0x00000001U 9085 #define GPIO_OTYPER_OT_1 0x00000002U 9086 #define GPIO_OTYPER_OT_2 0x00000004U 9087 #define GPIO_OTYPER_OT_3 0x00000008U 9088 #define GPIO_OTYPER_OT_4 0x00000010U 9089 #define GPIO_OTYPER_OT_5 0x00000020U 9090 #define GPIO_OTYPER_OT_6 0x00000040U 9091 #define GPIO_OTYPER_OT_7 0x00000080U 9092 #define GPIO_OTYPER_OT_8 0x00000100U 9093 #define GPIO_OTYPER_OT_9 0x00000200U 9094 #define GPIO_OTYPER_OT_10 0x00000400U 9095 #define GPIO_OTYPER_OT_11 0x00000800U 9096 #define GPIO_OTYPER_OT_12 0x00001000U 9097 #define GPIO_OTYPER_OT_13 0x00002000U 9098 #define GPIO_OTYPER_OT_14 0x00004000U 9099 #define GPIO_OTYPER_OT_15 0x00008000U 9102 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U) 9103 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) 9104 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk 9105 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) 9106 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) 9107 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U) 9108 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) 9109 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk 9110 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) 9111 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) 9112 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U) 9113 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) 9114 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk 9115 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) 9116 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) 9117 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U) 9118 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) 9119 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk 9120 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) 9121 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) 9122 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U) 9123 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) 9124 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk 9125 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) 9126 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) 9127 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U) 9128 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) 9129 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk 9130 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) 9131 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) 9132 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U) 9133 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) 9134 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk 9135 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) 9136 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) 9137 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U) 9138 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) 9139 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk 9140 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) 9141 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) 9142 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U) 9143 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) 9144 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk 9145 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) 9146 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) 9147 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U) 9148 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) 9149 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk 9150 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) 9151 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) 9152 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U) 9153 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) 9154 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk 9155 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) 9156 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) 9157 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U) 9158 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) 9159 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk 9160 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) 9161 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) 9162 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U) 9163 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) 9164 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk 9165 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) 9166 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) 9167 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U) 9168 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) 9169 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk 9170 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) 9171 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) 9172 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U) 9173 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) 9174 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk 9175 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) 9176 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) 9177 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U) 9178 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) 9179 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk 9180 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) 9181 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) 9184 #define GPIO_PUPDR_PUPDR0_Pos (0U) 9185 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) 9186 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk 9187 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) 9188 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) 9189 #define GPIO_PUPDR_PUPDR1_Pos (2U) 9190 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) 9191 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk 9192 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) 9193 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) 9194 #define GPIO_PUPDR_PUPDR2_Pos (4U) 9195 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) 9196 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk 9197 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) 9198 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) 9199 #define GPIO_PUPDR_PUPDR3_Pos (6U) 9200 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) 9201 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk 9202 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) 9203 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) 9204 #define GPIO_PUPDR_PUPDR4_Pos (8U) 9205 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) 9206 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk 9207 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) 9208 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) 9209 #define GPIO_PUPDR_PUPDR5_Pos (10U) 9210 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) 9211 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk 9212 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) 9213 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) 9214 #define GPIO_PUPDR_PUPDR6_Pos (12U) 9215 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) 9216 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk 9217 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) 9218 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) 9219 #define GPIO_PUPDR_PUPDR7_Pos (14U) 9220 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) 9221 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk 9222 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) 9223 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) 9224 #define GPIO_PUPDR_PUPDR8_Pos (16U) 9225 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) 9226 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk 9227 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) 9228 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) 9229 #define GPIO_PUPDR_PUPDR9_Pos (18U) 9230 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) 9231 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk 9232 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) 9233 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) 9234 #define GPIO_PUPDR_PUPDR10_Pos (20U) 9235 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) 9236 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk 9237 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) 9238 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) 9239 #define GPIO_PUPDR_PUPDR11_Pos (22U) 9240 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) 9241 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk 9242 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) 9243 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) 9244 #define GPIO_PUPDR_PUPDR12_Pos (24U) 9245 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) 9246 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk 9247 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) 9248 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) 9249 #define GPIO_PUPDR_PUPDR13_Pos (26U) 9250 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) 9251 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk 9252 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) 9253 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) 9254 #define GPIO_PUPDR_PUPDR14_Pos (28U) 9255 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) 9256 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk 9257 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) 9258 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) 9259 #define GPIO_PUPDR_PUPDR15_Pos (30U) 9260 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) 9261 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk 9262 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) 9263 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) 9266 #define GPIO_IDR_IDR_0 0x00000001U 9267 #define GPIO_IDR_IDR_1 0x00000002U 9268 #define GPIO_IDR_IDR_2 0x00000004U 9269 #define GPIO_IDR_IDR_3 0x00000008U 9270 #define GPIO_IDR_IDR_4 0x00000010U 9271 #define GPIO_IDR_IDR_5 0x00000020U 9272 #define GPIO_IDR_IDR_6 0x00000040U 9273 #define GPIO_IDR_IDR_7 0x00000080U 9274 #define GPIO_IDR_IDR_8 0x00000100U 9275 #define GPIO_IDR_IDR_9 0x00000200U 9276 #define GPIO_IDR_IDR_10 0x00000400U 9277 #define GPIO_IDR_IDR_11 0x00000800U 9278 #define GPIO_IDR_IDR_12 0x00001000U 9279 #define GPIO_IDR_IDR_13 0x00002000U 9280 #define GPIO_IDR_IDR_14 0x00004000U 9281 #define GPIO_IDR_IDR_15 0x00008000U 9284 #define GPIO_ODR_ODR_0 0x00000001U 9285 #define GPIO_ODR_ODR_1 0x00000002U 9286 #define GPIO_ODR_ODR_2 0x00000004U 9287 #define GPIO_ODR_ODR_3 0x00000008U 9288 #define GPIO_ODR_ODR_4 0x00000010U 9289 #define GPIO_ODR_ODR_5 0x00000020U 9290 #define GPIO_ODR_ODR_6 0x00000040U 9291 #define GPIO_ODR_ODR_7 0x00000080U 9292 #define GPIO_ODR_ODR_8 0x00000100U 9293 #define GPIO_ODR_ODR_9 0x00000200U 9294 #define GPIO_ODR_ODR_10 0x00000400U 9295 #define GPIO_ODR_ODR_11 0x00000800U 9296 #define GPIO_ODR_ODR_12 0x00001000U 9297 #define GPIO_ODR_ODR_13 0x00002000U 9298 #define GPIO_ODR_ODR_14 0x00004000U 9299 #define GPIO_ODR_ODR_15 0x00008000U 9302 #define GPIO_BSRR_BS_0 0x00000001U 9303 #define GPIO_BSRR_BS_1 0x00000002U 9304 #define GPIO_BSRR_BS_2 0x00000004U 9305 #define GPIO_BSRR_BS_3 0x00000008U 9306 #define GPIO_BSRR_BS_4 0x00000010U 9307 #define GPIO_BSRR_BS_5 0x00000020U 9308 #define GPIO_BSRR_BS_6 0x00000040U 9309 #define GPIO_BSRR_BS_7 0x00000080U 9310 #define GPIO_BSRR_BS_8 0x00000100U 9311 #define GPIO_BSRR_BS_9 0x00000200U 9312 #define GPIO_BSRR_BS_10 0x00000400U 9313 #define GPIO_BSRR_BS_11 0x00000800U 9314 #define GPIO_BSRR_BS_12 0x00001000U 9315 #define GPIO_BSRR_BS_13 0x00002000U 9316 #define GPIO_BSRR_BS_14 0x00004000U 9317 #define GPIO_BSRR_BS_15 0x00008000U 9318 #define GPIO_BSRR_BR_0 0x00010000U 9319 #define GPIO_BSRR_BR_1 0x00020000U 9320 #define GPIO_BSRR_BR_2 0x00040000U 9321 #define GPIO_BSRR_BR_3 0x00080000U 9322 #define GPIO_BSRR_BR_4 0x00100000U 9323 #define GPIO_BSRR_BR_5 0x00200000U 9324 #define GPIO_BSRR_BR_6 0x00400000U 9325 #define GPIO_BSRR_BR_7 0x00800000U 9326 #define GPIO_BSRR_BR_8 0x01000000U 9327 #define GPIO_BSRR_BR_9 0x02000000U 9328 #define GPIO_BSRR_BR_10 0x04000000U 9329 #define GPIO_BSRR_BR_11 0x08000000U 9330 #define GPIO_BSRR_BR_12 0x10000000U 9331 #define GPIO_BSRR_BR_13 0x20000000U 9332 #define GPIO_BSRR_BR_14 0x40000000U 9333 #define GPIO_BSRR_BR_15 0x80000000U 9336 #define GPIO_LCKR_LCK0_Pos (0U) 9337 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) 9338 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 9339 #define GPIO_LCKR_LCK1_Pos (1U) 9340 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) 9341 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 9342 #define GPIO_LCKR_LCK2_Pos (2U) 9343 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) 9344 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 9345 #define GPIO_LCKR_LCK3_Pos (3U) 9346 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) 9347 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 9348 #define GPIO_LCKR_LCK4_Pos (4U) 9349 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) 9350 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 9351 #define GPIO_LCKR_LCK5_Pos (5U) 9352 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) 9353 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 9354 #define GPIO_LCKR_LCK6_Pos (6U) 9355 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) 9356 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 9357 #define GPIO_LCKR_LCK7_Pos (7U) 9358 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) 9359 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 9360 #define GPIO_LCKR_LCK8_Pos (8U) 9361 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) 9362 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 9363 #define GPIO_LCKR_LCK9_Pos (9U) 9364 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) 9365 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 9366 #define GPIO_LCKR_LCK10_Pos (10U) 9367 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) 9368 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 9369 #define GPIO_LCKR_LCK11_Pos (11U) 9370 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) 9371 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 9372 #define GPIO_LCKR_LCK12_Pos (12U) 9373 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) 9374 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 9375 #define GPIO_LCKR_LCK13_Pos (13U) 9376 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) 9377 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 9378 #define GPIO_LCKR_LCK14_Pos (14U) 9379 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) 9380 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 9381 #define GPIO_LCKR_LCK15_Pos (15U) 9382 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) 9383 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 9384 #define GPIO_LCKR_LCKK_Pos (16U) 9385 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) 9386 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 9389 #define GPIO_AFRL_AFRL0_Pos (0U) 9390 #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) 9391 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk 9392 #define GPIO_AFRL_AFRL0_0 (0x1U << GPIO_AFRL_AFRL0_Pos) 9393 #define GPIO_AFRL_AFRL0_1 (0x2U << GPIO_AFRL_AFRL0_Pos) 9394 #define GPIO_AFRL_AFRL0_2 (0x4U << GPIO_AFRL_AFRL0_Pos) 9395 #define GPIO_AFRL_AFRL0_3 (0x8U << GPIO_AFRL_AFRL0_Pos) 9396 #define GPIO_AFRL_AFRL1_Pos (4U) 9397 #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) 9398 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk 9399 #define GPIO_AFRL_AFRL1_0 (0x1U << GPIO_AFRL_AFRL1_Pos) 9400 #define GPIO_AFRL_AFRL1_1 (0x2U << GPIO_AFRL_AFRL1_Pos) 9401 #define GPIO_AFRL_AFRL1_2 (0x4U << GPIO_AFRL_AFRL1_Pos) 9402 #define GPIO_AFRL_AFRL1_3 (0x8U << GPIO_AFRL_AFRL1_Pos) 9403 #define GPIO_AFRL_AFRL2_Pos (8U) 9404 #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) 9405 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk 9406 #define GPIO_AFRL_AFRL2_0 (0x1U << GPIO_AFRL_AFRL2_Pos) 9407 #define GPIO_AFRL_AFRL2_1 (0x2U << GPIO_AFRL_AFRL2_Pos) 9408 #define GPIO_AFRL_AFRL2_2 (0x4U << GPIO_AFRL_AFRL2_Pos) 9409 #define GPIO_AFRL_AFRL2_3 (0x8U << GPIO_AFRL_AFRL2_Pos) 9410 #define GPIO_AFRL_AFRL3_Pos (12U) 9411 #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) 9412 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk 9413 #define GPIO_AFRL_AFRL3_0 (0x1U << GPIO_AFRL_AFRL3_Pos) 9414 #define GPIO_AFRL_AFRL3_1 (0x2U << GPIO_AFRL_AFRL3_Pos) 9415 #define GPIO_AFRL_AFRL3_2 (0x4U << GPIO_AFRL_AFRL3_Pos) 9416 #define GPIO_AFRL_AFRL3_3 (0x8U << GPIO_AFRL_AFRL3_Pos) 9417 #define GPIO_AFRL_AFRL4_Pos (16U) 9418 #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) 9419 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk 9420 #define GPIO_AFRL_AFRL4_0 (0x1U << GPIO_AFRL_AFRL4_Pos) 9421 #define GPIO_AFRL_AFRL4_1 (0x2U << GPIO_AFRL_AFRL4_Pos) 9422 #define GPIO_AFRL_AFRL4_2 (0x4U << GPIO_AFRL_AFRL4_Pos) 9423 #define GPIO_AFRL_AFRL4_3 (0x8U << GPIO_AFRL_AFRL4_Pos) 9424 #define GPIO_AFRL_AFRL5_Pos (20U) 9425 #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) 9426 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk 9427 #define GPIO_AFRL_AFRL5_0 (0x1U << GPIO_AFRL_AFRL5_Pos) 9428 #define GPIO_AFRL_AFRL5_1 (0x2U << GPIO_AFRL_AFRL5_Pos) 9429 #define GPIO_AFRL_AFRL5_2 (0x4U << GPIO_AFRL_AFRL5_Pos) 9430 #define GPIO_AFRL_AFRL5_3 (0x8U << GPIO_AFRL_AFRL5_Pos) 9431 #define GPIO_AFRL_AFRL6_Pos (24U) 9432 #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) 9433 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk 9434 #define GPIO_AFRL_AFRL6_0 (0x1U << GPIO_AFRL_AFRL6_Pos) 9435 #define GPIO_AFRL_AFRL6_1 (0x2U << GPIO_AFRL_AFRL6_Pos) 9436 #define GPIO_AFRL_AFRL6_2 (0x4U << GPIO_AFRL_AFRL6_Pos) 9437 #define GPIO_AFRL_AFRL6_3 (0x8U << GPIO_AFRL_AFRL6_Pos) 9438 #define GPIO_AFRL_AFRL7_Pos (28U) 9439 #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) 9440 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk 9441 #define GPIO_AFRL_AFRL7_0 (0x1U << GPIO_AFRL_AFRL7_Pos) 9442 #define GPIO_AFRL_AFRL7_1 (0x2U << GPIO_AFRL_AFRL7_Pos) 9443 #define GPIO_AFRL_AFRL7_2 (0x4U << GPIO_AFRL_AFRL7_Pos) 9444 #define GPIO_AFRL_AFRL7_3 (0x8U << GPIO_AFRL_AFRL7_Pos) 9447 #define GPIO_AFRH_AFRH0_Pos (0U) 9448 #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) 9449 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk 9450 #define GPIO_AFRH_AFRH0_0 (0x1U << GPIO_AFRH_AFRH0_Pos) 9451 #define GPIO_AFRH_AFRH0_1 (0x2U << GPIO_AFRH_AFRH0_Pos) 9452 #define GPIO_AFRH_AFRH0_2 (0x4U << GPIO_AFRH_AFRH0_Pos) 9453 #define GPIO_AFRH_AFRH0_3 (0x8U << GPIO_AFRH_AFRH0_Pos) 9454 #define GPIO_AFRH_AFRH1_Pos (4U) 9455 #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) 9456 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk 9457 #define GPIO_AFRH_AFRH1_0 (0x1U << GPIO_AFRH_AFRH1_Pos) 9458 #define GPIO_AFRH_AFRH1_1 (0x2U << GPIO_AFRH_AFRH1_Pos) 9459 #define GPIO_AFRH_AFRH1_2 (0x4U << GPIO_AFRH_AFRH1_Pos) 9460 #define GPIO_AFRH_AFRH1_3 (0x8U << GPIO_AFRH_AFRH1_Pos) 9461 #define GPIO_AFRH_AFRH2_Pos (8U) 9462 #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) 9463 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk 9464 #define GPIO_AFRH_AFRH2_0 (0x1U << GPIO_AFRH_AFRH2_Pos) 9465 #define GPIO_AFRH_AFRH2_1 (0x2U << GPIO_AFRH_AFRH2_Pos) 9466 #define GPIO_AFRH_AFRH2_2 (0x4U << GPIO_AFRH_AFRH2_Pos) 9467 #define GPIO_AFRH_AFRH2_3 (0x8U << GPIO_AFRH_AFRH2_Pos) 9468 #define GPIO_AFRH_AFRH3_Pos (12U) 9469 #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) 9470 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk 9471 #define GPIO_AFRH_AFRH3_0 (0x1U << GPIO_AFRH_AFRH3_Pos) 9472 #define GPIO_AFRH_AFRH3_1 (0x2U << GPIO_AFRH_AFRH3_Pos) 9473 #define GPIO_AFRH_AFRH3_2 (0x4U << GPIO_AFRH_AFRH3_Pos) 9474 #define GPIO_AFRH_AFRH3_3 (0x8U << GPIO_AFRH_AFRH3_Pos) 9475 #define GPIO_AFRH_AFRH4_Pos (16U) 9476 #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) 9477 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk 9478 #define GPIO_AFRH_AFRH4_0 (0x1U << GPIO_AFRH_AFRH4_Pos) 9479 #define GPIO_AFRH_AFRH4_1 (0x2U << GPIO_AFRH_AFRH4_Pos) 9480 #define GPIO_AFRH_AFRH4_2 (0x4U << GPIO_AFRH_AFRH4_Pos) 9481 #define GPIO_AFRH_AFRH4_3 (0x8U << GPIO_AFRH_AFRH4_Pos) 9482 #define GPIO_AFRH_AFRH5_Pos (20U) 9483 #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) 9484 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk 9485 #define GPIO_AFRH_AFRH5_0 (0x1U << GPIO_AFRH_AFRH5_Pos) 9486 #define GPIO_AFRH_AFRH5_1 (0x2U << GPIO_AFRH_AFRH5_Pos) 9487 #define GPIO_AFRH_AFRH5_2 (0x4U << GPIO_AFRH_AFRH5_Pos) 9488 #define GPIO_AFRH_AFRH5_3 (0x8U << GPIO_AFRH_AFRH5_Pos) 9489 #define GPIO_AFRH_AFRH6_Pos (24U) 9490 #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) 9491 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk 9492 #define GPIO_AFRH_AFRH6_0 (0x1U << GPIO_AFRH_AFRH6_Pos) 9493 #define GPIO_AFRH_AFRH6_1 (0x2U << GPIO_AFRH_AFRH6_Pos) 9494 #define GPIO_AFRH_AFRH6_2 (0x4U << GPIO_AFRH_AFRH6_Pos) 9495 #define GPIO_AFRH_AFRH6_3 (0x8U << GPIO_AFRH_AFRH6_Pos) 9496 #define GPIO_AFRH_AFRH7_Pos (28U) 9497 #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) 9498 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk 9499 #define GPIO_AFRH_AFRH7_0 (0x1U << GPIO_AFRH_AFRH7_Pos) 9500 #define GPIO_AFRH_AFRH7_1 (0x2U << GPIO_AFRH_AFRH7_Pos) 9501 #define GPIO_AFRH_AFRH7_2 (0x4U << GPIO_AFRH_AFRH7_Pos) 9502 #define GPIO_AFRH_AFRH7_3 (0x8U << GPIO_AFRH_AFRH7_Pos) 9511 #define I2C_CR1_PE_Pos (0U) 9512 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) 9513 #define I2C_CR1_PE I2C_CR1_PE_Msk 9514 #define I2C_CR1_TXIE_Pos (1U) 9515 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) 9516 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk 9517 #define I2C_CR1_RXIE_Pos (2U) 9518 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) 9519 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk 9520 #define I2C_CR1_ADDRIE_Pos (3U) 9521 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) 9522 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk 9523 #define I2C_CR1_NACKIE_Pos (4U) 9524 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) 9525 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk 9526 #define I2C_CR1_STOPIE_Pos (5U) 9527 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) 9528 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk 9529 #define I2C_CR1_TCIE_Pos (6U) 9530 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) 9531 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk 9532 #define I2C_CR1_ERRIE_Pos (7U) 9533 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) 9534 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk 9535 #define I2C_CR1_DNF_Pos (8U) 9536 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) 9537 #define I2C_CR1_DNF I2C_CR1_DNF_Msk 9538 #define I2C_CR1_ANFOFF_Pos (12U) 9539 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) 9540 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk 9541 #define I2C_CR1_TXDMAEN_Pos (14U) 9542 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) 9543 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk 9544 #define I2C_CR1_RXDMAEN_Pos (15U) 9545 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) 9546 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk 9547 #define I2C_CR1_SBC_Pos (16U) 9548 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) 9549 #define I2C_CR1_SBC I2C_CR1_SBC_Msk 9550 #define I2C_CR1_NOSTRETCH_Pos (17U) 9551 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) 9552 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk 9553 #define I2C_CR1_GCEN_Pos (19U) 9554 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) 9555 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk 9556 #define I2C_CR1_SMBHEN_Pos (20U) 9557 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) 9558 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk 9559 #define I2C_CR1_SMBDEN_Pos (21U) 9560 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) 9561 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk 9562 #define I2C_CR1_ALERTEN_Pos (22U) 9563 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) 9564 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk 9565 #define I2C_CR1_PECEN_Pos (23U) 9566 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) 9567 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk 9571 #define I2C_CR2_SADD_Pos (0U) 9572 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) 9573 #define I2C_CR2_SADD I2C_CR2_SADD_Msk 9574 #define I2C_CR2_RD_WRN_Pos (10U) 9575 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) 9576 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk 9577 #define I2C_CR2_ADD10_Pos (11U) 9578 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) 9579 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk 9580 #define I2C_CR2_HEAD10R_Pos (12U) 9581 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) 9582 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk 9583 #define I2C_CR2_START_Pos (13U) 9584 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) 9585 #define I2C_CR2_START I2C_CR2_START_Msk 9586 #define I2C_CR2_STOP_Pos (14U) 9587 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) 9588 #define I2C_CR2_STOP I2C_CR2_STOP_Msk 9589 #define I2C_CR2_NACK_Pos (15U) 9590 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) 9591 #define I2C_CR2_NACK I2C_CR2_NACK_Msk 9592 #define I2C_CR2_NBYTES_Pos (16U) 9593 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) 9594 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk 9595 #define I2C_CR2_RELOAD_Pos (24U) 9596 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) 9597 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk 9598 #define I2C_CR2_AUTOEND_Pos (25U) 9599 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) 9600 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk 9601 #define I2C_CR2_PECBYTE_Pos (26U) 9602 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) 9603 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk 9606 #define I2C_OAR1_OA1_Pos (0U) 9607 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) 9608 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk 9609 #define I2C_OAR1_OA1MODE_Pos (10U) 9610 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) 9611 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk 9612 #define I2C_OAR1_OA1EN_Pos (15U) 9613 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) 9614 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk 9617 #define I2C_OAR2_OA2_Pos (1U) 9618 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) 9619 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk 9620 #define I2C_OAR2_OA2MSK_Pos (8U) 9621 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) 9622 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk 9623 #define I2C_OAR2_OA2NOMASK 0x00000000U 9624 #define I2C_OAR2_OA2MASK01_Pos (8U) 9625 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) 9626 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk 9627 #define I2C_OAR2_OA2MASK02_Pos (9U) 9628 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) 9629 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk 9630 #define I2C_OAR2_OA2MASK03_Pos (8U) 9631 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) 9632 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk 9633 #define I2C_OAR2_OA2MASK04_Pos (10U) 9634 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) 9635 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk 9636 #define I2C_OAR2_OA2MASK05_Pos (8U) 9637 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) 9638 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk 9639 #define I2C_OAR2_OA2MASK06_Pos (9U) 9640 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) 9641 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk 9642 #define I2C_OAR2_OA2MASK07_Pos (8U) 9643 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) 9644 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk 9645 #define I2C_OAR2_OA2EN_Pos (15U) 9646 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) 9647 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk 9650 #define I2C_TIMINGR_SCLL_Pos (0U) 9651 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) 9652 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk 9653 #define I2C_TIMINGR_SCLH_Pos (8U) 9654 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) 9655 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk 9656 #define I2C_TIMINGR_SDADEL_Pos (16U) 9657 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) 9658 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk 9659 #define I2C_TIMINGR_SCLDEL_Pos (20U) 9660 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) 9661 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk 9662 #define I2C_TIMINGR_PRESC_Pos (28U) 9663 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) 9664 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk 9667 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) 9668 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) 9669 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk 9670 #define I2C_TIMEOUTR_TIDLE_Pos (12U) 9671 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) 9672 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk 9673 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) 9674 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) 9675 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk 9676 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) 9677 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) 9678 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk 9679 #define I2C_TIMEOUTR_TEXTEN_Pos (31U) 9680 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) 9681 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk 9684 #define I2C_ISR_TXE_Pos (0U) 9685 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) 9686 #define I2C_ISR_TXE I2C_ISR_TXE_Msk 9687 #define I2C_ISR_TXIS_Pos (1U) 9688 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) 9689 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk 9690 #define I2C_ISR_RXNE_Pos (2U) 9691 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) 9692 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk 9693 #define I2C_ISR_ADDR_Pos (3U) 9694 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) 9695 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk 9696 #define I2C_ISR_NACKF_Pos (4U) 9697 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) 9698 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk 9699 #define I2C_ISR_STOPF_Pos (5U) 9700 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) 9701 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk 9702 #define I2C_ISR_TC_Pos (6U) 9703 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) 9704 #define I2C_ISR_TC I2C_ISR_TC_Msk 9705 #define I2C_ISR_TCR_Pos (7U) 9706 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) 9707 #define I2C_ISR_TCR I2C_ISR_TCR_Msk 9708 #define I2C_ISR_BERR_Pos (8U) 9709 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) 9710 #define I2C_ISR_BERR I2C_ISR_BERR_Msk 9711 #define I2C_ISR_ARLO_Pos (9U) 9712 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) 9713 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk 9714 #define I2C_ISR_OVR_Pos (10U) 9715 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) 9716 #define I2C_ISR_OVR I2C_ISR_OVR_Msk 9717 #define I2C_ISR_PECERR_Pos (11U) 9718 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) 9719 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk 9720 #define I2C_ISR_TIMEOUT_Pos (12U) 9721 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) 9722 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk 9723 #define I2C_ISR_ALERT_Pos (13U) 9724 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) 9725 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk 9726 #define I2C_ISR_BUSY_Pos (15U) 9727 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) 9728 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk 9729 #define I2C_ISR_DIR_Pos (16U) 9730 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) 9731 #define I2C_ISR_DIR I2C_ISR_DIR_Msk 9732 #define I2C_ISR_ADDCODE_Pos (17U) 9733 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) 9734 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk 9737 #define I2C_ICR_ADDRCF_Pos (3U) 9738 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) 9739 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk 9740 #define I2C_ICR_NACKCF_Pos (4U) 9741 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) 9742 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk 9743 #define I2C_ICR_STOPCF_Pos (5U) 9744 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) 9745 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk 9746 #define I2C_ICR_BERRCF_Pos (8U) 9747 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) 9748 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk 9749 #define I2C_ICR_ARLOCF_Pos (9U) 9750 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) 9751 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk 9752 #define I2C_ICR_OVRCF_Pos (10U) 9753 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) 9754 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk 9755 #define I2C_ICR_PECCF_Pos (11U) 9756 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) 9757 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk 9758 #define I2C_ICR_TIMOUTCF_Pos (12U) 9759 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) 9760 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk 9761 #define I2C_ICR_ALERTCF_Pos (13U) 9762 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) 9763 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk 9766 #define I2C_PECR_PEC_Pos (0U) 9767 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) 9768 #define I2C_PECR_PEC I2C_PECR_PEC_Msk 9771 #define I2C_RXDR_RXDATA_Pos (0U) 9772 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) 9773 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk 9776 #define I2C_TXDR_TXDATA_Pos (0U) 9777 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) 9778 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk 9787 #define IWDG_KR_KEY_Pos (0U) 9788 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) 9789 #define IWDG_KR_KEY IWDG_KR_KEY_Msk 9792 #define IWDG_PR_PR_Pos (0U) 9793 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) 9794 #define IWDG_PR_PR IWDG_PR_PR_Msk 9795 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) 9796 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) 9797 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) 9800 #define IWDG_RLR_RL_Pos (0U) 9801 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) 9802 #define IWDG_RLR_RL IWDG_RLR_RL_Msk 9805 #define IWDG_SR_PVU_Pos (0U) 9806 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) 9807 #define IWDG_SR_PVU IWDG_SR_PVU_Msk 9808 #define IWDG_SR_RVU_Pos (1U) 9809 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) 9810 #define IWDG_SR_RVU IWDG_SR_RVU_Msk 9811 #define IWDG_SR_WVU_Pos (2U) 9812 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) 9813 #define IWDG_SR_WVU IWDG_SR_WVU_Msk 9816 #define IWDG_WINR_WIN_Pos (0U) 9817 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) 9818 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk 9828 #define LTDC_SSCR_VSH_Pos (0U) 9829 #define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) 9830 #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk 9831 #define LTDC_SSCR_HSW_Pos (16U) 9832 #define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) 9833 #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk 9837 #define LTDC_BPCR_AVBP_Pos (0U) 9838 #define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) 9839 #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk 9840 #define LTDC_BPCR_AHBP_Pos (16U) 9841 #define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) 9842 #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk 9846 #define LTDC_AWCR_AAH_Pos (0U) 9847 #define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) 9848 #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk 9849 #define LTDC_AWCR_AAW_Pos (16U) 9850 #define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) 9851 #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk 9855 #define LTDC_TWCR_TOTALH_Pos (0U) 9856 #define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) 9857 #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk 9858 #define LTDC_TWCR_TOTALW_Pos (16U) 9859 #define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) 9860 #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk 9864 #define LTDC_GCR_LTDCEN_Pos (0U) 9865 #define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) 9866 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk 9867 #define LTDC_GCR_DBW_Pos (4U) 9868 #define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) 9869 #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk 9870 #define LTDC_GCR_DGW_Pos (8U) 9871 #define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) 9872 #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk 9873 #define LTDC_GCR_DRW_Pos (12U) 9874 #define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) 9875 #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk 9876 #define LTDC_GCR_DEN_Pos (16U) 9877 #define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) 9878 #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk 9879 #define LTDC_GCR_PCPOL_Pos (28U) 9880 #define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) 9881 #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk 9882 #define LTDC_GCR_DEPOL_Pos (29U) 9883 #define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) 9884 #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk 9885 #define LTDC_GCR_VSPOL_Pos (30U) 9886 #define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) 9887 #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk 9888 #define LTDC_GCR_HSPOL_Pos (31U) 9889 #define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) 9890 #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk 9895 #define LTDC_SRCR_IMR_Pos (0U) 9896 #define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) 9897 #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk 9898 #define LTDC_SRCR_VBR_Pos (1U) 9899 #define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) 9900 #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk 9904 #define LTDC_BCCR_BCBLUE_Pos (0U) 9905 #define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) 9906 #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk 9907 #define LTDC_BCCR_BCGREEN_Pos (8U) 9908 #define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) 9909 #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk 9910 #define LTDC_BCCR_BCRED_Pos (16U) 9911 #define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) 9912 #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk 9916 #define LTDC_IER_LIE_Pos (0U) 9917 #define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) 9918 #define LTDC_IER_LIE LTDC_IER_LIE_Msk 9919 #define LTDC_IER_FUIE_Pos (1U) 9920 #define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) 9921 #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk 9922 #define LTDC_IER_TERRIE_Pos (2U) 9923 #define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) 9924 #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk 9925 #define LTDC_IER_RRIE_Pos (3U) 9926 #define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) 9927 #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk 9931 #define LTDC_ISR_LIF_Pos (0U) 9932 #define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) 9933 #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk 9934 #define LTDC_ISR_FUIF_Pos (1U) 9935 #define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) 9936 #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk 9937 #define LTDC_ISR_TERRIF_Pos (2U) 9938 #define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) 9939 #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk 9940 #define LTDC_ISR_RRIF_Pos (3U) 9941 #define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) 9942 #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk 9946 #define LTDC_ICR_CLIF_Pos (0U) 9947 #define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) 9948 #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk 9949 #define LTDC_ICR_CFUIF_Pos (1U) 9950 #define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) 9951 #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk 9952 #define LTDC_ICR_CTERRIF_Pos (2U) 9953 #define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) 9954 #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk 9955 #define LTDC_ICR_CRRIF_Pos (3U) 9956 #define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) 9957 #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk 9961 #define LTDC_LIPCR_LIPOS_Pos (0U) 9962 #define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) 9963 #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk 9967 #define LTDC_CPSR_CYPOS_Pos (0U) 9968 #define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) 9969 #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk 9970 #define LTDC_CPSR_CXPOS_Pos (16U) 9971 #define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) 9972 #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk 9976 #define LTDC_CDSR_VDES_Pos (0U) 9977 #define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) 9978 #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk 9979 #define LTDC_CDSR_HDES_Pos (1U) 9980 #define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) 9981 #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk 9982 #define LTDC_CDSR_VSYNCS_Pos (2U) 9983 #define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) 9984 #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk 9985 #define LTDC_CDSR_HSYNCS_Pos (3U) 9986 #define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) 9987 #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk 9991 #define LTDC_LxCR_LEN_Pos (0U) 9992 #define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) 9993 #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk 9994 #define LTDC_LxCR_COLKEN_Pos (1U) 9995 #define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) 9996 #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk 9997 #define LTDC_LxCR_CLUTEN_Pos (4U) 9998 #define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) 9999 #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk 10003 #define LTDC_LxWHPCR_WHSTPOS_Pos (0U) 10004 #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) 10005 #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk 10006 #define LTDC_LxWHPCR_WHSPPOS_Pos (16U) 10007 #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) 10008 #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk 10012 #define LTDC_LxWVPCR_WVSTPOS_Pos (0U) 10013 #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) 10014 #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk 10015 #define LTDC_LxWVPCR_WVSPPOS_Pos (16U) 10016 #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) 10017 #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk 10021 #define LTDC_LxCKCR_CKBLUE_Pos (0U) 10022 #define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) 10023 #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk 10024 #define LTDC_LxCKCR_CKGREEN_Pos (8U) 10025 #define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) 10026 #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk 10027 #define LTDC_LxCKCR_CKRED_Pos (16U) 10028 #define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) 10029 #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk 10033 #define LTDC_LxPFCR_PF_Pos (0U) 10034 #define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) 10035 #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk 10039 #define LTDC_LxCACR_CONSTA_Pos (0U) 10040 #define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) 10041 #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk 10045 #define LTDC_LxDCCR_DCBLUE_Pos (0U) 10046 #define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) 10047 #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk 10048 #define LTDC_LxDCCR_DCGREEN_Pos (8U) 10049 #define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) 10050 #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk 10051 #define LTDC_LxDCCR_DCRED_Pos (16U) 10052 #define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) 10053 #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk 10054 #define LTDC_LxDCCR_DCALPHA_Pos (24U) 10055 #define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) 10056 #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk 10060 #define LTDC_LxBFCR_BF2_Pos (0U) 10061 #define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) 10062 #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk 10063 #define LTDC_LxBFCR_BF1_Pos (8U) 10064 #define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) 10065 #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk 10069 #define LTDC_LxCFBAR_CFBADD_Pos (0U) 10070 #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) 10071 #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk 10075 #define LTDC_LxCFBLR_CFBLL_Pos (0U) 10076 #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) 10077 #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk 10078 #define LTDC_LxCFBLR_CFBP_Pos (16U) 10079 #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) 10080 #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk 10084 #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U) 10085 #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) 10086 #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk 10090 #define LTDC_LxCLUTWR_BLUE_Pos (0U) 10091 #define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) 10092 #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk 10093 #define LTDC_LxCLUTWR_GREEN_Pos (8U) 10094 #define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) 10095 #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk 10096 #define LTDC_LxCLUTWR_RED_Pos (16U) 10097 #define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) 10098 #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk 10099 #define LTDC_LxCLUTWR_CLUTADD_Pos (24U) 10100 #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) 10101 #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk 10109 #define PWR_CR1_LPDS_Pos (0U) 10110 #define PWR_CR1_LPDS_Msk (0x1U << PWR_CR1_LPDS_Pos) 10111 #define PWR_CR1_LPDS PWR_CR1_LPDS_Msk 10112 #define PWR_CR1_PDDS_Pos (1U) 10113 #define PWR_CR1_PDDS_Msk (0x1U << PWR_CR1_PDDS_Pos) 10114 #define PWR_CR1_PDDS PWR_CR1_PDDS_Msk 10115 #define PWR_CR1_CSBF_Pos (3U) 10116 #define PWR_CR1_CSBF_Msk (0x1U << PWR_CR1_CSBF_Pos) 10117 #define PWR_CR1_CSBF PWR_CR1_CSBF_Msk 10118 #define PWR_CR1_PVDE_Pos (4U) 10119 #define PWR_CR1_PVDE_Msk (0x1U << PWR_CR1_PVDE_Pos) 10120 #define PWR_CR1_PVDE PWR_CR1_PVDE_Msk 10121 #define PWR_CR1_PLS_Pos (5U) 10122 #define PWR_CR1_PLS_Msk (0x7U << PWR_CR1_PLS_Pos) 10123 #define PWR_CR1_PLS PWR_CR1_PLS_Msk 10124 #define PWR_CR1_PLS_0 (0x1U << PWR_CR1_PLS_Pos) 10125 #define PWR_CR1_PLS_1 (0x2U << PWR_CR1_PLS_Pos) 10126 #define PWR_CR1_PLS_2 (0x4U << PWR_CR1_PLS_Pos) 10129 #define PWR_CR1_PLS_LEV0 0x00000000U 10130 #define PWR_CR1_PLS_LEV1_Pos (5U) 10131 #define PWR_CR1_PLS_LEV1_Msk (0x1U << PWR_CR1_PLS_LEV1_Pos) 10132 #define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk 10133 #define PWR_CR1_PLS_LEV2_Pos (6U) 10134 #define PWR_CR1_PLS_LEV2_Msk (0x1U << PWR_CR1_PLS_LEV2_Pos) 10135 #define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk 10136 #define PWR_CR1_PLS_LEV3_Pos (5U) 10137 #define PWR_CR1_PLS_LEV3_Msk (0x3U << PWR_CR1_PLS_LEV3_Pos) 10138 #define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk 10139 #define PWR_CR1_PLS_LEV4_Pos (7U) 10140 #define PWR_CR1_PLS_LEV4_Msk (0x1U << PWR_CR1_PLS_LEV4_Pos) 10141 #define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk 10142 #define PWR_CR1_PLS_LEV5_Pos (5U) 10143 #define PWR_CR1_PLS_LEV5_Msk (0x5U << PWR_CR1_PLS_LEV5_Pos) 10144 #define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk 10145 #define PWR_CR1_PLS_LEV6_Pos (6U) 10146 #define PWR_CR1_PLS_LEV6_Msk (0x3U << PWR_CR1_PLS_LEV6_Pos) 10147 #define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk 10148 #define PWR_CR1_PLS_LEV7_Pos (5U) 10149 #define PWR_CR1_PLS_LEV7_Msk (0x7U << PWR_CR1_PLS_LEV7_Pos) 10150 #define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk 10151 #define PWR_CR1_DBP_Pos (8U) 10152 #define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) 10153 #define PWR_CR1_DBP PWR_CR1_DBP_Msk 10154 #define PWR_CR1_FPDS_Pos (9U) 10155 #define PWR_CR1_FPDS_Msk (0x1U << PWR_CR1_FPDS_Pos) 10156 #define PWR_CR1_FPDS PWR_CR1_FPDS_Msk 10157 #define PWR_CR1_LPUDS_Pos (10U) 10158 #define PWR_CR1_LPUDS_Msk (0x1U << PWR_CR1_LPUDS_Pos) 10159 #define PWR_CR1_LPUDS PWR_CR1_LPUDS_Msk 10160 #define PWR_CR1_MRUDS_Pos (11U) 10161 #define PWR_CR1_MRUDS_Msk (0x1U << PWR_CR1_MRUDS_Pos) 10162 #define PWR_CR1_MRUDS PWR_CR1_MRUDS_Msk 10163 #define PWR_CR1_ADCDC1_Pos (13U) 10164 #define PWR_CR1_ADCDC1_Msk (0x1U << PWR_CR1_ADCDC1_Pos) 10165 #define PWR_CR1_ADCDC1 PWR_CR1_ADCDC1_Msk 10166 #define PWR_CR1_VOS_Pos (14U) 10167 #define PWR_CR1_VOS_Msk (0x3U << PWR_CR1_VOS_Pos) 10168 #define PWR_CR1_VOS PWR_CR1_VOS_Msk 10169 #define PWR_CR1_VOS_0 (0x1U << PWR_CR1_VOS_Pos) 10170 #define PWR_CR1_VOS_1 (0x2U << PWR_CR1_VOS_Pos) 10171 #define PWR_CR1_ODEN_Pos (16U) 10172 #define PWR_CR1_ODEN_Msk (0x1U << PWR_CR1_ODEN_Pos) 10173 #define PWR_CR1_ODEN PWR_CR1_ODEN_Msk 10174 #define PWR_CR1_ODSWEN_Pos (17U) 10175 #define PWR_CR1_ODSWEN_Msk (0x1U << PWR_CR1_ODSWEN_Pos) 10176 #define PWR_CR1_ODSWEN PWR_CR1_ODSWEN_Msk 10177 #define PWR_CR1_UDEN_Pos (18U) 10178 #define PWR_CR1_UDEN_Msk (0x3U << PWR_CR1_UDEN_Pos) 10179 #define PWR_CR1_UDEN PWR_CR1_UDEN_Msk 10180 #define PWR_CR1_UDEN_0 (0x1U << PWR_CR1_UDEN_Pos) 10181 #define PWR_CR1_UDEN_1 (0x2U << PWR_CR1_UDEN_Pos) 10184 #define PWR_CSR1_WUIF_Pos (0U) 10185 #define PWR_CSR1_WUIF_Msk (0x1U << PWR_CSR1_WUIF_Pos) 10186 #define PWR_CSR1_WUIF PWR_CSR1_WUIF_Msk 10187 #define PWR_CSR1_SBF_Pos (1U) 10188 #define PWR_CSR1_SBF_Msk (0x1U << PWR_CSR1_SBF_Pos) 10189 #define PWR_CSR1_SBF PWR_CSR1_SBF_Msk 10190 #define PWR_CSR1_PVDO_Pos (2U) 10191 #define PWR_CSR1_PVDO_Msk (0x1U << PWR_CSR1_PVDO_Pos) 10192 #define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk 10193 #define PWR_CSR1_BRR_Pos (3U) 10194 #define PWR_CSR1_BRR_Msk (0x1U << PWR_CSR1_BRR_Pos) 10195 #define PWR_CSR1_BRR PWR_CSR1_BRR_Msk 10196 #define PWR_CSR1_EIWUP_Pos (8U) 10197 #define PWR_CSR1_EIWUP_Msk (0x1U << PWR_CSR1_EIWUP_Pos) 10198 #define PWR_CSR1_EIWUP PWR_CSR1_EIWUP_Msk 10199 #define PWR_CSR1_BRE_Pos (9U) 10200 #define PWR_CSR1_BRE_Msk (0x1U << PWR_CSR1_BRE_Pos) 10201 #define PWR_CSR1_BRE PWR_CSR1_BRE_Msk 10202 #define PWR_CSR1_VOSRDY_Pos (14U) 10203 #define PWR_CSR1_VOSRDY_Msk (0x1U << PWR_CSR1_VOSRDY_Pos) 10204 #define PWR_CSR1_VOSRDY PWR_CSR1_VOSRDY_Msk 10205 #define PWR_CSR1_ODRDY_Pos (16U) 10206 #define PWR_CSR1_ODRDY_Msk (0x1U << PWR_CSR1_ODRDY_Pos) 10207 #define PWR_CSR1_ODRDY PWR_CSR1_ODRDY_Msk 10208 #define PWR_CSR1_ODSWRDY_Pos (17U) 10209 #define PWR_CSR1_ODSWRDY_Msk (0x1U << PWR_CSR1_ODSWRDY_Pos) 10210 #define PWR_CSR1_ODSWRDY PWR_CSR1_ODSWRDY_Msk 10211 #define PWR_CSR1_UDRDY_Pos (18U) 10212 #define PWR_CSR1_UDRDY_Msk (0x3U << PWR_CSR1_UDRDY_Pos) 10213 #define PWR_CSR1_UDRDY PWR_CSR1_UDRDY_Msk 10217 #define PWR_CR2_CWUPF1_Pos (0U) 10218 #define PWR_CR2_CWUPF1_Msk (0x1U << PWR_CR2_CWUPF1_Pos) 10219 #define PWR_CR2_CWUPF1 PWR_CR2_CWUPF1_Msk 10220 #define PWR_CR2_CWUPF2_Pos (1U) 10221 #define PWR_CR2_CWUPF2_Msk (0x1U << PWR_CR2_CWUPF2_Pos) 10222 #define PWR_CR2_CWUPF2 PWR_CR2_CWUPF2_Msk 10223 #define PWR_CR2_CWUPF3_Pos (2U) 10224 #define PWR_CR2_CWUPF3_Msk (0x1U << PWR_CR2_CWUPF3_Pos) 10225 #define PWR_CR2_CWUPF3 PWR_CR2_CWUPF3_Msk 10226 #define PWR_CR2_CWUPF4_Pos (3U) 10227 #define PWR_CR2_CWUPF4_Msk (0x1U << PWR_CR2_CWUPF4_Pos) 10228 #define PWR_CR2_CWUPF4 PWR_CR2_CWUPF4_Msk 10229 #define PWR_CR2_CWUPF5_Pos (4U) 10230 #define PWR_CR2_CWUPF5_Msk (0x1U << PWR_CR2_CWUPF5_Pos) 10231 #define PWR_CR2_CWUPF5 PWR_CR2_CWUPF5_Msk 10232 #define PWR_CR2_CWUPF6_Pos (5U) 10233 #define PWR_CR2_CWUPF6_Msk (0x1U << PWR_CR2_CWUPF6_Pos) 10234 #define PWR_CR2_CWUPF6 PWR_CR2_CWUPF6_Msk 10235 #define PWR_CR2_WUPP1_Pos (8U) 10236 #define PWR_CR2_WUPP1_Msk (0x1U << PWR_CR2_WUPP1_Pos) 10237 #define PWR_CR2_WUPP1 PWR_CR2_WUPP1_Msk 10238 #define PWR_CR2_WUPP2_Pos (9U) 10239 #define PWR_CR2_WUPP2_Msk (0x1U << PWR_CR2_WUPP2_Pos) 10240 #define PWR_CR2_WUPP2 PWR_CR2_WUPP2_Msk 10241 #define PWR_CR2_WUPP3_Pos (10U) 10242 #define PWR_CR2_WUPP3_Msk (0x1U << PWR_CR2_WUPP3_Pos) 10243 #define PWR_CR2_WUPP3 PWR_CR2_WUPP3_Msk 10244 #define PWR_CR2_WUPP4_Pos (11U) 10245 #define PWR_CR2_WUPP4_Msk (0x1U << PWR_CR2_WUPP4_Pos) 10246 #define PWR_CR2_WUPP4 PWR_CR2_WUPP4_Msk 10247 #define PWR_CR2_WUPP5_Pos (12U) 10248 #define PWR_CR2_WUPP5_Msk (0x1U << PWR_CR2_WUPP5_Pos) 10249 #define PWR_CR2_WUPP5 PWR_CR2_WUPP5_Msk 10250 #define PWR_CR2_WUPP6_Pos (13U) 10251 #define PWR_CR2_WUPP6_Msk (0x1U << PWR_CR2_WUPP6_Pos) 10252 #define PWR_CR2_WUPP6 PWR_CR2_WUPP6_Msk 10255 #define PWR_CSR2_WUPF1_Pos (0U) 10256 #define PWR_CSR2_WUPF1_Msk (0x1U << PWR_CSR2_WUPF1_Pos) 10257 #define PWR_CSR2_WUPF1 PWR_CSR2_WUPF1_Msk 10258 #define PWR_CSR2_WUPF2_Pos (1U) 10259 #define PWR_CSR2_WUPF2_Msk (0x1U << PWR_CSR2_WUPF2_Pos) 10260 #define PWR_CSR2_WUPF2 PWR_CSR2_WUPF2_Msk 10261 #define PWR_CSR2_WUPF3_Pos (2U) 10262 #define PWR_CSR2_WUPF3_Msk (0x1U << PWR_CSR2_WUPF3_Pos) 10263 #define PWR_CSR2_WUPF3 PWR_CSR2_WUPF3_Msk 10264 #define PWR_CSR2_WUPF4_Pos (3U) 10265 #define PWR_CSR2_WUPF4_Msk (0x1U << PWR_CSR2_WUPF4_Pos) 10266 #define PWR_CSR2_WUPF4 PWR_CSR2_WUPF4_Msk 10267 #define PWR_CSR2_WUPF5_Pos (4U) 10268 #define PWR_CSR2_WUPF5_Msk (0x1U << PWR_CSR2_WUPF5_Pos) 10269 #define PWR_CSR2_WUPF5 PWR_CSR2_WUPF5_Msk 10270 #define PWR_CSR2_WUPF6_Pos (5U) 10271 #define PWR_CSR2_WUPF6_Msk (0x1U << PWR_CSR2_WUPF6_Pos) 10272 #define PWR_CSR2_WUPF6 PWR_CSR2_WUPF6_Msk 10273 #define PWR_CSR2_EWUP1_Pos (8U) 10274 #define PWR_CSR2_EWUP1_Msk (0x1U << PWR_CSR2_EWUP1_Pos) 10275 #define PWR_CSR2_EWUP1 PWR_CSR2_EWUP1_Msk 10276 #define PWR_CSR2_EWUP2_Pos (9U) 10277 #define PWR_CSR2_EWUP2_Msk (0x1U << PWR_CSR2_EWUP2_Pos) 10278 #define PWR_CSR2_EWUP2 PWR_CSR2_EWUP2_Msk 10279 #define PWR_CSR2_EWUP3_Pos (10U) 10280 #define PWR_CSR2_EWUP3_Msk (0x1U << PWR_CSR2_EWUP3_Pos) 10281 #define PWR_CSR2_EWUP3 PWR_CSR2_EWUP3_Msk 10282 #define PWR_CSR2_EWUP4_Pos (11U) 10283 #define PWR_CSR2_EWUP4_Msk (0x1U << PWR_CSR2_EWUP4_Pos) 10284 #define PWR_CSR2_EWUP4 PWR_CSR2_EWUP4_Msk 10285 #define PWR_CSR2_EWUP5_Pos (12U) 10286 #define PWR_CSR2_EWUP5_Msk (0x1U << PWR_CSR2_EWUP5_Pos) 10287 #define PWR_CSR2_EWUP5 PWR_CSR2_EWUP5_Msk 10288 #define PWR_CSR2_EWUP6_Pos (13U) 10289 #define PWR_CSR2_EWUP6_Msk (0x1U << PWR_CSR2_EWUP6_Pos) 10290 #define PWR_CSR2_EWUP6 PWR_CSR2_EWUP6_Msk 10298 #define QUADSPI_CR_EN_Pos (0U) 10299 #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) 10300 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk 10301 #define QUADSPI_CR_ABORT_Pos (1U) 10302 #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) 10303 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk 10304 #define QUADSPI_CR_DMAEN_Pos (2U) 10305 #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) 10306 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk 10307 #define QUADSPI_CR_TCEN_Pos (3U) 10308 #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) 10309 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk 10310 #define QUADSPI_CR_SSHIFT_Pos (4U) 10311 #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) 10312 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk 10313 #define QUADSPI_CR_DFM_Pos (6U) 10314 #define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) 10315 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk 10316 #define QUADSPI_CR_FSEL_Pos (7U) 10317 #define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) 10318 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk 10319 #define QUADSPI_CR_FTHRES_Pos (8U) 10320 #define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) 10321 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk 10322 #define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) 10323 #define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) 10324 #define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) 10325 #define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) 10326 #define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) 10327 #define QUADSPI_CR_TEIE_Pos (16U) 10328 #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) 10329 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk 10330 #define QUADSPI_CR_TCIE_Pos (17U) 10331 #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) 10332 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk 10333 #define QUADSPI_CR_FTIE_Pos (18U) 10334 #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) 10335 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk 10336 #define QUADSPI_CR_SMIE_Pos (19U) 10337 #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) 10338 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk 10339 #define QUADSPI_CR_TOIE_Pos (20U) 10340 #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) 10341 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk 10342 #define QUADSPI_CR_APMS_Pos (22U) 10343 #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) 10344 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk 10345 #define QUADSPI_CR_PMM_Pos (23U) 10346 #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) 10347 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk 10348 #define QUADSPI_CR_PRESCALER_Pos (24U) 10349 #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) 10350 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk 10351 #define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) 10352 #define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) 10353 #define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) 10354 #define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) 10355 #define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) 10356 #define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) 10357 #define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) 10358 #define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) 10361 #define QUADSPI_DCR_CKMODE_Pos (0U) 10362 #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) 10363 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk 10364 #define QUADSPI_DCR_CSHT_Pos (8U) 10365 #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) 10366 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk 10367 #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) 10368 #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) 10369 #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) 10370 #define QUADSPI_DCR_FSIZE_Pos (16U) 10371 #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) 10372 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk 10373 #define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) 10374 #define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) 10375 #define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) 10376 #define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) 10377 #define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) 10380 #define QUADSPI_SR_TEF_Pos (0U) 10381 #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) 10382 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk 10383 #define QUADSPI_SR_TCF_Pos (1U) 10384 #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) 10385 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk 10386 #define QUADSPI_SR_FTF_Pos (2U) 10387 #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) 10388 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk 10389 #define QUADSPI_SR_SMF_Pos (3U) 10390 #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) 10391 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk 10392 #define QUADSPI_SR_TOF_Pos (4U) 10393 #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) 10394 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk 10395 #define QUADSPI_SR_BUSY_Pos (5U) 10396 #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) 10397 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk 10398 #define QUADSPI_SR_FLEVEL_Pos (8U) 10399 #define QUADSPI_SR_FLEVEL_Msk (0x1FU << QUADSPI_SR_FLEVEL_Pos) 10400 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk 10401 #define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) 10402 #define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) 10403 #define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) 10404 #define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) 10405 #define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) 10408 #define QUADSPI_FCR_CTEF_Pos (0U) 10409 #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) 10410 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk 10411 #define QUADSPI_FCR_CTCF_Pos (1U) 10412 #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) 10413 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk 10414 #define QUADSPI_FCR_CSMF_Pos (3U) 10415 #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) 10416 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk 10417 #define QUADSPI_FCR_CTOF_Pos (4U) 10418 #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) 10419 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk 10422 #define QUADSPI_DLR_DL_Pos (0U) 10423 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) 10424 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk 10427 #define QUADSPI_CCR_INSTRUCTION_Pos (0U) 10428 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) 10429 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk 10430 #define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) 10431 #define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) 10432 #define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) 10433 #define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) 10434 #define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) 10435 #define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) 10436 #define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) 10437 #define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) 10438 #define QUADSPI_CCR_IMODE_Pos (8U) 10439 #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) 10440 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk 10441 #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) 10442 #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) 10443 #define QUADSPI_CCR_ADMODE_Pos (10U) 10444 #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) 10445 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk 10446 #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) 10447 #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) 10448 #define QUADSPI_CCR_ADSIZE_Pos (12U) 10449 #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) 10450 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk 10451 #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) 10452 #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) 10453 #define QUADSPI_CCR_ABMODE_Pos (14U) 10454 #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) 10455 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk 10456 #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) 10457 #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) 10458 #define QUADSPI_CCR_ABSIZE_Pos (16U) 10459 #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) 10460 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk 10461 #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) 10462 #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) 10463 #define QUADSPI_CCR_DCYC_Pos (18U) 10464 #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) 10465 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk 10466 #define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) 10467 #define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) 10468 #define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) 10469 #define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) 10470 #define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) 10471 #define QUADSPI_CCR_DMODE_Pos (24U) 10472 #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) 10473 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk 10474 #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) 10475 #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) 10476 #define QUADSPI_CCR_FMODE_Pos (26U) 10477 #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) 10478 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk 10479 #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) 10480 #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) 10481 #define QUADSPI_CCR_SIOO_Pos (28U) 10482 #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) 10483 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk 10484 #define QUADSPI_CCR_DHHC_Pos (30U) 10485 #define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) 10486 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk 10487 #define QUADSPI_CCR_DDRM_Pos (31U) 10488 #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) 10489 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk 10491 #define QUADSPI_AR_ADDRESS_Pos (0U) 10492 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) 10493 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk 10496 #define QUADSPI_ABR_ALTERNATE_Pos (0U) 10497 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) 10498 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk 10501 #define QUADSPI_DR_DATA_Pos (0U) 10502 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) 10503 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk 10506 #define QUADSPI_PSMKR_MASK_Pos (0U) 10507 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) 10508 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk 10511 #define QUADSPI_PSMAR_MATCH_Pos (0U) 10512 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) 10513 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk 10516 #define QUADSPI_PIR_INTERVAL_Pos (0U) 10517 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) 10518 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk 10521 #define QUADSPI_LPTR_TIMEOUT_Pos (0U) 10522 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) 10523 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk 10531 #define RCC_CR_HSION_Pos (0U) 10532 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) 10533 #define RCC_CR_HSION RCC_CR_HSION_Msk 10534 #define RCC_CR_HSIRDY_Pos (1U) 10535 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) 10536 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk 10537 #define RCC_CR_HSITRIM_Pos (3U) 10538 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) 10539 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk 10540 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) 10541 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) 10542 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) 10543 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) 10544 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) 10545 #define RCC_CR_HSICAL_Pos (8U) 10546 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) 10547 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk 10548 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) 10549 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) 10550 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) 10551 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) 10552 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) 10553 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) 10554 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) 10555 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) 10556 #define RCC_CR_HSEON_Pos (16U) 10557 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) 10558 #define RCC_CR_HSEON RCC_CR_HSEON_Msk 10559 #define RCC_CR_HSERDY_Pos (17U) 10560 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) 10561 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk 10562 #define RCC_CR_HSEBYP_Pos (18U) 10563 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) 10564 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk 10565 #define RCC_CR_CSSON_Pos (19U) 10566 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) 10567 #define RCC_CR_CSSON RCC_CR_CSSON_Msk 10568 #define RCC_CR_PLLON_Pos (24U) 10569 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) 10570 #define RCC_CR_PLLON RCC_CR_PLLON_Msk 10571 #define RCC_CR_PLLRDY_Pos (25U) 10572 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) 10573 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk 10574 #define RCC_CR_PLLI2SON_Pos (26U) 10575 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) 10576 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk 10577 #define RCC_CR_PLLI2SRDY_Pos (27U) 10578 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) 10579 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk 10580 #define RCC_CR_PLLSAION_Pos (28U) 10581 #define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) 10582 #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk 10583 #define RCC_CR_PLLSAIRDY_Pos (29U) 10584 #define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) 10585 #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk 10588 #define RCC_PLLCFGR_PLLM_Pos (0U) 10589 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) 10590 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk 10591 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) 10592 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) 10593 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) 10594 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) 10595 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) 10596 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) 10597 #define RCC_PLLCFGR_PLLN_Pos (6U) 10598 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) 10599 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk 10600 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) 10601 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) 10602 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) 10603 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) 10604 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) 10605 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) 10606 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) 10607 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) 10608 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) 10609 #define RCC_PLLCFGR_PLLP_Pos (16U) 10610 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) 10611 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk 10612 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) 10613 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) 10614 #define RCC_PLLCFGR_PLLSRC_Pos (22U) 10615 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) 10616 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk 10617 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U) 10618 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) 10619 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk 10620 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U 10621 #define RCC_PLLCFGR_PLLQ_Pos (24U) 10622 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) 10623 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk 10624 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) 10625 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) 10626 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) 10627 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) 10629 #define RCC_PLLCFGR_PLLR_Pos (28U) 10630 #define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) 10631 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk 10632 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) 10633 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) 10634 #define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) 10638 #define RCC_CFGR_SW_Pos (0U) 10639 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) 10640 #define RCC_CFGR_SW RCC_CFGR_SW_Msk 10641 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) 10642 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) 10643 #define RCC_CFGR_SW_HSI 0x00000000U 10644 #define RCC_CFGR_SW_HSE 0x00000001U 10645 #define RCC_CFGR_SW_PLL 0x00000002U 10648 #define RCC_CFGR_SWS_Pos (2U) 10649 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) 10650 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk 10651 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) 10652 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) 10653 #define RCC_CFGR_SWS_HSI 0x00000000U 10654 #define RCC_CFGR_SWS_HSE 0x00000004U 10655 #define RCC_CFGR_SWS_PLL 0x00000008U 10658 #define RCC_CFGR_HPRE_Pos (4U) 10659 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) 10660 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk 10661 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) 10662 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) 10663 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) 10664 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) 10666 #define RCC_CFGR_HPRE_DIV1 0x00000000U 10667 #define RCC_CFGR_HPRE_DIV2 0x00000080U 10668 #define RCC_CFGR_HPRE_DIV4 0x00000090U 10669 #define RCC_CFGR_HPRE_DIV8 0x000000A0U 10670 #define RCC_CFGR_HPRE_DIV16 0x000000B0U 10671 #define RCC_CFGR_HPRE_DIV64 0x000000C0U 10672 #define RCC_CFGR_HPRE_DIV128 0x000000D0U 10673 #define RCC_CFGR_HPRE_DIV256 0x000000E0U 10674 #define RCC_CFGR_HPRE_DIV512 0x000000F0U 10677 #define RCC_CFGR_PPRE1_Pos (10U) 10678 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) 10679 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk 10680 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) 10681 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) 10682 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) 10684 #define RCC_CFGR_PPRE1_DIV1 0x00000000U 10685 #define RCC_CFGR_PPRE1_DIV2 0x00001000U 10686 #define RCC_CFGR_PPRE1_DIV4 0x00001400U 10687 #define RCC_CFGR_PPRE1_DIV8 0x00001800U 10688 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U 10691 #define RCC_CFGR_PPRE2_Pos (13U) 10692 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) 10693 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk 10694 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) 10695 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) 10696 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) 10698 #define RCC_CFGR_PPRE2_DIV1 0x00000000U 10699 #define RCC_CFGR_PPRE2_DIV2 0x00008000U 10700 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U 10701 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U 10702 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U 10705 #define RCC_CFGR_RTCPRE_Pos (16U) 10706 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) 10707 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk 10708 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) 10709 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) 10710 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) 10711 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) 10712 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) 10715 #define RCC_CFGR_MCO1_Pos (21U) 10716 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) 10717 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk 10718 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) 10719 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) 10721 #define RCC_CFGR_I2SSRC_Pos (23U) 10722 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) 10723 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk 10725 #define RCC_CFGR_MCO1PRE_Pos (24U) 10726 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) 10727 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk 10728 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) 10729 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) 10730 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) 10732 #define RCC_CFGR_MCO2PRE_Pos (27U) 10733 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) 10734 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk 10735 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) 10736 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) 10737 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) 10739 #define RCC_CFGR_MCO2_Pos (30U) 10740 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) 10741 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk 10742 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) 10743 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) 10746 #define RCC_CIR_LSIRDYF_Pos (0U) 10747 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) 10748 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk 10749 #define RCC_CIR_LSERDYF_Pos (1U) 10750 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) 10751 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk 10752 #define RCC_CIR_HSIRDYF_Pos (2U) 10753 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) 10754 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk 10755 #define RCC_CIR_HSERDYF_Pos (3U) 10756 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) 10757 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk 10758 #define RCC_CIR_PLLRDYF_Pos (4U) 10759 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) 10760 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk 10761 #define RCC_CIR_PLLI2SRDYF_Pos (5U) 10762 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) 10763 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk 10764 #define RCC_CIR_PLLSAIRDYF_Pos (6U) 10765 #define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) 10766 #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk 10767 #define RCC_CIR_CSSF_Pos (7U) 10768 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) 10769 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk 10770 #define RCC_CIR_LSIRDYIE_Pos (8U) 10771 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) 10772 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk 10773 #define RCC_CIR_LSERDYIE_Pos (9U) 10774 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) 10775 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk 10776 #define RCC_CIR_HSIRDYIE_Pos (10U) 10777 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) 10778 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk 10779 #define RCC_CIR_HSERDYIE_Pos (11U) 10780 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) 10781 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk 10782 #define RCC_CIR_PLLRDYIE_Pos (12U) 10783 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) 10784 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk 10785 #define RCC_CIR_PLLI2SRDYIE_Pos (13U) 10786 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) 10787 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk 10788 #define RCC_CIR_PLLSAIRDYIE_Pos (14U) 10789 #define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) 10790 #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk 10791 #define RCC_CIR_LSIRDYC_Pos (16U) 10792 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) 10793 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk 10794 #define RCC_CIR_LSERDYC_Pos (17U) 10795 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) 10796 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk 10797 #define RCC_CIR_HSIRDYC_Pos (18U) 10798 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) 10799 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk 10800 #define RCC_CIR_HSERDYC_Pos (19U) 10801 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) 10802 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk 10803 #define RCC_CIR_PLLRDYC_Pos (20U) 10804 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) 10805 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk 10806 #define RCC_CIR_PLLI2SRDYC_Pos (21U) 10807 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) 10808 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk 10809 #define RCC_CIR_PLLSAIRDYC_Pos (22U) 10810 #define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) 10811 #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk 10812 #define RCC_CIR_CSSC_Pos (23U) 10813 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) 10814 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk 10817 #define RCC_AHB1RSTR_GPIOARST_Pos (0U) 10818 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) 10819 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk 10820 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U) 10821 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) 10822 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk 10823 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U) 10824 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) 10825 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk 10826 #define RCC_AHB1RSTR_GPIODRST_Pos (3U) 10827 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) 10828 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk 10829 #define RCC_AHB1RSTR_GPIOERST_Pos (4U) 10830 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) 10831 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk 10832 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U) 10833 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) 10834 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk 10835 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U) 10836 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) 10837 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk 10838 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U) 10839 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) 10840 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk 10841 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U) 10842 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) 10843 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk 10844 #define RCC_AHB1RSTR_GPIOJRST_Pos (9U) 10845 #define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) 10846 #define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk 10847 #define RCC_AHB1RSTR_GPIOKRST_Pos (10U) 10848 #define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) 10849 #define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk 10850 #define RCC_AHB1RSTR_CRCRST_Pos (12U) 10851 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) 10852 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk 10853 #define RCC_AHB1RSTR_DMA1RST_Pos (21U) 10854 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) 10855 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk 10856 #define RCC_AHB1RSTR_DMA2RST_Pos (22U) 10857 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) 10858 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk 10859 #define RCC_AHB1RSTR_DMA2DRST_Pos (23U) 10860 #define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) 10861 #define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk 10862 #define RCC_AHB1RSTR_ETHMACRST_Pos (25U) 10863 #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) 10864 #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk 10865 #define RCC_AHB1RSTR_OTGHRST_Pos (29U) 10866 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) 10867 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk 10870 #define RCC_AHB2RSTR_DCMIRST_Pos (0U) 10871 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) 10872 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk 10873 #define RCC_AHB2RSTR_JPEGRST_Pos (1U) 10874 #define RCC_AHB2RSTR_JPEGRST_Msk (0x1U << RCC_AHB2RSTR_JPEGRST_Pos) 10875 #define RCC_AHB2RSTR_JPEGRST RCC_AHB2RSTR_JPEGRST_Msk 10876 #define RCC_AHB2RSTR_RNGRST_Pos (6U) 10877 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) 10878 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk 10879 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U) 10880 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) 10881 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk 10885 #define RCC_AHB3RSTR_FMCRST_Pos (0U) 10886 #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) 10887 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk 10888 #define RCC_AHB3RSTR_QSPIRST_Pos (1U) 10889 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) 10890 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk 10893 #define RCC_APB1RSTR_TIM2RST_Pos (0U) 10894 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) 10895 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk 10896 #define RCC_APB1RSTR_TIM3RST_Pos (1U) 10897 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) 10898 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk 10899 #define RCC_APB1RSTR_TIM4RST_Pos (2U) 10900 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) 10901 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk 10902 #define RCC_APB1RSTR_TIM5RST_Pos (3U) 10903 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) 10904 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk 10905 #define RCC_APB1RSTR_TIM6RST_Pos (4U) 10906 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) 10907 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk 10908 #define RCC_APB1RSTR_TIM7RST_Pos (5U) 10909 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) 10910 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk 10911 #define RCC_APB1RSTR_TIM12RST_Pos (6U) 10912 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) 10913 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk 10914 #define RCC_APB1RSTR_TIM13RST_Pos (7U) 10915 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) 10916 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk 10917 #define RCC_APB1RSTR_TIM14RST_Pos (8U) 10918 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) 10919 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk 10920 #define RCC_APB1RSTR_LPTIM1RST_Pos (9U) 10921 #define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) 10922 #define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk 10923 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 10924 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) 10925 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk 10926 #define RCC_APB1RSTR_CAN3RST_Pos (13U) 10927 #define RCC_APB1RSTR_CAN3RST_Msk (0x1U << RCC_APB1RSTR_CAN3RST_Pos) 10928 #define RCC_APB1RSTR_CAN3RST RCC_APB1RSTR_CAN3RST_Msk 10929 #define RCC_APB1RSTR_SPI2RST_Pos (14U) 10930 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) 10931 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk 10932 #define RCC_APB1RSTR_SPI3RST_Pos (15U) 10933 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) 10934 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk 10935 #define RCC_APB1RSTR_SPDIFRXRST_Pos (16U) 10936 #define RCC_APB1RSTR_SPDIFRXRST_Msk (0x1U << RCC_APB1RSTR_SPDIFRXRST_Pos) 10937 #define RCC_APB1RSTR_SPDIFRXRST RCC_APB1RSTR_SPDIFRXRST_Msk 10938 #define RCC_APB1RSTR_USART2RST_Pos (17U) 10939 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) 10940 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk 10941 #define RCC_APB1RSTR_USART3RST_Pos (18U) 10942 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) 10943 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk 10944 #define RCC_APB1RSTR_UART4RST_Pos (19U) 10945 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) 10946 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk 10947 #define RCC_APB1RSTR_UART5RST_Pos (20U) 10948 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) 10949 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk 10950 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 10951 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) 10952 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk 10953 #define RCC_APB1RSTR_I2C2RST_Pos (22U) 10954 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) 10955 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk 10956 #define RCC_APB1RSTR_I2C3RST_Pos (23U) 10957 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) 10958 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk 10959 #define RCC_APB1RSTR_I2C4RST_Pos (24U) 10960 #define RCC_APB1RSTR_I2C4RST_Msk (0x1U << RCC_APB1RSTR_I2C4RST_Pos) 10961 #define RCC_APB1RSTR_I2C4RST RCC_APB1RSTR_I2C4RST_Msk 10962 #define RCC_APB1RSTR_CAN1RST_Pos (25U) 10963 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) 10964 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk 10965 #define RCC_APB1RSTR_CAN2RST_Pos (26U) 10966 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) 10967 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk 10968 #define RCC_APB1RSTR_CECRST_Pos (27U) 10969 #define RCC_APB1RSTR_CECRST_Msk (0x1U << RCC_APB1RSTR_CECRST_Pos) 10970 #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk 10971 #define RCC_APB1RSTR_PWRRST_Pos (28U) 10972 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) 10973 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk 10974 #define RCC_APB1RSTR_DACRST_Pos (29U) 10975 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) 10976 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk 10977 #define RCC_APB1RSTR_UART7RST_Pos (30U) 10978 #define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) 10979 #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk 10980 #define RCC_APB1RSTR_UART8RST_Pos (31U) 10981 #define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) 10982 #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk 10985 #define RCC_APB2RSTR_TIM1RST_Pos (0U) 10986 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) 10987 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk 10988 #define RCC_APB2RSTR_TIM8RST_Pos (1U) 10989 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) 10990 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk 10991 #define RCC_APB2RSTR_USART1RST_Pos (4U) 10992 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) 10993 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk 10994 #define RCC_APB2RSTR_USART6RST_Pos (5U) 10995 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) 10996 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk 10997 #define RCC_APB2RSTR_SDMMC2RST_Pos (7U) 10998 #define RCC_APB2RSTR_SDMMC2RST_Msk (0x1U << RCC_APB2RSTR_SDMMC2RST_Pos) 10999 #define RCC_APB2RSTR_SDMMC2RST RCC_APB2RSTR_SDMMC2RST_Msk 11000 #define RCC_APB2RSTR_ADCRST_Pos (8U) 11001 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) 11002 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk 11003 #define RCC_APB2RSTR_SDMMC1RST_Pos (11U) 11004 #define RCC_APB2RSTR_SDMMC1RST_Msk (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) 11005 #define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk 11006 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 11007 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) 11008 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk 11009 #define RCC_APB2RSTR_SPI4RST_Pos (13U) 11010 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) 11011 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk 11012 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U) 11013 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) 11014 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk 11015 #define RCC_APB2RSTR_TIM9RST_Pos (16U) 11016 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) 11017 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk 11018 #define RCC_APB2RSTR_TIM10RST_Pos (17U) 11019 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) 11020 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk 11021 #define RCC_APB2RSTR_TIM11RST_Pos (18U) 11022 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) 11023 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk 11024 #define RCC_APB2RSTR_SPI5RST_Pos (20U) 11025 #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) 11026 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk 11027 #define RCC_APB2RSTR_SPI6RST_Pos (21U) 11028 #define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) 11029 #define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk 11030 #define RCC_APB2RSTR_SAI1RST_Pos (22U) 11031 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) 11032 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk 11033 #define RCC_APB2RSTR_SAI2RST_Pos (23U) 11034 #define RCC_APB2RSTR_SAI2RST_Msk (0x1U << RCC_APB2RSTR_SAI2RST_Pos) 11035 #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk 11036 #define RCC_APB2RSTR_LTDCRST_Pos (26U) 11037 #define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) 11038 #define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk 11039 #define RCC_APB2RSTR_DSIRST_Pos (27U) 11040 #define RCC_APB2RSTR_DSIRST_Msk (0x1U << RCC_APB2RSTR_DSIRST_Pos) 11041 #define RCC_APB2RSTR_DSIRST RCC_APB2RSTR_DSIRST_Msk 11042 #define RCC_APB2RSTR_DFSDM1RST_Pos (29U) 11043 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) 11044 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk 11045 #define RCC_APB2RSTR_MDIORST_Pos (30U) 11046 #define RCC_APB2RSTR_MDIORST_Msk (0x1U << RCC_APB2RSTR_MDIORST_Pos) 11047 #define RCC_APB2RSTR_MDIORST RCC_APB2RSTR_MDIORST_Msk 11050 #define RCC_AHB1ENR_GPIOAEN_Pos (0U) 11051 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) 11052 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk 11053 #define RCC_AHB1ENR_GPIOBEN_Pos (1U) 11054 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) 11055 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk 11056 #define RCC_AHB1ENR_GPIOCEN_Pos (2U) 11057 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) 11058 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk 11059 #define RCC_AHB1ENR_GPIODEN_Pos (3U) 11060 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) 11061 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk 11062 #define RCC_AHB1ENR_GPIOEEN_Pos (4U) 11063 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) 11064 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk 11065 #define RCC_AHB1ENR_GPIOFEN_Pos (5U) 11066 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) 11067 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk 11068 #define RCC_AHB1ENR_GPIOGEN_Pos (6U) 11069 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) 11070 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk 11071 #define RCC_AHB1ENR_GPIOHEN_Pos (7U) 11072 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) 11073 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk 11074 #define RCC_AHB1ENR_GPIOIEN_Pos (8U) 11075 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) 11076 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk 11077 #define RCC_AHB1ENR_GPIOJEN_Pos (9U) 11078 #define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) 11079 #define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk 11080 #define RCC_AHB1ENR_GPIOKEN_Pos (10U) 11081 #define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) 11082 #define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk 11083 #define RCC_AHB1ENR_CRCEN_Pos (12U) 11084 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) 11085 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk 11086 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U) 11087 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) 11088 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk 11089 #define RCC_AHB1ENR_DTCMRAMEN_Pos (20U) 11090 #define RCC_AHB1ENR_DTCMRAMEN_Msk (0x1U << RCC_AHB1ENR_DTCMRAMEN_Pos) 11091 #define RCC_AHB1ENR_DTCMRAMEN RCC_AHB1ENR_DTCMRAMEN_Msk 11092 #define RCC_AHB1ENR_DMA1EN_Pos (21U) 11093 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) 11094 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk 11095 #define RCC_AHB1ENR_DMA2EN_Pos (22U) 11096 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) 11097 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk 11098 #define RCC_AHB1ENR_DMA2DEN_Pos (23U) 11099 #define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) 11100 #define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk 11101 #define RCC_AHB1ENR_ETHMACEN_Pos (25U) 11102 #define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) 11103 #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk 11104 #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U) 11105 #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) 11106 #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk 11107 #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U) 11108 #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) 11109 #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk 11110 #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U) 11111 #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) 11112 #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk 11113 #define RCC_AHB1ENR_OTGHSEN_Pos (29U) 11114 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) 11115 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk 11116 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U) 11117 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) 11118 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk 11121 #define RCC_AHB2ENR_DCMIEN_Pos (0U) 11122 #define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) 11123 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk 11124 #define RCC_AHB2ENR_JPEGEN_Pos (1U) 11125 #define RCC_AHB2ENR_JPEGEN_Msk (0x1U << RCC_AHB2ENR_JPEGEN_Pos) 11126 #define RCC_AHB2ENR_JPEGEN RCC_AHB2ENR_JPEGEN_Msk 11127 #define RCC_AHB2ENR_RNGEN_Pos (6U) 11128 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) 11129 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk 11130 #define RCC_AHB2ENR_OTGFSEN_Pos (7U) 11131 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) 11132 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk 11135 #define RCC_AHB3ENR_FMCEN_Pos (0U) 11136 #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) 11137 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk 11138 #define RCC_AHB3ENR_QSPIEN_Pos (1U) 11139 #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) 11140 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk 11143 #define RCC_APB1ENR_TIM2EN_Pos (0U) 11144 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) 11145 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk 11146 #define RCC_APB1ENR_TIM3EN_Pos (1U) 11147 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) 11148 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk 11149 #define RCC_APB1ENR_TIM4EN_Pos (2U) 11150 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) 11151 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk 11152 #define RCC_APB1ENR_TIM5EN_Pos (3U) 11153 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) 11154 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk 11155 #define RCC_APB1ENR_TIM6EN_Pos (4U) 11156 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) 11157 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk 11158 #define RCC_APB1ENR_TIM7EN_Pos (5U) 11159 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) 11160 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk 11161 #define RCC_APB1ENR_TIM12EN_Pos (6U) 11162 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) 11163 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk 11164 #define RCC_APB1ENR_TIM13EN_Pos (7U) 11165 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) 11166 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk 11167 #define RCC_APB1ENR_TIM14EN_Pos (8U) 11168 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) 11169 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk 11170 #define RCC_APB1ENR_LPTIM1EN_Pos (9U) 11171 #define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) 11172 #define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk 11173 #define RCC_APB1ENR_RTCEN_Pos (10U) 11174 #define RCC_APB1ENR_RTCEN_Msk (0x1U << RCC_APB1ENR_RTCEN_Pos) 11175 #define RCC_APB1ENR_RTCEN RCC_APB1ENR_RTCEN_Msk 11176 #define RCC_APB1ENR_WWDGEN_Pos (11U) 11177 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) 11178 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk 11179 #define RCC_APB1ENR_CAN3EN_Pos (13U) 11180 #define RCC_APB1ENR_CAN3EN_Msk (0x1U << RCC_APB1ENR_CAN3EN_Pos) 11181 #define RCC_APB1ENR_CAN3EN RCC_APB1ENR_CAN3EN_Msk 11182 #define RCC_APB1ENR_SPI2EN_Pos (14U) 11183 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) 11184 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk 11185 #define RCC_APB1ENR_SPI3EN_Pos (15U) 11186 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) 11187 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk 11188 #define RCC_APB1ENR_SPDIFRXEN_Pos (16U) 11189 #define RCC_APB1ENR_SPDIFRXEN_Msk (0x1U << RCC_APB1ENR_SPDIFRXEN_Pos) 11190 #define RCC_APB1ENR_SPDIFRXEN RCC_APB1ENR_SPDIFRXEN_Msk 11191 #define RCC_APB1ENR_USART2EN_Pos (17U) 11192 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) 11193 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk 11194 #define RCC_APB1ENR_USART3EN_Pos (18U) 11195 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) 11196 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk 11197 #define RCC_APB1ENR_UART4EN_Pos (19U) 11198 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) 11199 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk 11200 #define RCC_APB1ENR_UART5EN_Pos (20U) 11201 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) 11202 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk 11203 #define RCC_APB1ENR_I2C1EN_Pos (21U) 11204 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) 11205 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk 11206 #define RCC_APB1ENR_I2C2EN_Pos (22U) 11207 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) 11208 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk 11209 #define RCC_APB1ENR_I2C3EN_Pos (23U) 11210 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) 11211 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk 11212 #define RCC_APB1ENR_I2C4EN_Pos (24U) 11213 #define RCC_APB1ENR_I2C4EN_Msk (0x1U << RCC_APB1ENR_I2C4EN_Pos) 11214 #define RCC_APB1ENR_I2C4EN RCC_APB1ENR_I2C4EN_Msk 11215 #define RCC_APB1ENR_CAN1EN_Pos (25U) 11216 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) 11217 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk 11218 #define RCC_APB1ENR_CAN2EN_Pos (26U) 11219 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) 11220 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk 11221 #define RCC_APB1ENR_CECEN_Pos (27U) 11222 #define RCC_APB1ENR_CECEN_Msk (0x1U << RCC_APB1ENR_CECEN_Pos) 11223 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk 11224 #define RCC_APB1ENR_PWREN_Pos (28U) 11225 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) 11226 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk 11227 #define RCC_APB1ENR_DACEN_Pos (29U) 11228 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) 11229 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk 11230 #define RCC_APB1ENR_UART7EN_Pos (30U) 11231 #define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) 11232 #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk 11233 #define RCC_APB1ENR_UART8EN_Pos (31U) 11234 #define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) 11235 #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk 11238 #define RCC_APB2ENR_TIM1EN_Pos (0U) 11239 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) 11240 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk 11241 #define RCC_APB2ENR_TIM8EN_Pos (1U) 11242 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) 11243 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk 11244 #define RCC_APB2ENR_USART1EN_Pos (4U) 11245 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) 11246 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk 11247 #define RCC_APB2ENR_USART6EN_Pos (5U) 11248 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) 11249 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk 11250 #define RCC_APB2ENR_SDMMC2EN_Pos (7U) 11251 #define RCC_APB2ENR_SDMMC2EN_Msk (0x1U << RCC_APB2ENR_SDMMC2EN_Pos) 11252 #define RCC_APB2ENR_SDMMC2EN RCC_APB2ENR_SDMMC2EN_Msk 11253 #define RCC_APB2ENR_ADC1EN_Pos (8U) 11254 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) 11255 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk 11256 #define RCC_APB2ENR_ADC2EN_Pos (9U) 11257 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) 11258 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk 11259 #define RCC_APB2ENR_ADC3EN_Pos (10U) 11260 #define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) 11261 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk 11262 #define RCC_APB2ENR_SDMMC1EN_Pos (11U) 11263 #define RCC_APB2ENR_SDMMC1EN_Msk (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) 11264 #define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk 11265 #define RCC_APB2ENR_SPI1EN_Pos (12U) 11266 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) 11267 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk 11268 #define RCC_APB2ENR_SPI4EN_Pos (13U) 11269 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) 11270 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk 11271 #define RCC_APB2ENR_SYSCFGEN_Pos (14U) 11272 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) 11273 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk 11274 #define RCC_APB2ENR_TIM9EN_Pos (16U) 11275 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) 11276 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk 11277 #define RCC_APB2ENR_TIM10EN_Pos (17U) 11278 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) 11279 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk 11280 #define RCC_APB2ENR_TIM11EN_Pos (18U) 11281 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) 11282 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk 11283 #define RCC_APB2ENR_SPI5EN_Pos (20U) 11284 #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) 11285 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk 11286 #define RCC_APB2ENR_SPI6EN_Pos (21U) 11287 #define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) 11288 #define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk 11289 #define RCC_APB2ENR_SAI1EN_Pos (22U) 11290 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) 11291 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk 11292 #define RCC_APB2ENR_SAI2EN_Pos (23U) 11293 #define RCC_APB2ENR_SAI2EN_Msk (0x1U << RCC_APB2ENR_SAI2EN_Pos) 11294 #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk 11295 #define RCC_APB2ENR_LTDCEN_Pos (26U) 11296 #define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) 11297 #define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk 11298 #define RCC_APB2ENR_DSIEN_Pos (27U) 11299 #define RCC_APB2ENR_DSIEN_Msk (0x1U << RCC_APB2ENR_DSIEN_Pos) 11300 #define RCC_APB2ENR_DSIEN RCC_APB2ENR_DSIEN_Msk 11301 #define RCC_APB2ENR_DFSDM1EN_Pos (29U) 11302 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) 11303 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk 11304 #define RCC_APB2ENR_MDIOEN_Pos (30U) 11305 #define RCC_APB2ENR_MDIOEN_Msk (0x1U << RCC_APB2ENR_MDIOEN_Pos) 11306 #define RCC_APB2ENR_MDIOEN RCC_APB2ENR_MDIOEN_Msk 11309 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U) 11310 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) 11311 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk 11312 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U) 11313 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) 11314 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk 11315 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U) 11316 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) 11317 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk 11318 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U) 11319 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) 11320 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk 11321 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U) 11322 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) 11323 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk 11324 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U) 11325 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) 11326 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk 11327 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U) 11328 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) 11329 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk 11330 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U) 11331 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) 11332 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk 11333 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U) 11334 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) 11335 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk 11336 #define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U) 11337 #define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) 11338 #define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk 11339 #define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U) 11340 #define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) 11341 #define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk 11342 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U) 11343 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) 11344 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk 11345 #define RCC_AHB1LPENR_AXILPEN_Pos (13U) 11346 #define RCC_AHB1LPENR_AXILPEN_Msk (0x1U << RCC_AHB1LPENR_AXILPEN_Pos) 11347 #define RCC_AHB1LPENR_AXILPEN RCC_AHB1LPENR_AXILPEN_Msk 11348 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U) 11349 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) 11350 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk 11351 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U) 11352 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) 11353 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk 11354 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U) 11355 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) 11356 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk 11357 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U) 11358 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) 11359 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk 11360 #define RCC_AHB1LPENR_DTCMLPEN_Pos (20U) 11361 #define RCC_AHB1LPENR_DTCMLPEN_Msk (0x1U << RCC_AHB1LPENR_DTCMLPEN_Pos) 11362 #define RCC_AHB1LPENR_DTCMLPEN RCC_AHB1LPENR_DTCMLPEN_Msk 11363 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U) 11364 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) 11365 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk 11366 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U) 11367 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) 11368 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk 11369 #define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U) 11370 #define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) 11371 #define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk 11372 #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U) 11373 #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) 11374 #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk 11375 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U) 11376 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) 11377 #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk 11378 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U) 11379 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) 11380 #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk 11381 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U) 11382 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) 11383 #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk 11384 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U) 11385 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) 11386 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk 11387 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U) 11388 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) 11389 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk 11392 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U) 11393 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) 11394 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk 11395 #define RCC_AHB2LPENR_JPEGLPEN_Pos (1U) 11396 #define RCC_AHB2LPENR_JPEGLPEN_Msk (0x1U << RCC_AHB2LPENR_JPEGLPEN_Pos) 11397 #define RCC_AHB2LPENR_JPEGLPEN RCC_AHB2LPENR_JPEGLPEN_Msk 11398 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U) 11399 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) 11400 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk 11401 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U) 11402 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) 11403 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk 11406 #define RCC_AHB3LPENR_FMCLPEN_Pos (0U) 11407 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) 11408 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk 11409 #define RCC_AHB3LPENR_QSPILPEN_Pos (1U) 11410 #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) 11411 #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk 11413 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U) 11414 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) 11415 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk 11416 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U) 11417 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) 11418 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk 11419 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U) 11420 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) 11421 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk 11422 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U) 11423 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) 11424 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk 11425 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U) 11426 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) 11427 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk 11428 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U) 11429 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) 11430 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk 11431 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U) 11432 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) 11433 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk 11434 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U) 11435 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) 11436 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk 11437 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U) 11438 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) 11439 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk 11440 #define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U) 11441 #define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1U << RCC_APB1LPENR_LPTIM1LPEN_Pos) 11442 #define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk 11443 #define RCC_APB1LPENR_RTCLPEN_Pos (10U) 11444 #define RCC_APB1LPENR_RTCLPEN_Msk (0x1U << RCC_APB1LPENR_RTCLPEN_Pos) 11445 #define RCC_APB1LPENR_RTCLPEN RCC_APB1LPENR_RTCLPEN_Msk 11446 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U) 11447 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) 11448 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk 11449 #define RCC_APB1LPENR_CAN3LPEN_Pos (13U) 11450 #define RCC_APB1LPENR_CAN3LPEN_Msk (0x1U << RCC_APB1LPENR_CAN3LPEN_Pos) 11451 #define RCC_APB1LPENR_CAN3LPEN RCC_APB1LPENR_CAN3LPEN_Msk 11452 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U) 11453 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) 11454 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk 11455 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U) 11456 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) 11457 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk 11458 #define RCC_APB1LPENR_SPDIFRXLPEN_Pos (16U) 11459 #define RCC_APB1LPENR_SPDIFRXLPEN_Msk (0x1U << RCC_APB1LPENR_SPDIFRXLPEN_Pos) 11460 #define RCC_APB1LPENR_SPDIFRXLPEN RCC_APB1LPENR_SPDIFRXLPEN_Msk 11461 #define RCC_APB1LPENR_USART2LPEN_Pos (17U) 11462 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) 11463 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk 11464 #define RCC_APB1LPENR_USART3LPEN_Pos (18U) 11465 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) 11466 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk 11467 #define RCC_APB1LPENR_UART4LPEN_Pos (19U) 11468 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) 11469 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk 11470 #define RCC_APB1LPENR_UART5LPEN_Pos (20U) 11471 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) 11472 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk 11473 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U) 11474 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) 11475 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk 11476 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U) 11477 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) 11478 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk 11479 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U) 11480 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) 11481 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk 11482 #define RCC_APB1LPENR_I2C4LPEN_Pos (24U) 11483 #define RCC_APB1LPENR_I2C4LPEN_Msk (0x1U << RCC_APB1LPENR_I2C4LPEN_Pos) 11484 #define RCC_APB1LPENR_I2C4LPEN RCC_APB1LPENR_I2C4LPEN_Msk 11485 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U) 11486 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) 11487 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk 11488 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U) 11489 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) 11490 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk 11491 #define RCC_APB1LPENR_CECLPEN_Pos (27U) 11492 #define RCC_APB1LPENR_CECLPEN_Msk (0x1U << RCC_APB1LPENR_CECLPEN_Pos) 11493 #define RCC_APB1LPENR_CECLPEN RCC_APB1LPENR_CECLPEN_Msk 11494 #define RCC_APB1LPENR_PWRLPEN_Pos (28U) 11495 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) 11496 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk 11497 #define RCC_APB1LPENR_DACLPEN_Pos (29U) 11498 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) 11499 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk 11500 #define RCC_APB1LPENR_UART7LPEN_Pos (30U) 11501 #define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) 11502 #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk 11503 #define RCC_APB1LPENR_UART8LPEN_Pos (31U) 11504 #define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) 11505 #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk 11508 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U) 11509 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) 11510 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk 11511 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U) 11512 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) 11513 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk 11514 #define RCC_APB2LPENR_USART1LPEN_Pos (4U) 11515 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) 11516 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk 11517 #define RCC_APB2LPENR_USART6LPEN_Pos (5U) 11518 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) 11519 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk 11520 #define RCC_APB2LPENR_SDMMC2LPEN_Pos (7U) 11521 #define RCC_APB2LPENR_SDMMC2LPEN_Msk (0x1U << RCC_APB2LPENR_SDMMC2LPEN_Pos) 11522 #define RCC_APB2LPENR_SDMMC2LPEN RCC_APB2LPENR_SDMMC2LPEN_Msk 11523 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U) 11524 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) 11525 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk 11526 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U) 11527 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) 11528 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk 11529 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U) 11530 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) 11531 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk 11532 #define RCC_APB2LPENR_SDMMC1LPEN_Pos (11U) 11533 #define RCC_APB2LPENR_SDMMC1LPEN_Msk (0x1U << RCC_APB2LPENR_SDMMC1LPEN_Pos) 11534 #define RCC_APB2LPENR_SDMMC1LPEN RCC_APB2LPENR_SDMMC1LPEN_Msk 11535 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U) 11536 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) 11537 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk 11538 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U) 11539 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) 11540 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk 11541 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U) 11542 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) 11543 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk 11544 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U) 11545 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) 11546 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk 11547 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U) 11548 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) 11549 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk 11550 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U) 11551 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) 11552 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk 11553 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U) 11554 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) 11555 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk 11556 #define RCC_APB2LPENR_SPI6LPEN_Pos (21U) 11557 #define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) 11558 #define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk 11559 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U) 11560 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) 11561 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk 11562 #define RCC_APB2LPENR_SAI2LPEN_Pos (23U) 11563 #define RCC_APB2LPENR_SAI2LPEN_Msk (0x1U << RCC_APB2LPENR_SAI2LPEN_Pos) 11564 #define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk 11565 #define RCC_APB2LPENR_LTDCLPEN_Pos (26U) 11566 #define RCC_APB2LPENR_LTDCLPEN_Msk (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) 11567 #define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk 11568 #define RCC_APB2LPENR_DSILPEN_Pos (27U) 11569 #define RCC_APB2LPENR_DSILPEN_Msk (0x1U << RCC_APB2LPENR_DSILPEN_Pos) 11570 #define RCC_APB2LPENR_DSILPEN RCC_APB2LPENR_DSILPEN_Msk 11571 #define RCC_APB2LPENR_DFSDM1LPEN_Pos (29U) 11572 #define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1U << RCC_APB2LPENR_DFSDM1LPEN_Pos) 11573 #define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk 11574 #define RCC_APB2LPENR_MDIOLPEN_Pos (30U) 11575 #define RCC_APB2LPENR_MDIOLPEN_Msk (0x1U << RCC_APB2LPENR_MDIOLPEN_Pos) 11576 #define RCC_APB2LPENR_MDIOLPEN RCC_APB2LPENR_MDIOLPEN_Msk 11579 #define RCC_BDCR_LSEON_Pos (0U) 11580 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) 11581 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk 11582 #define RCC_BDCR_LSERDY_Pos (1U) 11583 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) 11584 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk 11585 #define RCC_BDCR_LSEBYP_Pos (2U) 11586 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) 11587 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk 11588 #define RCC_BDCR_LSEDRV_Pos (3U) 11589 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) 11590 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk 11591 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) 11592 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) 11593 #define RCC_BDCR_RTCSEL_Pos (8U) 11594 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) 11595 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk 11596 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) 11597 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) 11598 #define RCC_BDCR_RTCEN_Pos (15U) 11599 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) 11600 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk 11601 #define RCC_BDCR_BDRST_Pos (16U) 11602 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) 11603 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk 11606 #define RCC_CSR_LSION_Pos (0U) 11607 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) 11608 #define RCC_CSR_LSION RCC_CSR_LSION_Msk 11609 #define RCC_CSR_LSIRDY_Pos (1U) 11610 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) 11611 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk 11612 #define RCC_CSR_RMVF_Pos (24U) 11613 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) 11614 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk 11615 #define RCC_CSR_BORRSTF_Pos (25U) 11616 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) 11617 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk 11618 #define RCC_CSR_PINRSTF_Pos (26U) 11619 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) 11620 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk 11621 #define RCC_CSR_PORRSTF_Pos (27U) 11622 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) 11623 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk 11624 #define RCC_CSR_SFTRSTF_Pos (28U) 11625 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) 11626 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk 11627 #define RCC_CSR_IWDGRSTF_Pos (29U) 11628 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) 11629 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk 11630 #define RCC_CSR_WWDGRSTF_Pos (30U) 11631 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) 11632 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk 11633 #define RCC_CSR_LPWRRSTF_Pos (31U) 11634 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) 11635 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk 11638 #define RCC_SSCGR_MODPER_Pos (0U) 11639 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) 11640 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk 11641 #define RCC_SSCGR_INCSTEP_Pos (13U) 11642 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) 11643 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk 11644 #define RCC_SSCGR_SPREADSEL_Pos (30U) 11645 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) 11646 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk 11647 #define RCC_SSCGR_SSCGEN_Pos (31U) 11648 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) 11649 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk 11652 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U) 11653 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) 11654 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk 11655 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) 11656 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) 11657 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) 11658 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) 11659 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) 11660 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) 11661 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) 11662 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) 11663 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) 11664 #define RCC_PLLI2SCFGR_PLLI2SP_Pos (16U) 11665 #define RCC_PLLI2SCFGR_PLLI2SP_Msk (0x3U << RCC_PLLI2SCFGR_PLLI2SP_Pos) 11666 #define RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP_Msk 11667 #define RCC_PLLI2SCFGR_PLLI2SP_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SP_Pos) 11668 #define RCC_PLLI2SCFGR_PLLI2SP_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SP_Pos) 11669 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U) 11670 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) 11671 #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk 11672 #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) 11673 #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) 11674 #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) 11675 #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) 11676 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U) 11677 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) 11678 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk 11679 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) 11680 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) 11681 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) 11684 #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U) 11685 #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) 11686 #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk 11687 #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) 11688 #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) 11689 #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) 11690 #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) 11691 #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) 11692 #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) 11693 #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) 11694 #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) 11695 #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) 11696 #define RCC_PLLSAICFGR_PLLSAIP_Pos (16U) 11697 #define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3U << RCC_PLLSAICFGR_PLLSAIP_Pos) 11698 #define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk 11699 #define RCC_PLLSAICFGR_PLLSAIP_0 (0x1U << RCC_PLLSAICFGR_PLLSAIP_Pos) 11700 #define RCC_PLLSAICFGR_PLLSAIP_1 (0x2U << RCC_PLLSAICFGR_PLLSAIP_Pos) 11701 #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U) 11702 #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) 11703 #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk 11704 #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) 11705 #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) 11706 #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) 11707 #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) 11708 #define RCC_PLLSAICFGR_PLLSAIR_Pos (28U) 11709 #define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) 11710 #define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk 11711 #define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) 11712 #define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) 11713 #define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) 11716 #define RCC_DCKCFGR1_PLLI2SDIVQ_Pos (0U) 11717 #define RCC_DCKCFGR1_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) 11718 #define RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ_Msk 11719 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) 11720 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) 11721 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) 11722 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) 11723 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) 11725 #define RCC_DCKCFGR1_PLLSAIDIVQ_Pos (8U) 11726 #define RCC_DCKCFGR1_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) 11727 #define RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ_Msk 11728 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) 11729 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) 11730 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) 11731 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) 11732 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) 11734 #define RCC_DCKCFGR1_PLLSAIDIVR_Pos (16U) 11735 #define RCC_DCKCFGR1_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR1_PLLSAIDIVR_Pos) 11736 #define RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR_Msk 11737 #define RCC_DCKCFGR1_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR1_PLLSAIDIVR_Pos) 11738 #define RCC_DCKCFGR1_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR1_PLLSAIDIVR_Pos) 11743 #define RCC_SAI1SEL_PLLSRC_SUPPORT 11744 #define RCC_DCKCFGR1_SAI1SEL_Pos (20U) 11745 #define RCC_DCKCFGR1_SAI1SEL_Msk (0x3U << RCC_DCKCFGR1_SAI1SEL_Pos) 11746 #define RCC_DCKCFGR1_SAI1SEL RCC_DCKCFGR1_SAI1SEL_Msk 11747 #define RCC_DCKCFGR1_SAI1SEL_0 (0x1U << RCC_DCKCFGR1_SAI1SEL_Pos) 11748 #define RCC_DCKCFGR1_SAI1SEL_1 (0x2U << RCC_DCKCFGR1_SAI1SEL_Pos) 11753 #define RCC_SAI2SEL_PLLSRC_SUPPORT 11754 #define RCC_DCKCFGR1_SAI2SEL_Pos (22U) 11755 #define RCC_DCKCFGR1_SAI2SEL_Msk (0x3U << RCC_DCKCFGR1_SAI2SEL_Pos) 11756 #define RCC_DCKCFGR1_SAI2SEL RCC_DCKCFGR1_SAI2SEL_Msk 11757 #define RCC_DCKCFGR1_SAI2SEL_0 (0x1U << RCC_DCKCFGR1_SAI2SEL_Pos) 11758 #define RCC_DCKCFGR1_SAI2SEL_1 (0x2U << RCC_DCKCFGR1_SAI2SEL_Pos) 11760 #define RCC_DCKCFGR1_TIMPRE_Pos (24U) 11761 #define RCC_DCKCFGR1_TIMPRE_Msk (0x1U << RCC_DCKCFGR1_TIMPRE_Pos) 11762 #define RCC_DCKCFGR1_TIMPRE RCC_DCKCFGR1_TIMPRE_Msk 11763 #define RCC_DCKCFGR1_DFSDM1SEL_Pos (25U) 11764 #define RCC_DCKCFGR1_DFSDM1SEL_Msk (0x1U << RCC_DCKCFGR1_DFSDM1SEL_Pos) 11765 #define RCC_DCKCFGR1_DFSDM1SEL RCC_DCKCFGR1_DFSDM1SEL_Msk 11766 #define RCC_DCKCFGR1_ADFSDM1SEL_Pos (26U) 11767 #define RCC_DCKCFGR1_ADFSDM1SEL_Msk (0x1U << RCC_DCKCFGR1_ADFSDM1SEL_Pos) 11768 #define RCC_DCKCFGR1_ADFSDM1SEL RCC_DCKCFGR1_ADFSDM1SEL_Msk 11771 #define RCC_DCKCFGR2_USART1SEL_Pos (0U) 11772 #define RCC_DCKCFGR2_USART1SEL_Msk (0x3U << RCC_DCKCFGR2_USART1SEL_Pos) 11773 #define RCC_DCKCFGR2_USART1SEL RCC_DCKCFGR2_USART1SEL_Msk 11774 #define RCC_DCKCFGR2_USART1SEL_0 (0x1U << RCC_DCKCFGR2_USART1SEL_Pos) 11775 #define RCC_DCKCFGR2_USART1SEL_1 (0x2U << RCC_DCKCFGR2_USART1SEL_Pos) 11776 #define RCC_DCKCFGR2_USART2SEL_Pos (2U) 11777 #define RCC_DCKCFGR2_USART2SEL_Msk (0x3U << RCC_DCKCFGR2_USART2SEL_Pos) 11778 #define RCC_DCKCFGR2_USART2SEL RCC_DCKCFGR2_USART2SEL_Msk 11779 #define RCC_DCKCFGR2_USART2SEL_0 (0x1U << RCC_DCKCFGR2_USART2SEL_Pos) 11780 #define RCC_DCKCFGR2_USART2SEL_1 (0x2U << RCC_DCKCFGR2_USART2SEL_Pos) 11781 #define RCC_DCKCFGR2_USART3SEL_Pos (4U) 11782 #define RCC_DCKCFGR2_USART3SEL_Msk (0x3U << RCC_DCKCFGR2_USART3SEL_Pos) 11783 #define RCC_DCKCFGR2_USART3SEL RCC_DCKCFGR2_USART3SEL_Msk 11784 #define RCC_DCKCFGR2_USART3SEL_0 (0x1U << RCC_DCKCFGR2_USART3SEL_Pos) 11785 #define RCC_DCKCFGR2_USART3SEL_1 (0x2U << RCC_DCKCFGR2_USART3SEL_Pos) 11786 #define RCC_DCKCFGR2_UART4SEL_Pos (6U) 11787 #define RCC_DCKCFGR2_UART4SEL_Msk (0x3U << RCC_DCKCFGR2_UART4SEL_Pos) 11788 #define RCC_DCKCFGR2_UART4SEL RCC_DCKCFGR2_UART4SEL_Msk 11789 #define RCC_DCKCFGR2_UART4SEL_0 (0x1U << RCC_DCKCFGR2_UART4SEL_Pos) 11790 #define RCC_DCKCFGR2_UART4SEL_1 (0x2U << RCC_DCKCFGR2_UART4SEL_Pos) 11791 #define RCC_DCKCFGR2_UART5SEL_Pos (8U) 11792 #define RCC_DCKCFGR2_UART5SEL_Msk (0x3U << RCC_DCKCFGR2_UART5SEL_Pos) 11793 #define RCC_DCKCFGR2_UART5SEL RCC_DCKCFGR2_UART5SEL_Msk 11794 #define RCC_DCKCFGR2_UART5SEL_0 (0x1U << RCC_DCKCFGR2_UART5SEL_Pos) 11795 #define RCC_DCKCFGR2_UART5SEL_1 (0x2U << RCC_DCKCFGR2_UART5SEL_Pos) 11796 #define RCC_DCKCFGR2_USART6SEL_Pos (10U) 11797 #define RCC_DCKCFGR2_USART6SEL_Msk (0x3U << RCC_DCKCFGR2_USART6SEL_Pos) 11798 #define RCC_DCKCFGR2_USART6SEL RCC_DCKCFGR2_USART6SEL_Msk 11799 #define RCC_DCKCFGR2_USART6SEL_0 (0x1U << RCC_DCKCFGR2_USART6SEL_Pos) 11800 #define RCC_DCKCFGR2_USART6SEL_1 (0x2U << RCC_DCKCFGR2_USART6SEL_Pos) 11801 #define RCC_DCKCFGR2_UART7SEL_Pos (12U) 11802 #define RCC_DCKCFGR2_UART7SEL_Msk (0x3U << RCC_DCKCFGR2_UART7SEL_Pos) 11803 #define RCC_DCKCFGR2_UART7SEL RCC_DCKCFGR2_UART7SEL_Msk 11804 #define RCC_DCKCFGR2_UART7SEL_0 (0x1U << RCC_DCKCFGR2_UART7SEL_Pos) 11805 #define RCC_DCKCFGR2_UART7SEL_1 (0x2U << RCC_DCKCFGR2_UART7SEL_Pos) 11806 #define RCC_DCKCFGR2_UART8SEL_Pos (14U) 11807 #define RCC_DCKCFGR2_UART8SEL_Msk (0x3U << RCC_DCKCFGR2_UART8SEL_Pos) 11808 #define RCC_DCKCFGR2_UART8SEL RCC_DCKCFGR2_UART8SEL_Msk 11809 #define RCC_DCKCFGR2_UART8SEL_0 (0x1U << RCC_DCKCFGR2_UART8SEL_Pos) 11810 #define RCC_DCKCFGR2_UART8SEL_1 (0x2U << RCC_DCKCFGR2_UART8SEL_Pos) 11811 #define RCC_DCKCFGR2_I2C1SEL_Pos (16U) 11812 #define RCC_DCKCFGR2_I2C1SEL_Msk (0x3U << RCC_DCKCFGR2_I2C1SEL_Pos) 11813 #define RCC_DCKCFGR2_I2C1SEL RCC_DCKCFGR2_I2C1SEL_Msk 11814 #define RCC_DCKCFGR2_I2C1SEL_0 (0x1U << RCC_DCKCFGR2_I2C1SEL_Pos) 11815 #define RCC_DCKCFGR2_I2C1SEL_1 (0x2U << RCC_DCKCFGR2_I2C1SEL_Pos) 11816 #define RCC_DCKCFGR2_I2C2SEL_Pos (18U) 11817 #define RCC_DCKCFGR2_I2C2SEL_Msk (0x3U << RCC_DCKCFGR2_I2C2SEL_Pos) 11818 #define RCC_DCKCFGR2_I2C2SEL RCC_DCKCFGR2_I2C2SEL_Msk 11819 #define RCC_DCKCFGR2_I2C2SEL_0 (0x1U << RCC_DCKCFGR2_I2C2SEL_Pos) 11820 #define RCC_DCKCFGR2_I2C2SEL_1 (0x2U << RCC_DCKCFGR2_I2C2SEL_Pos) 11821 #define RCC_DCKCFGR2_I2C3SEL_Pos (20U) 11822 #define RCC_DCKCFGR2_I2C3SEL_Msk (0x3U << RCC_DCKCFGR2_I2C3SEL_Pos) 11823 #define RCC_DCKCFGR2_I2C3SEL RCC_DCKCFGR2_I2C3SEL_Msk 11824 #define RCC_DCKCFGR2_I2C3SEL_0 (0x1U << RCC_DCKCFGR2_I2C3SEL_Pos) 11825 #define RCC_DCKCFGR2_I2C3SEL_1 (0x2U << RCC_DCKCFGR2_I2C3SEL_Pos) 11826 #define RCC_DCKCFGR2_I2C4SEL_Pos (22U) 11827 #define RCC_DCKCFGR2_I2C4SEL_Msk (0x3U << RCC_DCKCFGR2_I2C4SEL_Pos) 11828 #define RCC_DCKCFGR2_I2C4SEL RCC_DCKCFGR2_I2C4SEL_Msk 11829 #define RCC_DCKCFGR2_I2C4SEL_0 (0x1U << RCC_DCKCFGR2_I2C4SEL_Pos) 11830 #define RCC_DCKCFGR2_I2C4SEL_1 (0x2U << RCC_DCKCFGR2_I2C4SEL_Pos) 11831 #define RCC_DCKCFGR2_LPTIM1SEL_Pos (24U) 11832 #define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3U << RCC_DCKCFGR2_LPTIM1SEL_Pos) 11833 #define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk 11834 #define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1U << RCC_DCKCFGR2_LPTIM1SEL_Pos) 11835 #define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2U << RCC_DCKCFGR2_LPTIM1SEL_Pos) 11836 #define RCC_DCKCFGR2_CECSEL_Pos (26U) 11837 #define RCC_DCKCFGR2_CECSEL_Msk (0x1U << RCC_DCKCFGR2_CECSEL_Pos) 11838 #define RCC_DCKCFGR2_CECSEL RCC_DCKCFGR2_CECSEL_Msk 11839 #define RCC_DCKCFGR2_CK48MSEL_Pos (27U) 11840 #define RCC_DCKCFGR2_CK48MSEL_Msk (0x1U << RCC_DCKCFGR2_CK48MSEL_Pos) 11841 #define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk 11842 #define RCC_DCKCFGR2_SDMMC1SEL_Pos (28U) 11843 #define RCC_DCKCFGR2_SDMMC1SEL_Msk (0x1U << RCC_DCKCFGR2_SDMMC1SEL_Pos) 11844 #define RCC_DCKCFGR2_SDMMC1SEL RCC_DCKCFGR2_SDMMC1SEL_Msk 11845 #define RCC_DCKCFGR2_SDMMC2SEL_Pos (29U) 11846 #define RCC_DCKCFGR2_SDMMC2SEL_Msk (0x1U << RCC_DCKCFGR2_SDMMC2SEL_Pos) 11847 #define RCC_DCKCFGR2_SDMMC2SEL RCC_DCKCFGR2_SDMMC2SEL_Msk 11848 #define RCC_DCKCFGR2_DSISEL_Pos (30U) 11849 #define RCC_DCKCFGR2_DSISEL_Msk (0x1U << RCC_DCKCFGR2_DSISEL_Pos) 11850 #define RCC_DCKCFGR2_DSISEL RCC_DCKCFGR2_DSISEL_Msk 11858 #define RNG_CR_RNGEN_Pos (2U) 11859 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) 11860 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk 11861 #define RNG_CR_IE_Pos (3U) 11862 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) 11863 #define RNG_CR_IE RNG_CR_IE_Msk 11866 #define RNG_SR_DRDY_Pos (0U) 11867 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) 11868 #define RNG_SR_DRDY RNG_SR_DRDY_Msk 11869 #define RNG_SR_CECS_Pos (1U) 11870 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) 11871 #define RNG_SR_CECS RNG_SR_CECS_Msk 11872 #define RNG_SR_SECS_Pos (2U) 11873 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) 11874 #define RNG_SR_SECS RNG_SR_SECS_Msk 11875 #define RNG_SR_CEIS_Pos (5U) 11876 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) 11877 #define RNG_SR_CEIS RNG_SR_CEIS_Msk 11878 #define RNG_SR_SEIS_Pos (6U) 11879 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) 11880 #define RNG_SR_SEIS RNG_SR_SEIS_Msk 11888 #define RTC_TR_PM_Pos (22U) 11889 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) 11890 #define RTC_TR_PM RTC_TR_PM_Msk 11891 #define RTC_TR_HT_Pos (20U) 11892 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) 11893 #define RTC_TR_HT RTC_TR_HT_Msk 11894 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) 11895 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) 11896 #define RTC_TR_HU_Pos (16U) 11897 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) 11898 #define RTC_TR_HU RTC_TR_HU_Msk 11899 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) 11900 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) 11901 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) 11902 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) 11903 #define RTC_TR_MNT_Pos (12U) 11904 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) 11905 #define RTC_TR_MNT RTC_TR_MNT_Msk 11906 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) 11907 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) 11908 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) 11909 #define RTC_TR_MNU_Pos (8U) 11910 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) 11911 #define RTC_TR_MNU RTC_TR_MNU_Msk 11912 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) 11913 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) 11914 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) 11915 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) 11916 #define RTC_TR_ST_Pos (4U) 11917 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) 11918 #define RTC_TR_ST RTC_TR_ST_Msk 11919 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) 11920 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) 11921 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) 11922 #define RTC_TR_SU_Pos (0U) 11923 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) 11924 #define RTC_TR_SU RTC_TR_SU_Msk 11925 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) 11926 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) 11927 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) 11928 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) 11931 #define RTC_DR_YT_Pos (20U) 11932 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) 11933 #define RTC_DR_YT RTC_DR_YT_Msk 11934 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) 11935 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) 11936 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) 11937 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) 11938 #define RTC_DR_YU_Pos (16U) 11939 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) 11940 #define RTC_DR_YU RTC_DR_YU_Msk 11941 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) 11942 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) 11943 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) 11944 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) 11945 #define RTC_DR_WDU_Pos (13U) 11946 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) 11947 #define RTC_DR_WDU RTC_DR_WDU_Msk 11948 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) 11949 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) 11950 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) 11951 #define RTC_DR_MT_Pos (12U) 11952 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) 11953 #define RTC_DR_MT RTC_DR_MT_Msk 11954 #define RTC_DR_MU_Pos (8U) 11955 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) 11956 #define RTC_DR_MU RTC_DR_MU_Msk 11957 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) 11958 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) 11959 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) 11960 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) 11961 #define RTC_DR_DT_Pos (4U) 11962 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) 11963 #define RTC_DR_DT RTC_DR_DT_Msk 11964 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) 11965 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) 11966 #define RTC_DR_DU_Pos (0U) 11967 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) 11968 #define RTC_DR_DU RTC_DR_DU_Msk 11969 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) 11970 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) 11971 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) 11972 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) 11975 #define RTC_CR_ITSE_Pos (24U) 11976 #define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) 11977 #define RTC_CR_ITSE RTC_CR_ITSE_Msk 11978 #define RTC_CR_COE_Pos (23U) 11979 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) 11980 #define RTC_CR_COE RTC_CR_COE_Msk 11981 #define RTC_CR_OSEL_Pos (21U) 11982 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) 11983 #define RTC_CR_OSEL RTC_CR_OSEL_Msk 11984 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) 11985 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) 11986 #define RTC_CR_POL_Pos (20U) 11987 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) 11988 #define RTC_CR_POL RTC_CR_POL_Msk 11989 #define RTC_CR_COSEL_Pos (19U) 11990 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) 11991 #define RTC_CR_COSEL RTC_CR_COSEL_Msk 11992 #define RTC_CR_BKP_Pos (18U) 11993 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) 11994 #define RTC_CR_BKP RTC_CR_BKP_Msk 11995 #define RTC_CR_SUB1H_Pos (17U) 11996 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) 11997 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk 11998 #define RTC_CR_ADD1H_Pos (16U) 11999 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) 12000 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk 12001 #define RTC_CR_TSIE_Pos (15U) 12002 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) 12003 #define RTC_CR_TSIE RTC_CR_TSIE_Msk 12004 #define RTC_CR_WUTIE_Pos (14U) 12005 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) 12006 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk 12007 #define RTC_CR_ALRBIE_Pos (13U) 12008 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) 12009 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk 12010 #define RTC_CR_ALRAIE_Pos (12U) 12011 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) 12012 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk 12013 #define RTC_CR_TSE_Pos (11U) 12014 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) 12015 #define RTC_CR_TSE RTC_CR_TSE_Msk 12016 #define RTC_CR_WUTE_Pos (10U) 12017 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) 12018 #define RTC_CR_WUTE RTC_CR_WUTE_Msk 12019 #define RTC_CR_ALRBE_Pos (9U) 12020 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) 12021 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk 12022 #define RTC_CR_ALRAE_Pos (8U) 12023 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) 12024 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk 12025 #define RTC_CR_FMT_Pos (6U) 12026 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) 12027 #define RTC_CR_FMT RTC_CR_FMT_Msk 12028 #define RTC_CR_BYPSHAD_Pos (5U) 12029 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) 12030 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk 12031 #define RTC_CR_REFCKON_Pos (4U) 12032 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) 12033 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk 12034 #define RTC_CR_TSEDGE_Pos (3U) 12035 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) 12036 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk 12037 #define RTC_CR_WUCKSEL_Pos (0U) 12038 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) 12039 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk 12040 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) 12041 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) 12042 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) 12045 #define RTC_CR_BCK RTC_CR_BKP 12048 #define RTC_ISR_ITSF_Pos (17U) 12049 #define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) 12050 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk 12051 #define RTC_ISR_RECALPF_Pos (16U) 12052 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) 12053 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk 12054 #define RTC_ISR_TAMP3F_Pos (15U) 12055 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) 12056 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk 12057 #define RTC_ISR_TAMP2F_Pos (14U) 12058 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) 12059 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk 12060 #define RTC_ISR_TAMP1F_Pos (13U) 12061 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) 12062 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk 12063 #define RTC_ISR_TSOVF_Pos (12U) 12064 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) 12065 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk 12066 #define RTC_ISR_TSF_Pos (11U) 12067 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) 12068 #define RTC_ISR_TSF RTC_ISR_TSF_Msk 12069 #define RTC_ISR_WUTF_Pos (10U) 12070 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) 12071 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk 12072 #define RTC_ISR_ALRBF_Pos (9U) 12073 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) 12074 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk 12075 #define RTC_ISR_ALRAF_Pos (8U) 12076 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) 12077 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk 12078 #define RTC_ISR_INIT_Pos (7U) 12079 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) 12080 #define RTC_ISR_INIT RTC_ISR_INIT_Msk 12081 #define RTC_ISR_INITF_Pos (6U) 12082 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) 12083 #define RTC_ISR_INITF RTC_ISR_INITF_Msk 12084 #define RTC_ISR_RSF_Pos (5U) 12085 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) 12086 #define RTC_ISR_RSF RTC_ISR_RSF_Msk 12087 #define RTC_ISR_INITS_Pos (4U) 12088 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) 12089 #define RTC_ISR_INITS RTC_ISR_INITS_Msk 12090 #define RTC_ISR_SHPF_Pos (3U) 12091 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) 12092 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk 12093 #define RTC_ISR_WUTWF_Pos (2U) 12094 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) 12095 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk 12096 #define RTC_ISR_ALRBWF_Pos (1U) 12097 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) 12098 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk 12099 #define RTC_ISR_ALRAWF_Pos (0U) 12100 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) 12101 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk 12104 #define RTC_PRER_PREDIV_A_Pos (16U) 12105 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) 12106 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk 12107 #define RTC_PRER_PREDIV_S_Pos (0U) 12108 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) 12109 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk 12112 #define RTC_WUTR_WUT_Pos (0U) 12113 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) 12114 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk 12117 #define RTC_ALRMAR_MSK4_Pos (31U) 12118 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) 12119 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk 12120 #define RTC_ALRMAR_WDSEL_Pos (30U) 12121 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) 12122 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk 12123 #define RTC_ALRMAR_DT_Pos (28U) 12124 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) 12125 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk 12126 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) 12127 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) 12128 #define RTC_ALRMAR_DU_Pos (24U) 12129 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) 12130 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk 12131 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) 12132 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) 12133 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) 12134 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) 12135 #define RTC_ALRMAR_MSK3_Pos (23U) 12136 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) 12137 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk 12138 #define RTC_ALRMAR_PM_Pos (22U) 12139 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) 12140 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk 12141 #define RTC_ALRMAR_HT_Pos (20U) 12142 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) 12143 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk 12144 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) 12145 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) 12146 #define RTC_ALRMAR_HU_Pos (16U) 12147 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) 12148 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk 12149 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) 12150 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) 12151 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) 12152 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) 12153 #define RTC_ALRMAR_MSK2_Pos (15U) 12154 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) 12155 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk 12156 #define RTC_ALRMAR_MNT_Pos (12U) 12157 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) 12158 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk 12159 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) 12160 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) 12161 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) 12162 #define RTC_ALRMAR_MNU_Pos (8U) 12163 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) 12164 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk 12165 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) 12166 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) 12167 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) 12168 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) 12169 #define RTC_ALRMAR_MSK1_Pos (7U) 12170 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) 12171 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk 12172 #define RTC_ALRMAR_ST_Pos (4U) 12173 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) 12174 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk 12175 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) 12176 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) 12177 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) 12178 #define RTC_ALRMAR_SU_Pos (0U) 12179 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) 12180 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk 12181 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) 12182 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) 12183 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) 12184 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) 12187 #define RTC_ALRMBR_MSK4_Pos (31U) 12188 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) 12189 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk 12190 #define RTC_ALRMBR_WDSEL_Pos (30U) 12191 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) 12192 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk 12193 #define RTC_ALRMBR_DT_Pos (28U) 12194 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) 12195 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk 12196 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) 12197 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) 12198 #define RTC_ALRMBR_DU_Pos (24U) 12199 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) 12200 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk 12201 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) 12202 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) 12203 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) 12204 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) 12205 #define RTC_ALRMBR_MSK3_Pos (23U) 12206 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) 12207 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk 12208 #define RTC_ALRMBR_PM_Pos (22U) 12209 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) 12210 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk 12211 #define RTC_ALRMBR_HT_Pos (20U) 12212 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) 12213 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk 12214 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) 12215 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) 12216 #define RTC_ALRMBR_HU_Pos (16U) 12217 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) 12218 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk 12219 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) 12220 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) 12221 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) 12222 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) 12223 #define RTC_ALRMBR_MSK2_Pos (15U) 12224 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) 12225 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk 12226 #define RTC_ALRMBR_MNT_Pos (12U) 12227 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) 12228 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk 12229 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) 12230 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) 12231 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) 12232 #define RTC_ALRMBR_MNU_Pos (8U) 12233 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) 12234 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk 12235 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) 12236 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) 12237 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) 12238 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) 12239 #define RTC_ALRMBR_MSK1_Pos (7U) 12240 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) 12241 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk 12242 #define RTC_ALRMBR_ST_Pos (4U) 12243 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) 12244 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk 12245 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) 12246 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) 12247 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) 12248 #define RTC_ALRMBR_SU_Pos (0U) 12249 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) 12250 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk 12251 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) 12252 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) 12253 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) 12254 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) 12257 #define RTC_WPR_KEY_Pos (0U) 12258 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) 12259 #define RTC_WPR_KEY RTC_WPR_KEY_Msk 12262 #define RTC_SSR_SS_Pos (0U) 12263 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) 12264 #define RTC_SSR_SS RTC_SSR_SS_Msk 12267 #define RTC_SHIFTR_SUBFS_Pos (0U) 12268 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) 12269 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk 12270 #define RTC_SHIFTR_ADD1S_Pos (31U) 12271 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) 12272 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk 12275 #define RTC_TSTR_PM_Pos (22U) 12276 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) 12277 #define RTC_TSTR_PM RTC_TSTR_PM_Msk 12278 #define RTC_TSTR_HT_Pos (20U) 12279 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) 12280 #define RTC_TSTR_HT RTC_TSTR_HT_Msk 12281 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) 12282 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) 12283 #define RTC_TSTR_HU_Pos (16U) 12284 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) 12285 #define RTC_TSTR_HU RTC_TSTR_HU_Msk 12286 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) 12287 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) 12288 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) 12289 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) 12290 #define RTC_TSTR_MNT_Pos (12U) 12291 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) 12292 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk 12293 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) 12294 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) 12295 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) 12296 #define RTC_TSTR_MNU_Pos (8U) 12297 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) 12298 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk 12299 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) 12300 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) 12301 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) 12302 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) 12303 #define RTC_TSTR_ST_Pos (4U) 12304 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) 12305 #define RTC_TSTR_ST RTC_TSTR_ST_Msk 12306 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) 12307 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) 12308 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) 12309 #define RTC_TSTR_SU_Pos (0U) 12310 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) 12311 #define RTC_TSTR_SU RTC_TSTR_SU_Msk 12312 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) 12313 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) 12314 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) 12315 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) 12318 #define RTC_TSDR_WDU_Pos (13U) 12319 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) 12320 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk 12321 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) 12322 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) 12323 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) 12324 #define RTC_TSDR_MT_Pos (12U) 12325 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) 12326 #define RTC_TSDR_MT RTC_TSDR_MT_Msk 12327 #define RTC_TSDR_MU_Pos (8U) 12328 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) 12329 #define RTC_TSDR_MU RTC_TSDR_MU_Msk 12330 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) 12331 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) 12332 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) 12333 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) 12334 #define RTC_TSDR_DT_Pos (4U) 12335 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) 12336 #define RTC_TSDR_DT RTC_TSDR_DT_Msk 12337 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) 12338 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) 12339 #define RTC_TSDR_DU_Pos (0U) 12340 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) 12341 #define RTC_TSDR_DU RTC_TSDR_DU_Msk 12342 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) 12343 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) 12344 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) 12345 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) 12348 #define RTC_TSSSR_SS_Pos (0U) 12349 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) 12350 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk 12353 #define RTC_CALR_CALP_Pos (15U) 12354 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) 12355 #define RTC_CALR_CALP RTC_CALR_CALP_Msk 12356 #define RTC_CALR_CALW8_Pos (14U) 12357 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) 12358 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk 12359 #define RTC_CALR_CALW16_Pos (13U) 12360 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) 12361 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk 12362 #define RTC_CALR_CALM_Pos (0U) 12363 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) 12364 #define RTC_CALR_CALM RTC_CALR_CALM_Msk 12365 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) 12366 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) 12367 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) 12368 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) 12369 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) 12370 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) 12371 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) 12372 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) 12373 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) 12376 #define RTC_TAMPCR_TAMP3MF_Pos (24U) 12377 #define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) 12378 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk 12379 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U) 12380 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) 12381 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk 12382 #define RTC_TAMPCR_TAMP3IE_Pos (22U) 12383 #define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) 12384 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk 12385 #define RTC_TAMPCR_TAMP2MF_Pos (21U) 12386 #define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) 12387 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk 12388 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U) 12389 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) 12390 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk 12391 #define RTC_TAMPCR_TAMP2IE_Pos (19U) 12392 #define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) 12393 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk 12394 #define RTC_TAMPCR_TAMP1MF_Pos (18U) 12395 #define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) 12396 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk 12397 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U) 12398 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) 12399 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk 12400 #define RTC_TAMPCR_TAMP1IE_Pos (16U) 12401 #define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) 12402 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk 12403 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U) 12404 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) 12405 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk 12406 #define RTC_TAMPCR_TAMPPRCH_Pos (13U) 12407 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) 12408 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk 12409 #define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) 12410 #define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) 12411 #define RTC_TAMPCR_TAMPFLT_Pos (11U) 12412 #define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) 12413 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk 12414 #define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) 12415 #define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) 12416 #define RTC_TAMPCR_TAMPFREQ_Pos (8U) 12417 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) 12418 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk 12419 #define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) 12420 #define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) 12421 #define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) 12422 #define RTC_TAMPCR_TAMPTS_Pos (7U) 12423 #define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) 12424 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk 12425 #define RTC_TAMPCR_TAMP3TRG_Pos (6U) 12426 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) 12427 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk 12428 #define RTC_TAMPCR_TAMP3E_Pos (5U) 12429 #define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) 12430 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk 12431 #define RTC_TAMPCR_TAMP2TRG_Pos (4U) 12432 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) 12433 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk 12434 #define RTC_TAMPCR_TAMP2E_Pos (3U) 12435 #define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) 12436 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk 12437 #define RTC_TAMPCR_TAMPIE_Pos (2U) 12438 #define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) 12439 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk 12440 #define RTC_TAMPCR_TAMP1TRG_Pos (1U) 12441 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) 12442 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk 12443 #define RTC_TAMPCR_TAMP1E_Pos (0U) 12444 #define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) 12445 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk 12449 #define RTC_ALRMASSR_MASKSS_Pos (24U) 12450 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) 12451 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 12452 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) 12453 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) 12454 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) 12455 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) 12456 #define RTC_ALRMASSR_SS_Pos (0U) 12457 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) 12458 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 12461 #define RTC_ALRMBSSR_MASKSS_Pos (24U) 12462 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) 12463 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk 12464 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) 12465 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) 12466 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) 12467 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) 12468 #define RTC_ALRMBSSR_SS_Pos (0U) 12469 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) 12470 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk 12473 #define RTC_OR_TSINSEL_Pos (1U) 12474 #define RTC_OR_TSINSEL_Msk (0x3U << RTC_OR_TSINSEL_Pos) 12475 #define RTC_OR_TSINSEL RTC_OR_TSINSEL_Msk 12476 #define RTC_OR_TSINSEL_0 (0x1U << RTC_OR_TSINSEL_Pos) 12477 #define RTC_OR_TSINSEL_1 (0x2U << RTC_OR_TSINSEL_Pos) 12478 #define RTC_OR_ALARMOUTTYPE_Pos (3U) 12479 #define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) 12480 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk 12482 #define RTC_OR_ALARMTYPE RTC_OR_ALARMOUTTYPE 12485 #define RTC_BKP0R_Pos (0U) 12486 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) 12487 #define RTC_BKP0R RTC_BKP0R_Msk 12490 #define RTC_BKP1R_Pos (0U) 12491 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) 12492 #define RTC_BKP1R RTC_BKP1R_Msk 12495 #define RTC_BKP2R_Pos (0U) 12496 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) 12497 #define RTC_BKP2R RTC_BKP2R_Msk 12500 #define RTC_BKP3R_Pos (0U) 12501 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) 12502 #define RTC_BKP3R RTC_BKP3R_Msk 12505 #define RTC_BKP4R_Pos (0U) 12506 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) 12507 #define RTC_BKP4R RTC_BKP4R_Msk 12510 #define RTC_BKP5R_Pos (0U) 12511 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) 12512 #define RTC_BKP5R RTC_BKP5R_Msk 12515 #define RTC_BKP6R_Pos (0U) 12516 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) 12517 #define RTC_BKP6R RTC_BKP6R_Msk 12520 #define RTC_BKP7R_Pos (0U) 12521 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) 12522 #define RTC_BKP7R RTC_BKP7R_Msk 12525 #define RTC_BKP8R_Pos (0U) 12526 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) 12527 #define RTC_BKP8R RTC_BKP8R_Msk 12530 #define RTC_BKP9R_Pos (0U) 12531 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) 12532 #define RTC_BKP9R RTC_BKP9R_Msk 12535 #define RTC_BKP10R_Pos (0U) 12536 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) 12537 #define RTC_BKP10R RTC_BKP10R_Msk 12540 #define RTC_BKP11R_Pos (0U) 12541 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) 12542 #define RTC_BKP11R RTC_BKP11R_Msk 12545 #define RTC_BKP12R_Pos (0U) 12546 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) 12547 #define RTC_BKP12R RTC_BKP12R_Msk 12550 #define RTC_BKP13R_Pos (0U) 12551 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) 12552 #define RTC_BKP13R RTC_BKP13R_Msk 12555 #define RTC_BKP14R_Pos (0U) 12556 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) 12557 #define RTC_BKP14R RTC_BKP14R_Msk 12560 #define RTC_BKP15R_Pos (0U) 12561 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) 12562 #define RTC_BKP15R RTC_BKP15R_Msk 12565 #define RTC_BKP16R_Pos (0U) 12566 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) 12567 #define RTC_BKP16R RTC_BKP16R_Msk 12570 #define RTC_BKP17R_Pos (0U) 12571 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) 12572 #define RTC_BKP17R RTC_BKP17R_Msk 12575 #define RTC_BKP18R_Pos (0U) 12576 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) 12577 #define RTC_BKP18R RTC_BKP18R_Msk 12580 #define RTC_BKP19R_Pos (0U) 12581 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) 12582 #define RTC_BKP19R RTC_BKP19R_Msk 12585 #define RTC_BKP20R_Pos (0U) 12586 #define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) 12587 #define RTC_BKP20R RTC_BKP20R_Msk 12590 #define RTC_BKP21R_Pos (0U) 12591 #define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) 12592 #define RTC_BKP21R RTC_BKP21R_Msk 12595 #define RTC_BKP22R_Pos (0U) 12596 #define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) 12597 #define RTC_BKP22R RTC_BKP22R_Msk 12600 #define RTC_BKP23R_Pos (0U) 12601 #define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) 12602 #define RTC_BKP23R RTC_BKP23R_Msk 12605 #define RTC_BKP24R_Pos (0U) 12606 #define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) 12607 #define RTC_BKP24R RTC_BKP24R_Msk 12610 #define RTC_BKP25R_Pos (0U) 12611 #define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) 12612 #define RTC_BKP25R RTC_BKP25R_Msk 12615 #define RTC_BKP26R_Pos (0U) 12616 #define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) 12617 #define RTC_BKP26R RTC_BKP26R_Msk 12620 #define RTC_BKP27R_Pos (0U) 12621 #define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) 12622 #define RTC_BKP27R RTC_BKP27R_Msk 12625 #define RTC_BKP28R_Pos (0U) 12626 #define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) 12627 #define RTC_BKP28R RTC_BKP28R_Msk 12630 #define RTC_BKP29R_Pos (0U) 12631 #define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) 12632 #define RTC_BKP29R RTC_BKP29R_Msk 12635 #define RTC_BKP30R_Pos (0U) 12636 #define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) 12637 #define RTC_BKP30R RTC_BKP30R_Msk 12640 #define RTC_BKP31R_Pos (0U) 12641 #define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) 12642 #define RTC_BKP31R RTC_BKP31R_Msk 12645 #define RTC_BKP_NUMBER 0x00000020U 12653 #define SAI_GCR_SYNCIN_Pos (0U) 12654 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) 12655 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk 12656 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) 12657 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) 12659 #define SAI_GCR_SYNCOUT_Pos (4U) 12660 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) 12661 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk 12662 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) 12663 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) 12666 #define SAI_xCR1_MODE_Pos (0U) 12667 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) 12668 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk 12669 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) 12670 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) 12672 #define SAI_xCR1_PRTCFG_Pos (2U) 12673 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) 12674 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk 12675 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) 12676 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) 12678 #define SAI_xCR1_DS_Pos (5U) 12679 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) 12680 #define SAI_xCR1_DS SAI_xCR1_DS_Msk 12681 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) 12682 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) 12683 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) 12685 #define SAI_xCR1_LSBFIRST_Pos (8U) 12686 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) 12687 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk 12688 #define SAI_xCR1_CKSTR_Pos (9U) 12689 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) 12690 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk 12692 #define SAI_xCR1_SYNCEN_Pos (10U) 12693 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) 12694 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk 12695 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) 12696 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) 12698 #define SAI_xCR1_MONO_Pos (12U) 12699 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) 12700 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk 12701 #define SAI_xCR1_OUTDRIV_Pos (13U) 12702 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) 12703 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk 12704 #define SAI_xCR1_SAIEN_Pos (16U) 12705 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) 12706 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk 12707 #define SAI_xCR1_DMAEN_Pos (17U) 12708 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) 12709 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk 12710 #define SAI_xCR1_NODIV_Pos (19U) 12711 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) 12712 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk 12714 #define SAI_xCR1_MCKDIV_Pos (20U) 12715 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) 12716 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk 12717 #define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) 12718 #define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) 12719 #define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) 12720 #define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) 12723 #define SAI_xCR2_FTH_Pos (0U) 12724 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) 12725 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk 12726 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) 12727 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) 12728 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) 12730 #define SAI_xCR2_FFLUSH_Pos (3U) 12731 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) 12732 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk 12733 #define SAI_xCR2_TRIS_Pos (4U) 12734 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) 12735 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk 12736 #define SAI_xCR2_MUTE_Pos (5U) 12737 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) 12738 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk 12739 #define SAI_xCR2_MUTEVAL_Pos (6U) 12740 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) 12741 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk 12743 #define SAI_xCR2_MUTECNT_Pos (7U) 12744 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) 12745 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk 12746 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) 12747 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) 12748 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) 12749 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) 12750 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) 12751 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) 12753 #define SAI_xCR2_CPL_Pos (13U) 12754 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) 12755 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk 12757 #define SAI_xCR2_COMP_Pos (14U) 12758 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) 12759 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk 12760 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) 12761 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) 12764 #define SAI_xFRCR_FRL_Pos (0U) 12765 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) 12766 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk 12767 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) 12768 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) 12769 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) 12770 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) 12771 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) 12772 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) 12773 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) 12774 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) 12776 #define SAI_xFRCR_FSALL_Pos (8U) 12777 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) 12778 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk 12779 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) 12780 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) 12781 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) 12782 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) 12783 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) 12784 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) 12785 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) 12787 #define SAI_xFRCR_FSDEF_Pos (16U) 12788 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) 12789 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk 12790 #define SAI_xFRCR_FSPOL_Pos (17U) 12791 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) 12792 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk 12793 #define SAI_xFRCR_FSOFF_Pos (18U) 12794 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) 12795 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk 12798 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL 12801 #define SAI_xSLOTR_FBOFF_Pos (0U) 12802 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) 12803 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk 12804 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) 12805 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) 12806 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) 12807 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) 12808 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) 12810 #define SAI_xSLOTR_SLOTSZ_Pos (6U) 12811 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) 12812 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk 12813 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) 12814 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) 12816 #define SAI_xSLOTR_NBSLOT_Pos (8U) 12817 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) 12818 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk 12819 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) 12820 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) 12821 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) 12822 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) 12824 #define SAI_xSLOTR_SLOTEN_Pos (16U) 12825 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) 12826 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk 12829 #define SAI_xIMR_OVRUDRIE_Pos (0U) 12830 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) 12831 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk 12832 #define SAI_xIMR_MUTEDETIE_Pos (1U) 12833 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) 12834 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk 12835 #define SAI_xIMR_WCKCFGIE_Pos (2U) 12836 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) 12837 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk 12838 #define SAI_xIMR_FREQIE_Pos (3U) 12839 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) 12840 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk 12841 #define SAI_xIMR_CNRDYIE_Pos (4U) 12842 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) 12843 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk 12844 #define SAI_xIMR_AFSDETIE_Pos (5U) 12845 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) 12846 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk 12847 #define SAI_xIMR_LFSDETIE_Pos (6U) 12848 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) 12849 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk 12852 #define SAI_xSR_OVRUDR_Pos (0U) 12853 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) 12854 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk 12855 #define SAI_xSR_MUTEDET_Pos (1U) 12856 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) 12857 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk 12858 #define SAI_xSR_WCKCFG_Pos (2U) 12859 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) 12860 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk 12861 #define SAI_xSR_FREQ_Pos (3U) 12862 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) 12863 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk 12864 #define SAI_xSR_CNRDY_Pos (4U) 12865 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) 12866 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk 12867 #define SAI_xSR_AFSDET_Pos (5U) 12868 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) 12869 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk 12870 #define SAI_xSR_LFSDET_Pos (6U) 12871 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) 12872 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk 12874 #define SAI_xSR_FLVL_Pos (16U) 12875 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) 12876 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk 12877 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) 12878 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) 12879 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) 12882 #define SAI_xCLRFR_COVRUDR_Pos (0U) 12883 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) 12884 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk 12885 #define SAI_xCLRFR_CMUTEDET_Pos (1U) 12886 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) 12887 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk 12888 #define SAI_xCLRFR_CWCKCFG_Pos (2U) 12889 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) 12890 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk 12891 #define SAI_xCLRFR_CFREQ_Pos (3U) 12892 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) 12893 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk 12894 #define SAI_xCLRFR_CCNRDY_Pos (4U) 12895 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) 12896 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk 12897 #define SAI_xCLRFR_CAFSDET_Pos (5U) 12898 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) 12899 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk 12900 #define SAI_xCLRFR_CLFSDET_Pos (6U) 12901 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) 12902 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk 12905 #define SAI_xDR_DATA_Pos (0U) 12906 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) 12907 #define SAI_xDR_DATA SAI_xDR_DATA_Msk 12915 #define SPDIFRX_CR_SPDIFEN_Pos (0U) 12916 #define SPDIFRX_CR_SPDIFEN_Msk (0x3U << SPDIFRX_CR_SPDIFEN_Pos) 12917 #define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk 12918 #define SPDIFRX_CR_RXDMAEN_Pos (2U) 12919 #define SPDIFRX_CR_RXDMAEN_Msk (0x1U << SPDIFRX_CR_RXDMAEN_Pos) 12920 #define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk 12921 #define SPDIFRX_CR_RXSTEO_Pos (3U) 12922 #define SPDIFRX_CR_RXSTEO_Msk (0x1U << SPDIFRX_CR_RXSTEO_Pos) 12923 #define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk 12924 #define SPDIFRX_CR_DRFMT_Pos (4U) 12925 #define SPDIFRX_CR_DRFMT_Msk (0x3U << SPDIFRX_CR_DRFMT_Pos) 12926 #define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk 12927 #define SPDIFRX_CR_PMSK_Pos (6U) 12928 #define SPDIFRX_CR_PMSK_Msk (0x1U << SPDIFRX_CR_PMSK_Pos) 12929 #define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk 12930 #define SPDIFRX_CR_VMSK_Pos (7U) 12931 #define SPDIFRX_CR_VMSK_Msk (0x1U << SPDIFRX_CR_VMSK_Pos) 12932 #define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk 12933 #define SPDIFRX_CR_CUMSK_Pos (8U) 12934 #define SPDIFRX_CR_CUMSK_Msk (0x1U << SPDIFRX_CR_CUMSK_Pos) 12935 #define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk 12936 #define SPDIFRX_CR_PTMSK_Pos (9U) 12937 #define SPDIFRX_CR_PTMSK_Msk (0x1U << SPDIFRX_CR_PTMSK_Pos) 12938 #define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk 12939 #define SPDIFRX_CR_CBDMAEN_Pos (10U) 12940 #define SPDIFRX_CR_CBDMAEN_Msk (0x1U << SPDIFRX_CR_CBDMAEN_Pos) 12941 #define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk 12942 #define SPDIFRX_CR_CHSEL_Pos (11U) 12943 #define SPDIFRX_CR_CHSEL_Msk (0x1U << SPDIFRX_CR_CHSEL_Pos) 12944 #define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk 12945 #define SPDIFRX_CR_NBTR_Pos (12U) 12946 #define SPDIFRX_CR_NBTR_Msk (0x3U << SPDIFRX_CR_NBTR_Pos) 12947 #define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk 12948 #define SPDIFRX_CR_WFA_Pos (14U) 12949 #define SPDIFRX_CR_WFA_Msk (0x1U << SPDIFRX_CR_WFA_Pos) 12950 #define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk 12951 #define SPDIFRX_CR_INSEL_Pos (16U) 12952 #define SPDIFRX_CR_INSEL_Msk (0x7U << SPDIFRX_CR_INSEL_Pos) 12953 #define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk 12956 #define SPDIFRX_IMR_RXNEIE_Pos (0U) 12957 #define SPDIFRX_IMR_RXNEIE_Msk (0x1U << SPDIFRX_IMR_RXNEIE_Pos) 12958 #define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk 12959 #define SPDIFRX_IMR_CSRNEIE_Pos (1U) 12960 #define SPDIFRX_IMR_CSRNEIE_Msk (0x1U << SPDIFRX_IMR_CSRNEIE_Pos) 12961 #define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk 12962 #define SPDIFRX_IMR_PERRIE_Pos (2U) 12963 #define SPDIFRX_IMR_PERRIE_Msk (0x1U << SPDIFRX_IMR_PERRIE_Pos) 12964 #define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk 12965 #define SPDIFRX_IMR_OVRIE_Pos (3U) 12966 #define SPDIFRX_IMR_OVRIE_Msk (0x1U << SPDIFRX_IMR_OVRIE_Pos) 12967 #define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk 12968 #define SPDIFRX_IMR_SBLKIE_Pos (4U) 12969 #define SPDIFRX_IMR_SBLKIE_Msk (0x1U << SPDIFRX_IMR_SBLKIE_Pos) 12970 #define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk 12971 #define SPDIFRX_IMR_SYNCDIE_Pos (5U) 12972 #define SPDIFRX_IMR_SYNCDIE_Msk (0x1U << SPDIFRX_IMR_SYNCDIE_Pos) 12973 #define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk 12974 #define SPDIFRX_IMR_IFEIE_Pos (6U) 12975 #define SPDIFRX_IMR_IFEIE_Msk (0x1U << SPDIFRX_IMR_IFEIE_Pos) 12976 #define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk 12979 #define SPDIFRX_SR_RXNE_Pos (0U) 12980 #define SPDIFRX_SR_RXNE_Msk (0x1U << SPDIFRX_SR_RXNE_Pos) 12981 #define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk 12982 #define SPDIFRX_SR_CSRNE_Pos (1U) 12983 #define SPDIFRX_SR_CSRNE_Msk (0x1U << SPDIFRX_SR_CSRNE_Pos) 12984 #define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk 12985 #define SPDIFRX_SR_PERR_Pos (2U) 12986 #define SPDIFRX_SR_PERR_Msk (0x1U << SPDIFRX_SR_PERR_Pos) 12987 #define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk 12988 #define SPDIFRX_SR_OVR_Pos (3U) 12989 #define SPDIFRX_SR_OVR_Msk (0x1U << SPDIFRX_SR_OVR_Pos) 12990 #define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk 12991 #define SPDIFRX_SR_SBD_Pos (4U) 12992 #define SPDIFRX_SR_SBD_Msk (0x1U << SPDIFRX_SR_SBD_Pos) 12993 #define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk 12994 #define SPDIFRX_SR_SYNCD_Pos (5U) 12995 #define SPDIFRX_SR_SYNCD_Msk (0x1U << SPDIFRX_SR_SYNCD_Pos) 12996 #define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk 12997 #define SPDIFRX_SR_FERR_Pos (6U) 12998 #define SPDIFRX_SR_FERR_Msk (0x1U << SPDIFRX_SR_FERR_Pos) 12999 #define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk 13000 #define SPDIFRX_SR_SERR_Pos (7U) 13001 #define SPDIFRX_SR_SERR_Msk (0x1U << SPDIFRX_SR_SERR_Pos) 13002 #define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk 13003 #define SPDIFRX_SR_TERR_Pos (8U) 13004 #define SPDIFRX_SR_TERR_Msk (0x1U << SPDIFRX_SR_TERR_Pos) 13005 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk 13006 #define SPDIFRX_SR_WIDTH5_Pos (16U) 13007 #define SPDIFRX_SR_WIDTH5_Msk (0x7FFFU << SPDIFRX_SR_WIDTH5_Pos) 13008 #define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk 13011 #define SPDIFRX_IFCR_PERRCF_Pos (2U) 13012 #define SPDIFRX_IFCR_PERRCF_Msk (0x1U << SPDIFRX_IFCR_PERRCF_Pos) 13013 #define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk 13014 #define SPDIFRX_IFCR_OVRCF_Pos (3U) 13015 #define SPDIFRX_IFCR_OVRCF_Msk (0x1U << SPDIFRX_IFCR_OVRCF_Pos) 13016 #define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk 13017 #define SPDIFRX_IFCR_SBDCF_Pos (4U) 13018 #define SPDIFRX_IFCR_SBDCF_Msk (0x1U << SPDIFRX_IFCR_SBDCF_Pos) 13019 #define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk 13020 #define SPDIFRX_IFCR_SYNCDCF_Pos (5U) 13021 #define SPDIFRX_IFCR_SYNCDCF_Msk (0x1U << SPDIFRX_IFCR_SYNCDCF_Pos) 13022 #define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk 13025 #define SPDIFRX_DR0_DR_Pos (0U) 13026 #define SPDIFRX_DR0_DR_Msk (0xFFFFFFU << SPDIFRX_DR0_DR_Pos) 13027 #define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk 13028 #define SPDIFRX_DR0_PE_Pos (24U) 13029 #define SPDIFRX_DR0_PE_Msk (0x1U << SPDIFRX_DR0_PE_Pos) 13030 #define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk 13031 #define SPDIFRX_DR0_V_Pos (25U) 13032 #define SPDIFRX_DR0_V_Msk (0x1U << SPDIFRX_DR0_V_Pos) 13033 #define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk 13034 #define SPDIFRX_DR0_U_Pos (26U) 13035 #define SPDIFRX_DR0_U_Msk (0x1U << SPDIFRX_DR0_U_Pos) 13036 #define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk 13037 #define SPDIFRX_DR0_C_Pos (27U) 13038 #define SPDIFRX_DR0_C_Msk (0x1U << SPDIFRX_DR0_C_Pos) 13039 #define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk 13040 #define SPDIFRX_DR0_PT_Pos (28U) 13041 #define SPDIFRX_DR0_PT_Msk (0x3U << SPDIFRX_DR0_PT_Pos) 13042 #define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk 13045 #define SPDIFRX_DR1_DR_Pos (8U) 13046 #define SPDIFRX_DR1_DR_Msk (0xFFFFFFU << SPDIFRX_DR1_DR_Pos) 13047 #define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk 13048 #define SPDIFRX_DR1_PT_Pos (4U) 13049 #define SPDIFRX_DR1_PT_Msk (0x3U << SPDIFRX_DR1_PT_Pos) 13050 #define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk 13051 #define SPDIFRX_DR1_C_Pos (3U) 13052 #define SPDIFRX_DR1_C_Msk (0x1U << SPDIFRX_DR1_C_Pos) 13053 #define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk 13054 #define SPDIFRX_DR1_U_Pos (2U) 13055 #define SPDIFRX_DR1_U_Msk (0x1U << SPDIFRX_DR1_U_Pos) 13056 #define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk 13057 #define SPDIFRX_DR1_V_Pos (1U) 13058 #define SPDIFRX_DR1_V_Msk (0x1U << SPDIFRX_DR1_V_Pos) 13059 #define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk 13060 #define SPDIFRX_DR1_PE_Pos (0U) 13061 #define SPDIFRX_DR1_PE_Msk (0x1U << SPDIFRX_DR1_PE_Pos) 13062 #define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk 13065 #define SPDIFRX_DR1_DRNL1_Pos (16U) 13066 #define SPDIFRX_DR1_DRNL1_Msk (0xFFFFU << SPDIFRX_DR1_DRNL1_Pos) 13067 #define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk 13068 #define SPDIFRX_DR1_DRNL2_Pos (0U) 13069 #define SPDIFRX_DR1_DRNL2_Msk (0xFFFFU << SPDIFRX_DR1_DRNL2_Pos) 13070 #define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk 13073 #define SPDIFRX_CSR_USR_Pos (0U) 13074 #define SPDIFRX_CSR_USR_Msk (0xFFFFU << SPDIFRX_CSR_USR_Pos) 13075 #define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk 13076 #define SPDIFRX_CSR_CS_Pos (16U) 13077 #define SPDIFRX_CSR_CS_Msk (0xFFU << SPDIFRX_CSR_CS_Pos) 13078 #define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk 13079 #define SPDIFRX_CSR_SOB_Pos (24U) 13080 #define SPDIFRX_CSR_SOB_Msk (0x1U << SPDIFRX_CSR_SOB_Pos) 13081 #define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk 13084 #define SPDIFRX_DIR_THI_Pos (0U) 13085 #define SPDIFRX_DIR_THI_Msk (0x13FFU << SPDIFRX_DIR_THI_Pos) 13086 #define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk 13087 #define SPDIFRX_DIR_TLO_Pos (16U) 13088 #define SPDIFRX_DIR_TLO_Msk (0x1FFFU << SPDIFRX_DIR_TLO_Pos) 13089 #define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk 13097 #define SDMMC_POWER_PWRCTRL_Pos (0U) 13098 #define SDMMC_POWER_PWRCTRL_Msk (0x3U << SDMMC_POWER_PWRCTRL_Pos) 13099 #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk 13100 #define SDMMC_POWER_PWRCTRL_0 (0x1U << SDMMC_POWER_PWRCTRL_Pos) 13101 #define SDMMC_POWER_PWRCTRL_1 (0x2U << SDMMC_POWER_PWRCTRL_Pos) 13104 #define SDMMC_CLKCR_CLKDIV_Pos (0U) 13105 #define SDMMC_CLKCR_CLKDIV_Msk (0xFFU << SDMMC_CLKCR_CLKDIV_Pos) 13106 #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk 13107 #define SDMMC_CLKCR_CLKEN_Pos (8U) 13108 #define SDMMC_CLKCR_CLKEN_Msk (0x1U << SDMMC_CLKCR_CLKEN_Pos) 13109 #define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk 13110 #define SDMMC_CLKCR_PWRSAV_Pos (9U) 13111 #define SDMMC_CLKCR_PWRSAV_Msk (0x1U << SDMMC_CLKCR_PWRSAV_Pos) 13112 #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk 13113 #define SDMMC_CLKCR_BYPASS_Pos (10U) 13114 #define SDMMC_CLKCR_BYPASS_Msk (0x1U << SDMMC_CLKCR_BYPASS_Pos) 13115 #define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk 13117 #define SDMMC_CLKCR_WIDBUS_Pos (11U) 13118 #define SDMMC_CLKCR_WIDBUS_Msk (0x3U << SDMMC_CLKCR_WIDBUS_Pos) 13119 #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk 13120 #define SDMMC_CLKCR_WIDBUS_0 (0x1U << SDMMC_CLKCR_WIDBUS_Pos) 13121 #define SDMMC_CLKCR_WIDBUS_1 (0x2U << SDMMC_CLKCR_WIDBUS_Pos) 13123 #define SDMMC_CLKCR_NEGEDGE_Pos (13U) 13124 #define SDMMC_CLKCR_NEGEDGE_Msk (0x1U << SDMMC_CLKCR_NEGEDGE_Pos) 13125 #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk 13126 #define SDMMC_CLKCR_HWFC_EN_Pos (14U) 13127 #define SDMMC_CLKCR_HWFC_EN_Msk (0x1U << SDMMC_CLKCR_HWFC_EN_Pos) 13128 #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk 13131 #define SDMMC_ARG_CMDARG_Pos (0U) 13132 #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos) 13133 #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk 13136 #define SDMMC_CMD_CMDINDEX_Pos (0U) 13137 #define SDMMC_CMD_CMDINDEX_Msk (0x3FU << SDMMC_CMD_CMDINDEX_Pos) 13138 #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk 13140 #define SDMMC_CMD_WAITRESP_Pos (6U) 13141 #define SDMMC_CMD_WAITRESP_Msk (0x3U << SDMMC_CMD_WAITRESP_Pos) 13142 #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk 13143 #define SDMMC_CMD_WAITRESP_0 (0x1U << SDMMC_CMD_WAITRESP_Pos) 13144 #define SDMMC_CMD_WAITRESP_1 (0x2U << SDMMC_CMD_WAITRESP_Pos) 13146 #define SDMMC_CMD_WAITINT_Pos (8U) 13147 #define SDMMC_CMD_WAITINT_Msk (0x1U << SDMMC_CMD_WAITINT_Pos) 13148 #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk 13149 #define SDMMC_CMD_WAITPEND_Pos (9U) 13150 #define SDMMC_CMD_WAITPEND_Msk (0x1U << SDMMC_CMD_WAITPEND_Pos) 13151 #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk 13152 #define SDMMC_CMD_CPSMEN_Pos (10U) 13153 #define SDMMC_CMD_CPSMEN_Msk (0x1U << SDMMC_CMD_CPSMEN_Pos) 13154 #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk 13155 #define SDMMC_CMD_SDIOSUSPEND_Pos (11U) 13156 #define SDMMC_CMD_SDIOSUSPEND_Msk (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos) 13157 #define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk 13160 #define SDMMC_RESPCMD_RESPCMD_Pos (0U) 13161 #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos) 13162 #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk 13165 #define SDMMC_RESP0_CARDSTATUS0_Pos (0U) 13166 #define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDMMC_RESP0_CARDSTATUS0_Pos) 13167 #define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk 13170 #define SDMMC_RESP1_CARDSTATUS1_Pos (0U) 13171 #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) 13172 #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk 13175 #define SDMMC_RESP2_CARDSTATUS2_Pos (0U) 13176 #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) 13177 #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk 13180 #define SDMMC_RESP3_CARDSTATUS3_Pos (0U) 13181 #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) 13182 #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk 13185 #define SDMMC_RESP4_CARDSTATUS4_Pos (0U) 13186 #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) 13187 #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk 13190 #define SDMMC_DTIMER_DATATIME_Pos (0U) 13191 #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) 13192 #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk 13195 #define SDMMC_DLEN_DATALENGTH_Pos (0U) 13196 #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) 13197 #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk 13200 #define SDMMC_DCTRL_DTEN_Pos (0U) 13201 #define SDMMC_DCTRL_DTEN_Msk (0x1U << SDMMC_DCTRL_DTEN_Pos) 13202 #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk 13203 #define SDMMC_DCTRL_DTDIR_Pos (1U) 13204 #define SDMMC_DCTRL_DTDIR_Msk (0x1U << SDMMC_DCTRL_DTDIR_Pos) 13205 #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk 13206 #define SDMMC_DCTRL_DTMODE_Pos (2U) 13207 #define SDMMC_DCTRL_DTMODE_Msk (0x1U << SDMMC_DCTRL_DTMODE_Pos) 13208 #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk 13209 #define SDMMC_DCTRL_DMAEN_Pos (3U) 13210 #define SDMMC_DCTRL_DMAEN_Msk (0x1U << SDMMC_DCTRL_DMAEN_Pos) 13211 #define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk 13213 #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U) 13214 #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos) 13215 #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk 13216 #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos) 13217 #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos) 13218 #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos) 13219 #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos) 13221 #define SDMMC_DCTRL_RWSTART_Pos (8U) 13222 #define SDMMC_DCTRL_RWSTART_Msk (0x1U << SDMMC_DCTRL_RWSTART_Pos) 13223 #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk 13224 #define SDMMC_DCTRL_RWSTOP_Pos (9U) 13225 #define SDMMC_DCTRL_RWSTOP_Msk (0x1U << SDMMC_DCTRL_RWSTOP_Pos) 13226 #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk 13227 #define SDMMC_DCTRL_RWMOD_Pos (10U) 13228 #define SDMMC_DCTRL_RWMOD_Msk (0x1U << SDMMC_DCTRL_RWMOD_Pos) 13229 #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk 13230 #define SDMMC_DCTRL_SDIOEN_Pos (11U) 13231 #define SDMMC_DCTRL_SDIOEN_Msk (0x1U << SDMMC_DCTRL_SDIOEN_Pos) 13232 #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk 13235 #define SDMMC_DCOUNT_DATACOUNT_Pos (0U) 13236 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) 13237 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk 13240 #define SDMMC_STA_CCRCFAIL_Pos (0U) 13241 #define SDMMC_STA_CCRCFAIL_Msk (0x1U << SDMMC_STA_CCRCFAIL_Pos) 13242 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk 13243 #define SDMMC_STA_DCRCFAIL_Pos (1U) 13244 #define SDMMC_STA_DCRCFAIL_Msk (0x1U << SDMMC_STA_DCRCFAIL_Pos) 13245 #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk 13246 #define SDMMC_STA_CTIMEOUT_Pos (2U) 13247 #define SDMMC_STA_CTIMEOUT_Msk (0x1U << SDMMC_STA_CTIMEOUT_Pos) 13248 #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk 13249 #define SDMMC_STA_DTIMEOUT_Pos (3U) 13250 #define SDMMC_STA_DTIMEOUT_Msk (0x1U << SDMMC_STA_DTIMEOUT_Pos) 13251 #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk 13252 #define SDMMC_STA_TXUNDERR_Pos (4U) 13253 #define SDMMC_STA_TXUNDERR_Msk (0x1U << SDMMC_STA_TXUNDERR_Pos) 13254 #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk 13255 #define SDMMC_STA_RXOVERR_Pos (5U) 13256 #define SDMMC_STA_RXOVERR_Msk (0x1U << SDMMC_STA_RXOVERR_Pos) 13257 #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk 13258 #define SDMMC_STA_CMDREND_Pos (6U) 13259 #define SDMMC_STA_CMDREND_Msk (0x1U << SDMMC_STA_CMDREND_Pos) 13260 #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk 13261 #define SDMMC_STA_CMDSENT_Pos (7U) 13262 #define SDMMC_STA_CMDSENT_Msk (0x1U << SDMMC_STA_CMDSENT_Pos) 13263 #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk 13264 #define SDMMC_STA_DATAEND_Pos (8U) 13265 #define SDMMC_STA_DATAEND_Msk (0x1U << SDMMC_STA_DATAEND_Pos) 13266 #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk 13267 #define SDMMC_STA_DBCKEND_Pos (10U) 13268 #define SDMMC_STA_DBCKEND_Msk (0x1U << SDMMC_STA_DBCKEND_Pos) 13269 #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk 13270 #define SDMMC_STA_CMDACT_Pos (11U) 13271 #define SDMMC_STA_CMDACT_Msk (0x1U << SDMMC_STA_CMDACT_Pos) 13272 #define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk 13273 #define SDMMC_STA_TXACT_Pos (12U) 13274 #define SDMMC_STA_TXACT_Msk (0x1U << SDMMC_STA_TXACT_Pos) 13275 #define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk 13276 #define SDMMC_STA_RXACT_Pos (13U) 13277 #define SDMMC_STA_RXACT_Msk (0x1U << SDMMC_STA_RXACT_Pos) 13278 #define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk 13279 #define SDMMC_STA_TXFIFOHE_Pos (14U) 13280 #define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) 13281 #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk 13282 #define SDMMC_STA_RXFIFOHF_Pos (15U) 13283 #define SDMMC_STA_RXFIFOHF_Msk (0x1U << SDMMC_STA_RXFIFOHF_Pos) 13284 #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk 13285 #define SDMMC_STA_TXFIFOF_Pos (16U) 13286 #define SDMMC_STA_TXFIFOF_Msk (0x1U << SDMMC_STA_TXFIFOF_Pos) 13287 #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk 13288 #define SDMMC_STA_RXFIFOF_Pos (17U) 13289 #define SDMMC_STA_RXFIFOF_Msk (0x1U << SDMMC_STA_RXFIFOF_Pos) 13290 #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk 13291 #define SDMMC_STA_TXFIFOE_Pos (18U) 13292 #define SDMMC_STA_TXFIFOE_Msk (0x1U << SDMMC_STA_TXFIFOE_Pos) 13293 #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk 13294 #define SDMMC_STA_RXFIFOE_Pos (19U) 13295 #define SDMMC_STA_RXFIFOE_Msk (0x1U << SDMMC_STA_RXFIFOE_Pos) 13296 #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk 13297 #define SDMMC_STA_TXDAVL_Pos (20U) 13298 #define SDMMC_STA_TXDAVL_Msk (0x1U << SDMMC_STA_TXDAVL_Pos) 13299 #define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk 13300 #define SDMMC_STA_RXDAVL_Pos (21U) 13301 #define SDMMC_STA_RXDAVL_Msk (0x1U << SDMMC_STA_RXDAVL_Pos) 13302 #define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk 13303 #define SDMMC_STA_SDIOIT_Pos (22U) 13304 #define SDMMC_STA_SDIOIT_Msk (0x1U << SDMMC_STA_SDIOIT_Pos) 13305 #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk 13308 #define SDMMC_ICR_CCRCFAILC_Pos (0U) 13309 #define SDMMC_ICR_CCRCFAILC_Msk (0x1U << SDMMC_ICR_CCRCFAILC_Pos) 13310 #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk 13311 #define SDMMC_ICR_DCRCFAILC_Pos (1U) 13312 #define SDMMC_ICR_DCRCFAILC_Msk (0x1U << SDMMC_ICR_DCRCFAILC_Pos) 13313 #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk 13314 #define SDMMC_ICR_CTIMEOUTC_Pos (2U) 13315 #define SDMMC_ICR_CTIMEOUTC_Msk (0x1U << SDMMC_ICR_CTIMEOUTC_Pos) 13316 #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk 13317 #define SDMMC_ICR_DTIMEOUTC_Pos (3U) 13318 #define SDMMC_ICR_DTIMEOUTC_Msk (0x1U << SDMMC_ICR_DTIMEOUTC_Pos) 13319 #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk 13320 #define SDMMC_ICR_TXUNDERRC_Pos (4U) 13321 #define SDMMC_ICR_TXUNDERRC_Msk (0x1U << SDMMC_ICR_TXUNDERRC_Pos) 13322 #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk 13323 #define SDMMC_ICR_RXOVERRC_Pos (5U) 13324 #define SDMMC_ICR_RXOVERRC_Msk (0x1U << SDMMC_ICR_RXOVERRC_Pos) 13325 #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk 13326 #define SDMMC_ICR_CMDRENDC_Pos (6U) 13327 #define SDMMC_ICR_CMDRENDC_Msk (0x1U << SDMMC_ICR_CMDRENDC_Pos) 13328 #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk 13329 #define SDMMC_ICR_CMDSENTC_Pos (7U) 13330 #define SDMMC_ICR_CMDSENTC_Msk (0x1U << SDMMC_ICR_CMDSENTC_Pos) 13331 #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk 13332 #define SDMMC_ICR_DATAENDC_Pos (8U) 13333 #define SDMMC_ICR_DATAENDC_Msk (0x1U << SDMMC_ICR_DATAENDC_Pos) 13334 #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk 13335 #define SDMMC_ICR_DBCKENDC_Pos (10U) 13336 #define SDMMC_ICR_DBCKENDC_Msk (0x1U << SDMMC_ICR_DBCKENDC_Pos) 13337 #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk 13338 #define SDMMC_ICR_SDIOITC_Pos (22U) 13339 #define SDMMC_ICR_SDIOITC_Msk (0x1U << SDMMC_ICR_SDIOITC_Pos) 13340 #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk 13343 #define SDMMC_MASK_CCRCFAILIE_Pos (0U) 13344 #define SDMMC_MASK_CCRCFAILIE_Msk (0x1U << SDMMC_MASK_CCRCFAILIE_Pos) 13345 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk 13346 #define SDMMC_MASK_DCRCFAILIE_Pos (1U) 13347 #define SDMMC_MASK_DCRCFAILIE_Msk (0x1U << SDMMC_MASK_DCRCFAILIE_Pos) 13348 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk 13349 #define SDMMC_MASK_CTIMEOUTIE_Pos (2U) 13350 #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos) 13351 #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk 13352 #define SDMMC_MASK_DTIMEOUTIE_Pos (3U) 13353 #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos) 13354 #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk 13355 #define SDMMC_MASK_TXUNDERRIE_Pos (4U) 13356 #define SDMMC_MASK_TXUNDERRIE_Msk (0x1U << SDMMC_MASK_TXUNDERRIE_Pos) 13357 #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk 13358 #define SDMMC_MASK_RXOVERRIE_Pos (5U) 13359 #define SDMMC_MASK_RXOVERRIE_Msk (0x1U << SDMMC_MASK_RXOVERRIE_Pos) 13360 #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk 13361 #define SDMMC_MASK_CMDRENDIE_Pos (6U) 13362 #define SDMMC_MASK_CMDRENDIE_Msk (0x1U << SDMMC_MASK_CMDRENDIE_Pos) 13363 #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk 13364 #define SDMMC_MASK_CMDSENTIE_Pos (7U) 13365 #define SDMMC_MASK_CMDSENTIE_Msk (0x1U << SDMMC_MASK_CMDSENTIE_Pos) 13366 #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk 13367 #define SDMMC_MASK_DATAENDIE_Pos (8U) 13368 #define SDMMC_MASK_DATAENDIE_Msk (0x1U << SDMMC_MASK_DATAENDIE_Pos) 13369 #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk 13370 #define SDMMC_MASK_DBCKENDIE_Pos (10U) 13371 #define SDMMC_MASK_DBCKENDIE_Msk (0x1U << SDMMC_MASK_DBCKENDIE_Pos) 13372 #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk 13373 #define SDMMC_MASK_CMDACTIE_Pos (11U) 13374 #define SDMMC_MASK_CMDACTIE_Msk (0x1U << SDMMC_MASK_CMDACTIE_Pos) 13375 #define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk 13376 #define SDMMC_MASK_TXACTIE_Pos (12U) 13377 #define SDMMC_MASK_TXACTIE_Msk (0x1U << SDMMC_MASK_TXACTIE_Pos) 13378 #define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk 13379 #define SDMMC_MASK_RXACTIE_Pos (13U) 13380 #define SDMMC_MASK_RXACTIE_Msk (0x1U << SDMMC_MASK_RXACTIE_Pos) 13381 #define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk 13382 #define SDMMC_MASK_TXFIFOHEIE_Pos (14U) 13383 #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos) 13384 #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk 13385 #define SDMMC_MASK_RXFIFOHFIE_Pos (15U) 13386 #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos) 13387 #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk 13388 #define SDMMC_MASK_TXFIFOFIE_Pos (16U) 13389 #define SDMMC_MASK_TXFIFOFIE_Msk (0x1U << SDMMC_MASK_TXFIFOFIE_Pos) 13390 #define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk 13391 #define SDMMC_MASK_RXFIFOFIE_Pos (17U) 13392 #define SDMMC_MASK_RXFIFOFIE_Msk (0x1U << SDMMC_MASK_RXFIFOFIE_Pos) 13393 #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk 13394 #define SDMMC_MASK_TXFIFOEIE_Pos (18U) 13395 #define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) 13396 #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk 13397 #define SDMMC_MASK_RXFIFOEIE_Pos (19U) 13398 #define SDMMC_MASK_RXFIFOEIE_Msk (0x1U << SDMMC_MASK_RXFIFOEIE_Pos) 13399 #define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk 13400 #define SDMMC_MASK_TXDAVLIE_Pos (20U) 13401 #define SDMMC_MASK_TXDAVLIE_Msk (0x1U << SDMMC_MASK_TXDAVLIE_Pos) 13402 #define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk 13403 #define SDMMC_MASK_RXDAVLIE_Pos (21U) 13404 #define SDMMC_MASK_RXDAVLIE_Msk (0x1U << SDMMC_MASK_RXDAVLIE_Pos) 13405 #define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk 13406 #define SDMMC_MASK_SDIOITIE_Pos (22U) 13407 #define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) 13408 #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk 13411 #define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U) 13412 #define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) 13413 #define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk 13416 #define SDMMC_FIFO_FIFODATA_Pos (0U) 13417 #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) 13418 #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk 13426 #define SPI_CR1_CPHA_Pos (0U) 13427 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) 13428 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk 13429 #define SPI_CR1_CPOL_Pos (1U) 13430 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) 13431 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk 13432 #define SPI_CR1_MSTR_Pos (2U) 13433 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) 13434 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk 13435 #define SPI_CR1_BR_Pos (3U) 13436 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) 13437 #define SPI_CR1_BR SPI_CR1_BR_Msk 13438 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) 13439 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) 13440 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) 13441 #define SPI_CR1_SPE_Pos (6U) 13442 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) 13443 #define SPI_CR1_SPE SPI_CR1_SPE_Msk 13444 #define SPI_CR1_LSBFIRST_Pos (7U) 13445 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) 13446 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk 13447 #define SPI_CR1_SSI_Pos (8U) 13448 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) 13449 #define SPI_CR1_SSI SPI_CR1_SSI_Msk 13450 #define SPI_CR1_SSM_Pos (9U) 13451 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) 13452 #define SPI_CR1_SSM SPI_CR1_SSM_Msk 13453 #define SPI_CR1_RXONLY_Pos (10U) 13454 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) 13455 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk 13456 #define SPI_CR1_CRCL_Pos (11U) 13457 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) 13458 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk 13459 #define SPI_CR1_CRCNEXT_Pos (12U) 13460 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) 13461 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk 13462 #define SPI_CR1_CRCEN_Pos (13U) 13463 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) 13464 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk 13465 #define SPI_CR1_BIDIOE_Pos (14U) 13466 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) 13467 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk 13468 #define SPI_CR1_BIDIMODE_Pos (15U) 13469 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) 13470 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk 13473 #define SPI_CR2_RXDMAEN_Pos (0U) 13474 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) 13475 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk 13476 #define SPI_CR2_TXDMAEN_Pos (1U) 13477 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) 13478 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk 13479 #define SPI_CR2_SSOE_Pos (2U) 13480 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) 13481 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk 13482 #define SPI_CR2_NSSP_Pos (3U) 13483 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) 13484 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk 13485 #define SPI_CR2_FRF_Pos (4U) 13486 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) 13487 #define SPI_CR2_FRF SPI_CR2_FRF_Msk 13488 #define SPI_CR2_ERRIE_Pos (5U) 13489 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) 13490 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk 13491 #define SPI_CR2_RXNEIE_Pos (6U) 13492 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) 13493 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk 13494 #define SPI_CR2_TXEIE_Pos (7U) 13495 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) 13496 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk 13497 #define SPI_CR2_DS_Pos (8U) 13498 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) 13499 #define SPI_CR2_DS SPI_CR2_DS_Msk 13500 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) 13501 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) 13502 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) 13503 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) 13504 #define SPI_CR2_FRXTH_Pos (12U) 13505 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) 13506 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk 13507 #define SPI_CR2_LDMARX_Pos (13U) 13508 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) 13509 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk 13510 #define SPI_CR2_LDMATX_Pos (14U) 13511 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) 13512 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk 13515 #define SPI_SR_RXNE_Pos (0U) 13516 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) 13517 #define SPI_SR_RXNE SPI_SR_RXNE_Msk 13518 #define SPI_SR_TXE_Pos (1U) 13519 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) 13520 #define SPI_SR_TXE SPI_SR_TXE_Msk 13521 #define SPI_SR_CHSIDE_Pos (2U) 13522 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) 13523 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk 13524 #define SPI_SR_UDR_Pos (3U) 13525 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) 13526 #define SPI_SR_UDR SPI_SR_UDR_Msk 13527 #define SPI_SR_CRCERR_Pos (4U) 13528 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) 13529 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk 13530 #define SPI_SR_MODF_Pos (5U) 13531 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) 13532 #define SPI_SR_MODF SPI_SR_MODF_Msk 13533 #define SPI_SR_OVR_Pos (6U) 13534 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) 13535 #define SPI_SR_OVR SPI_SR_OVR_Msk 13536 #define SPI_SR_BSY_Pos (7U) 13537 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) 13538 #define SPI_SR_BSY SPI_SR_BSY_Msk 13539 #define SPI_SR_FRE_Pos (8U) 13540 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) 13541 #define SPI_SR_FRE SPI_SR_FRE_Msk 13542 #define SPI_SR_FRLVL_Pos (9U) 13543 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) 13544 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk 13545 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) 13546 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) 13547 #define SPI_SR_FTLVL_Pos (11U) 13548 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) 13549 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk 13550 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) 13551 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) 13554 #define SPI_DR_DR_Pos (0U) 13555 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) 13556 #define SPI_DR_DR SPI_DR_DR_Msk 13559 #define SPI_CRCPR_CRCPOLY_Pos (0U) 13560 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) 13561 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk 13564 #define SPI_RXCRCR_RXCRC_Pos (0U) 13565 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) 13566 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk 13569 #define SPI_TXCRCR_TXCRC_Pos (0U) 13570 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) 13571 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk 13574 #define SPI_I2SCFGR_CHLEN_Pos (0U) 13575 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) 13576 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk 13577 #define SPI_I2SCFGR_DATLEN_Pos (1U) 13578 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) 13579 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk 13580 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) 13581 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) 13582 #define SPI_I2SCFGR_CKPOL_Pos (3U) 13583 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) 13584 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk 13585 #define SPI_I2SCFGR_I2SSTD_Pos (4U) 13586 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) 13587 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk 13588 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) 13589 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) 13590 #define SPI_I2SCFGR_PCMSYNC_Pos (7U) 13591 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) 13592 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk 13593 #define SPI_I2SCFGR_I2SCFG_Pos (8U) 13594 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) 13595 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk 13596 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) 13597 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) 13598 #define SPI_I2SCFGR_I2SE_Pos (10U) 13599 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) 13600 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk 13601 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 13602 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) 13603 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk 13604 #define SPI_I2SCFGR_ASTRTEN_Pos (12U) 13605 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) 13606 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk 13609 #define SPI_I2SPR_I2SDIV_Pos (0U) 13610 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) 13611 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk 13612 #define SPI_I2SPR_ODD_Pos (8U) 13613 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) 13614 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk 13615 #define SPI_I2SPR_MCKOE_Pos (9U) 13616 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) 13617 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk 13626 #define SYSCFG_MEMRMP_MEM_BOOT_Pos (0U) 13627 #define SYSCFG_MEMRMP_MEM_BOOT_Msk (0x1U << SYSCFG_MEMRMP_MEM_BOOT_Pos) 13628 #define SYSCFG_MEMRMP_MEM_BOOT SYSCFG_MEMRMP_MEM_BOOT_Msk 13630 #define SYSCFG_MEMRMP_SWP_FB_Pos (8U) 13631 #define SYSCFG_MEMRMP_SWP_FB_Msk (0x1U << SYSCFG_MEMRMP_SWP_FB_Pos) 13632 #define SYSCFG_MEMRMP_SWP_FB SYSCFG_MEMRMP_SWP_FB_Msk 13634 #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U) 13635 #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) 13636 #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk 13637 #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) 13638 #define SYSCFG_MEMRMP_SWP_FMC_1 (0x2U << SYSCFG_MEMRMP_SWP_FMC_Pos) 13641 #define SYSCFG_PMC_I2C1_FMP_Pos (0U) 13642 #define SYSCFG_PMC_I2C1_FMP_Msk (0x1U << SYSCFG_PMC_I2C1_FMP_Pos) 13643 #define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk 13644 #define SYSCFG_PMC_I2C2_FMP_Pos (1U) 13645 #define SYSCFG_PMC_I2C2_FMP_Msk (0x1U << SYSCFG_PMC_I2C2_FMP_Pos) 13646 #define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk 13647 #define SYSCFG_PMC_I2C3_FMP_Pos (2U) 13648 #define SYSCFG_PMC_I2C3_FMP_Msk (0x1U << SYSCFG_PMC_I2C3_FMP_Pos) 13649 #define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk 13650 #define SYSCFG_PMC_I2C4_FMP_Pos (3U) 13651 #define SYSCFG_PMC_I2C4_FMP_Msk (0x1U << SYSCFG_PMC_I2C4_FMP_Pos) 13652 #define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk 13653 #define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U) 13654 #define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1U << SYSCFG_PMC_I2C_PB6_FMP_Pos) 13655 #define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk 13656 #define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U) 13657 #define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1U << SYSCFG_PMC_I2C_PB7_FMP_Pos) 13658 #define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk 13659 #define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U) 13660 #define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1U << SYSCFG_PMC_I2C_PB8_FMP_Pos) 13661 #define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk 13662 #define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U) 13663 #define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1U << SYSCFG_PMC_I2C_PB9_FMP_Pos) 13664 #define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk 13666 #define SYSCFG_PMC_ADCxDC2_Pos (16U) 13667 #define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) 13668 #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk 13669 #define SYSCFG_PMC_ADC1DC2_Pos (16U) 13670 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) 13671 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk 13672 #define SYSCFG_PMC_ADC2DC2_Pos (17U) 13673 #define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) 13674 #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk 13675 #define SYSCFG_PMC_ADC3DC2_Pos (18U) 13676 #define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) 13677 #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk 13679 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U) 13680 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) 13681 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk 13684 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 13685 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) 13686 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk 13687 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 13688 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) 13689 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk 13690 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 13691 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) 13692 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk 13693 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 13694 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) 13695 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk 13699 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U 13700 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U 13701 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U 13702 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U 13703 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U 13704 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U 13705 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U 13706 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U 13707 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U 13708 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U 13709 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU 13714 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U 13715 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U 13716 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U 13717 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U 13718 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U 13719 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U 13720 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U 13721 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U 13722 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U 13723 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U 13724 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U 13729 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U 13730 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U 13731 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U 13732 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U 13733 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U 13734 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U 13735 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U 13736 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U 13737 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U 13738 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U 13739 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U 13744 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U 13745 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U 13746 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U 13747 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U 13748 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U 13749 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U 13750 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U 13751 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U 13752 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U 13753 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U 13754 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U 13757 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 13758 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) 13759 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk 13760 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 13761 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) 13762 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk 13763 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 13764 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) 13765 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk 13766 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 13767 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) 13768 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk 13772 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U 13773 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U 13774 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U 13775 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U 13776 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U 13777 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U 13778 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U 13779 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U 13780 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U 13781 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U 13782 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU 13787 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U 13788 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U 13789 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U 13790 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U 13791 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U 13792 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U 13793 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U 13794 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U 13795 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U 13796 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U 13797 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U 13802 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U 13803 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U 13804 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U 13805 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U 13806 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U 13807 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U 13808 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U 13809 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U 13810 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U 13811 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U 13812 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U 13817 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U 13818 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U 13819 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U 13820 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U 13821 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U 13822 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U 13823 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U 13824 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U 13825 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U 13826 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U 13827 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U 13830 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 13831 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) 13832 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk 13833 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 13834 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) 13835 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk 13836 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 13837 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) 13838 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk 13839 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 13840 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) 13841 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk 13846 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U 13847 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U 13848 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U 13849 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U 13850 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U 13851 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U 13852 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U 13853 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U 13854 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U 13855 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U 13860 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U 13861 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U 13862 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U 13863 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U 13864 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U 13865 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U 13866 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U 13867 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U 13868 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U 13869 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U 13874 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U 13875 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U 13876 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U 13877 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U 13878 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U 13879 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U 13880 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U 13881 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U 13882 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U 13883 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U 13888 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U 13889 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U 13890 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U 13891 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U 13892 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U 13893 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U 13894 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U 13895 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U 13896 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U 13897 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U 13901 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 13902 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) 13903 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk 13904 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 13905 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) 13906 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk 13907 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 13908 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) 13909 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk 13910 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 13911 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) 13912 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk 13916 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U 13917 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U 13918 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U 13919 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U 13920 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U 13921 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U 13922 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U 13923 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U 13924 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U 13925 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U 13930 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U 13931 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U 13932 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U 13933 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U 13934 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U 13935 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U 13936 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U 13937 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U 13938 #define SYSCFG_EXTICR4_EXTI13_PI 0x0080U 13939 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U 13944 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U 13945 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U 13946 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U 13947 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U 13948 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U 13949 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U 13950 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U 13951 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U 13952 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U 13953 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U 13958 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U 13959 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U 13960 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U 13961 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U 13962 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U 13963 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U 13964 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U 13965 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U 13966 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U 13967 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U 13970 #define SYSCFG_CBR_CLL_Pos (0U) 13971 #define SYSCFG_CBR_CLL_Msk (0x1U << SYSCFG_CBR_CLL_Pos) 13972 #define SYSCFG_CBR_CLL SYSCFG_CBR_CLL_Msk 13973 #define SYSCFG_CBR_PVDL_Pos (2U) 13974 #define SYSCFG_CBR_PVDL_Msk (0x1U << SYSCFG_CBR_PVDL_Pos) 13975 #define SYSCFG_CBR_PVDL SYSCFG_CBR_PVDL_Msk 13978 #define SYSCFG_CMPCR_CMP_PD_Pos (0U) 13979 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) 13980 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk 13981 #define SYSCFG_CMPCR_READY_Pos (8U) 13982 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) 13983 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk 13993 #define TIM_BREAK_INPUT_SUPPORT 13995 #define TIM_CR1_CEN_Pos (0U) 13996 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) 13997 #define TIM_CR1_CEN TIM_CR1_CEN_Msk 13998 #define TIM_CR1_UDIS_Pos (1U) 13999 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) 14000 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk 14001 #define TIM_CR1_URS_Pos (2U) 14002 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) 14003 #define TIM_CR1_URS TIM_CR1_URS_Msk 14004 #define TIM_CR1_OPM_Pos (3U) 14005 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) 14006 #define TIM_CR1_OPM TIM_CR1_OPM_Msk 14007 #define TIM_CR1_DIR_Pos (4U) 14008 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) 14009 #define TIM_CR1_DIR TIM_CR1_DIR_Msk 14011 #define TIM_CR1_CMS_Pos (5U) 14012 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) 14013 #define TIM_CR1_CMS TIM_CR1_CMS_Msk 14014 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) 14015 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) 14017 #define TIM_CR1_ARPE_Pos (7U) 14018 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) 14019 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk 14021 #define TIM_CR1_CKD_Pos (8U) 14022 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) 14023 #define TIM_CR1_CKD TIM_CR1_CKD_Msk 14024 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) 14025 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) 14026 #define TIM_CR1_UIFREMAP_Pos (11U) 14027 #define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) 14028 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk 14031 #define TIM_CR2_CCPC_Pos (0U) 14032 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) 14033 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk 14034 #define TIM_CR2_CCUS_Pos (2U) 14035 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) 14036 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk 14037 #define TIM_CR2_CCDS_Pos (3U) 14038 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) 14039 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk 14041 #define TIM_CR2_OIS5_Pos (16U) 14042 #define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) 14043 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk 14044 #define TIM_CR2_OIS6_Pos (18U) 14045 #define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) 14046 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk 14048 #define TIM_CR2_MMS_Pos (4U) 14049 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) 14050 #define TIM_CR2_MMS TIM_CR2_MMS_Msk 14051 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) 14052 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) 14053 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) 14055 #define TIM_CR2_MMS2_Pos (20U) 14056 #define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) 14057 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk 14058 #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) 14059 #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) 14060 #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) 14061 #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) 14063 #define TIM_CR2_TI1S_Pos (7U) 14064 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) 14065 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk 14066 #define TIM_CR2_OIS1_Pos (8U) 14067 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) 14068 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk 14069 #define TIM_CR2_OIS1N_Pos (9U) 14070 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) 14071 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk 14072 #define TIM_CR2_OIS2_Pos (10U) 14073 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) 14074 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk 14075 #define TIM_CR2_OIS2N_Pos (11U) 14076 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) 14077 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk 14078 #define TIM_CR2_OIS3_Pos (12U) 14079 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) 14080 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk 14081 #define TIM_CR2_OIS3N_Pos (13U) 14082 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) 14083 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk 14084 #define TIM_CR2_OIS4_Pos (14U) 14085 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) 14086 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk 14089 #define TIM_SMCR_SMS_Pos (0U) 14090 #define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) 14091 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk 14092 #define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) 14093 #define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) 14094 #define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) 14095 #define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) 14097 #define TIM_SMCR_TS_Pos (4U) 14098 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) 14099 #define TIM_SMCR_TS TIM_SMCR_TS_Msk 14100 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) 14101 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) 14102 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) 14104 #define TIM_SMCR_MSM_Pos (7U) 14105 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) 14106 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk 14108 #define TIM_SMCR_ETF_Pos (8U) 14109 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) 14110 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk 14111 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) 14112 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) 14113 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) 14114 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) 14116 #define TIM_SMCR_ETPS_Pos (12U) 14117 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) 14118 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk 14119 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) 14120 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) 14122 #define TIM_SMCR_ECE_Pos (14U) 14123 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) 14124 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk 14125 #define TIM_SMCR_ETP_Pos (15U) 14126 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) 14127 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk 14130 #define TIM_DIER_UIE_Pos (0U) 14131 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) 14132 #define TIM_DIER_UIE TIM_DIER_UIE_Msk 14133 #define TIM_DIER_CC1IE_Pos (1U) 14134 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) 14135 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk 14136 #define TIM_DIER_CC2IE_Pos (2U) 14137 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) 14138 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk 14139 #define TIM_DIER_CC3IE_Pos (3U) 14140 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) 14141 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk 14142 #define TIM_DIER_CC4IE_Pos (4U) 14143 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) 14144 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk 14145 #define TIM_DIER_COMIE_Pos (5U) 14146 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) 14147 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk 14148 #define TIM_DIER_TIE_Pos (6U) 14149 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) 14150 #define TIM_DIER_TIE TIM_DIER_TIE_Msk 14151 #define TIM_DIER_BIE_Pos (7U) 14152 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) 14153 #define TIM_DIER_BIE TIM_DIER_BIE_Msk 14154 #define TIM_DIER_UDE_Pos (8U) 14155 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) 14156 #define TIM_DIER_UDE TIM_DIER_UDE_Msk 14157 #define TIM_DIER_CC1DE_Pos (9U) 14158 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) 14159 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk 14160 #define TIM_DIER_CC2DE_Pos (10U) 14161 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) 14162 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk 14163 #define TIM_DIER_CC3DE_Pos (11U) 14164 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) 14165 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk 14166 #define TIM_DIER_CC4DE_Pos (12U) 14167 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) 14168 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk 14169 #define TIM_DIER_COMDE_Pos (13U) 14170 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) 14171 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk 14172 #define TIM_DIER_TDE_Pos (14U) 14173 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) 14174 #define TIM_DIER_TDE TIM_DIER_TDE_Msk 14177 #define TIM_SR_UIF_Pos (0U) 14178 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) 14179 #define TIM_SR_UIF TIM_SR_UIF_Msk 14180 #define TIM_SR_CC1IF_Pos (1U) 14181 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) 14182 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk 14183 #define TIM_SR_CC2IF_Pos (2U) 14184 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) 14185 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk 14186 #define TIM_SR_CC3IF_Pos (3U) 14187 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) 14188 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk 14189 #define TIM_SR_CC4IF_Pos (4U) 14190 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) 14191 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk 14192 #define TIM_SR_COMIF_Pos (5U) 14193 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) 14194 #define TIM_SR_COMIF TIM_SR_COMIF_Msk 14195 #define TIM_SR_TIF_Pos (6U) 14196 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) 14197 #define TIM_SR_TIF TIM_SR_TIF_Msk 14198 #define TIM_SR_BIF_Pos (7U) 14199 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) 14200 #define TIM_SR_BIF TIM_SR_BIF_Msk 14201 #define TIM_SR_B2IF_Pos (8U) 14202 #define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) 14203 #define TIM_SR_B2IF TIM_SR_B2IF_Msk 14204 #define TIM_SR_CC1OF_Pos (9U) 14205 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) 14206 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk 14207 #define TIM_SR_CC2OF_Pos (10U) 14208 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) 14209 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk 14210 #define TIM_SR_CC3OF_Pos (11U) 14211 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) 14212 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk 14213 #define TIM_SR_CC4OF_Pos (12U) 14214 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) 14215 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk 14216 #define TIM_SR_SBIF_Pos (13U) 14217 #define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) 14218 #define TIM_SR_SBIF TIM_SR_SBIF_Msk 14219 #define TIM_SR_CC5IF_Pos (16U) 14220 #define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) 14221 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk 14222 #define TIM_SR_CC6IF_Pos (17U) 14223 #define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) 14224 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk 14227 #define TIM_EGR_UG_Pos (0U) 14228 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) 14229 #define TIM_EGR_UG TIM_EGR_UG_Msk 14230 #define TIM_EGR_CC1G_Pos (1U) 14231 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) 14232 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk 14233 #define TIM_EGR_CC2G_Pos (2U) 14234 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) 14235 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk 14236 #define TIM_EGR_CC3G_Pos (3U) 14237 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) 14238 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk 14239 #define TIM_EGR_CC4G_Pos (4U) 14240 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) 14241 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk 14242 #define TIM_EGR_COMG_Pos (5U) 14243 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) 14244 #define TIM_EGR_COMG TIM_EGR_COMG_Msk 14245 #define TIM_EGR_TG_Pos (6U) 14246 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) 14247 #define TIM_EGR_TG TIM_EGR_TG_Msk 14248 #define TIM_EGR_BG_Pos (7U) 14249 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) 14250 #define TIM_EGR_BG TIM_EGR_BG_Msk 14251 #define TIM_EGR_B2G_Pos (8U) 14252 #define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) 14253 #define TIM_EGR_B2G TIM_EGR_B2G_Msk 14256 #define TIM_CCMR1_CC1S_Pos (0U) 14257 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) 14258 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk 14259 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) 14260 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) 14262 #define TIM_CCMR1_OC1FE_Pos (2U) 14263 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) 14264 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk 14265 #define TIM_CCMR1_OC1PE_Pos (3U) 14266 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) 14267 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk 14269 #define TIM_CCMR1_OC1M_Pos (4U) 14270 #define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) 14271 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk 14272 #define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) 14273 #define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) 14274 #define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) 14275 #define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) 14277 #define TIM_CCMR1_OC1CE_Pos (7U) 14278 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) 14279 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk 14281 #define TIM_CCMR1_CC2S_Pos (8U) 14282 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) 14283 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk 14284 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) 14285 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) 14287 #define TIM_CCMR1_OC2FE_Pos (10U) 14288 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) 14289 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk 14290 #define TIM_CCMR1_OC2PE_Pos (11U) 14291 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) 14292 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk 14294 #define TIM_CCMR1_OC2M_Pos (12U) 14295 #define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) 14296 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk 14297 #define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) 14298 #define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) 14299 #define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) 14300 #define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) 14302 #define TIM_CCMR1_OC2CE_Pos (15U) 14303 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) 14304 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk 14308 #define TIM_CCMR1_IC1PSC_Pos (2U) 14309 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) 14310 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk 14311 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) 14312 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) 14314 #define TIM_CCMR1_IC1F_Pos (4U) 14315 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) 14316 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk 14317 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) 14318 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) 14319 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) 14320 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) 14322 #define TIM_CCMR1_IC2PSC_Pos (10U) 14323 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) 14324 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk 14325 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) 14326 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) 14328 #define TIM_CCMR1_IC2F_Pos (12U) 14329 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) 14330 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk 14331 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) 14332 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) 14333 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) 14334 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) 14337 #define TIM_CCMR2_CC3S_Pos (0U) 14338 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) 14339 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk 14340 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) 14341 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) 14343 #define TIM_CCMR2_OC3FE_Pos (2U) 14344 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) 14345 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk 14346 #define TIM_CCMR2_OC3PE_Pos (3U) 14347 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) 14348 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk 14350 #define TIM_CCMR2_OC3M_Pos (4U) 14351 #define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) 14352 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk 14353 #define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) 14354 #define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) 14355 #define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) 14356 #define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) 14360 #define TIM_CCMR2_OC3CE_Pos (7U) 14361 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) 14362 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk 14364 #define TIM_CCMR2_CC4S_Pos (8U) 14365 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) 14366 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk 14367 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) 14368 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) 14370 #define TIM_CCMR2_OC4FE_Pos (10U) 14371 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) 14372 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk 14373 #define TIM_CCMR2_OC4PE_Pos (11U) 14374 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) 14375 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk 14377 #define TIM_CCMR2_OC4M_Pos (12U) 14378 #define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) 14379 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk 14380 #define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) 14381 #define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) 14382 #define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) 14383 #define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) 14385 #define TIM_CCMR2_OC4CE_Pos (15U) 14386 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) 14387 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk 14391 #define TIM_CCMR2_IC3PSC_Pos (2U) 14392 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) 14393 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk 14394 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) 14395 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) 14397 #define TIM_CCMR2_IC3F_Pos (4U) 14398 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) 14399 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk 14400 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) 14401 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) 14402 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) 14403 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) 14405 #define TIM_CCMR2_IC4PSC_Pos (10U) 14406 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) 14407 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk 14408 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) 14409 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) 14411 #define TIM_CCMR2_IC4F_Pos (12U) 14412 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) 14413 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk 14414 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) 14415 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) 14416 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) 14417 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) 14420 #define TIM_CCER_CC1E_Pos (0U) 14421 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) 14422 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk 14423 #define TIM_CCER_CC1P_Pos (1U) 14424 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) 14425 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk 14426 #define TIM_CCER_CC1NE_Pos (2U) 14427 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) 14428 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk 14429 #define TIM_CCER_CC1NP_Pos (3U) 14430 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) 14431 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk 14432 #define TIM_CCER_CC2E_Pos (4U) 14433 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) 14434 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk 14435 #define TIM_CCER_CC2P_Pos (5U) 14436 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) 14437 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk 14438 #define TIM_CCER_CC2NE_Pos (6U) 14439 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) 14440 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk 14441 #define TIM_CCER_CC2NP_Pos (7U) 14442 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) 14443 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk 14444 #define TIM_CCER_CC3E_Pos (8U) 14445 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) 14446 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk 14447 #define TIM_CCER_CC3P_Pos (9U) 14448 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) 14449 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk 14450 #define TIM_CCER_CC3NE_Pos (10U) 14451 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) 14452 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk 14453 #define TIM_CCER_CC3NP_Pos (11U) 14454 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) 14455 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk 14456 #define TIM_CCER_CC4E_Pos (12U) 14457 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) 14458 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk 14459 #define TIM_CCER_CC4P_Pos (13U) 14460 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) 14461 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk 14462 #define TIM_CCER_CC4NP_Pos (15U) 14463 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) 14464 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk 14465 #define TIM_CCER_CC5E_Pos (16U) 14466 #define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) 14467 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk 14468 #define TIM_CCER_CC5P_Pos (17U) 14469 #define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) 14470 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk 14471 #define TIM_CCER_CC6E_Pos (20U) 14472 #define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) 14473 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk 14474 #define TIM_CCER_CC6P_Pos (21U) 14475 #define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) 14476 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk 14480 #define TIM_CNT_CNT_Pos (0U) 14481 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) 14482 #define TIM_CNT_CNT TIM_CNT_CNT_Msk 14483 #define TIM_CNT_UIFCPY_Pos (31U) 14484 #define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) 14485 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk 14488 #define TIM_PSC_PSC_Pos (0U) 14489 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) 14490 #define TIM_PSC_PSC TIM_PSC_PSC_Msk 14493 #define TIM_ARR_ARR_Pos (0U) 14494 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) 14495 #define TIM_ARR_ARR TIM_ARR_ARR_Msk 14498 #define TIM_RCR_REP_Pos (0U) 14499 #define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) 14500 #define TIM_RCR_REP TIM_RCR_REP_Msk 14503 #define TIM_CCR1_CCR1_Pos (0U) 14504 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) 14505 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk 14508 #define TIM_CCR2_CCR2_Pos (0U) 14509 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) 14510 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk 14513 #define TIM_CCR3_CCR3_Pos (0U) 14514 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) 14515 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk 14518 #define TIM_CCR4_CCR4_Pos (0U) 14519 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) 14520 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk 14523 #define TIM_BDTR_DTG_Pos (0U) 14524 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) 14525 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk 14526 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) 14527 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) 14528 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) 14529 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) 14530 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) 14531 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) 14532 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) 14533 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) 14535 #define TIM_BDTR_LOCK_Pos (8U) 14536 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) 14537 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk 14538 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) 14539 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) 14541 #define TIM_BDTR_OSSI_Pos (10U) 14542 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) 14543 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk 14544 #define TIM_BDTR_OSSR_Pos (11U) 14545 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) 14546 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk 14547 #define TIM_BDTR_BKE_Pos (12U) 14548 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) 14549 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk 14550 #define TIM_BDTR_BKP_Pos (13U) 14551 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) 14552 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk 14553 #define TIM_BDTR_AOE_Pos (14U) 14554 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) 14555 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk 14556 #define TIM_BDTR_MOE_Pos (15U) 14557 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) 14558 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk 14559 #define TIM_BDTR_BKF_Pos (16U) 14560 #define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) 14561 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk 14562 #define TIM_BDTR_BK2F_Pos (20U) 14563 #define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) 14564 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk 14565 #define TIM_BDTR_BK2E_Pos (24U) 14566 #define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) 14567 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk 14568 #define TIM_BDTR_BK2P_Pos (25U) 14569 #define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) 14570 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk 14573 #define TIM_DCR_DBA_Pos (0U) 14574 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) 14575 #define TIM_DCR_DBA TIM_DCR_DBA_Msk 14576 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) 14577 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) 14578 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) 14579 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) 14580 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) 14582 #define TIM_DCR_DBL_Pos (8U) 14583 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) 14584 #define TIM_DCR_DBL TIM_DCR_DBL_Msk 14585 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) 14586 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) 14587 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) 14588 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) 14589 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) 14592 #define TIM_DMAR_DMAB_Pos (0U) 14593 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) 14594 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk 14597 #define TIM_OR_TI4_RMP_Pos (6U) 14598 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) 14599 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk 14600 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) 14601 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) 14602 #define TIM_OR_ITR1_RMP_Pos (10U) 14603 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) 14604 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk 14605 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) 14606 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) 14609 #define TIM2_OR_ITR1_RMP_Pos (10U) 14610 #define TIM2_OR_ITR1_RMP_Msk (0x3U << TIM2_OR_ITR1_RMP_Pos) 14611 #define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk 14612 #define TIM2_OR_ITR1_RMP_0 (0x1U << TIM2_OR_ITR1_RMP_Pos) 14613 #define TIM2_OR_ITR1_RMP_1 (0x2U << TIM2_OR_ITR1_RMP_Pos) 14616 #define TIM5_OR_TI4_RMP_Pos (6U) 14617 #define TIM5_OR_TI4_RMP_Msk (0x3U << TIM5_OR_TI4_RMP_Pos) 14618 #define TIM5_OR_TI4_RMP TIM5_OR_TI4_RMP_Msk 14619 #define TIM5_OR_TI4_RMP_0 (0x1U << TIM5_OR_TI4_RMP_Pos) 14620 #define TIM5_OR_TI4_RMP_1 (0x2U << TIM5_OR_TI4_RMP_Pos) 14623 #define TIM11_OR_TI1_RMP_Pos (0U) 14624 #define TIM11_OR_TI1_RMP_Msk (0x3U << TIM11_OR_TI1_RMP_Pos) 14625 #define TIM11_OR_TI1_RMP TIM11_OR_TI1_RMP_Msk 14626 #define TIM11_OR_TI1_RMP_0 (0x1U << TIM11_OR_TI1_RMP_Pos) 14627 #define TIM11_OR_TI1_RMP_1 (0x2U << TIM11_OR_TI1_RMP_Pos) 14630 #define TIM_CCMR3_OC5FE_Pos (2U) 14631 #define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) 14632 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk 14633 #define TIM_CCMR3_OC5PE_Pos (3U) 14634 #define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) 14635 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk 14637 #define TIM_CCMR3_OC5M_Pos (4U) 14638 #define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) 14639 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk 14640 #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) 14641 #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) 14642 #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) 14643 #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) 14645 #define TIM_CCMR3_OC5CE_Pos (7U) 14646 #define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) 14647 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk 14649 #define TIM_CCMR3_OC6FE_Pos (10U) 14650 #define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) 14651 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk 14652 #define TIM_CCMR3_OC6PE_Pos (11U) 14653 #define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) 14654 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk 14656 #define TIM_CCMR3_OC6M_Pos (12U) 14657 #define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) 14658 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk 14659 #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) 14660 #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) 14661 #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) 14662 #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) 14664 #define TIM_CCMR3_OC6CE_Pos (15U) 14665 #define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) 14666 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk 14669 #define TIM_CCR5_CCR5_Pos (0U) 14670 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) 14671 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk 14672 #define TIM_CCR5_GC5C1_Pos (29U) 14673 #define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) 14674 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk 14675 #define TIM_CCR5_GC5C2_Pos (30U) 14676 #define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) 14677 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk 14678 #define TIM_CCR5_GC5C3_Pos (31U) 14679 #define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) 14680 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk 14683 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU) 14686 #define TIM1_AF1_BKINE_Pos (0U) 14687 #define TIM1_AF1_BKINE_Msk (0x1U << TIM1_AF1_BKINE_Pos) 14688 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk 14689 #define TIM1_AF1_BKDF1BKE_Pos (8U) 14690 #define TIM1_AF1_BKDF1BKE_Msk (0x1U << TIM1_AF1_BKDF1BKE_Pos) 14691 #define TIM1_AF1_BKDF1BKE TIM1_AF1_BKDF1BKE_Msk 14692 #define TIM1_AF1_BKINP_Pos (9U) 14693 #define TIM1_AF1_BKINP_Msk (0x1U << TIM1_AF1_BKINP_Pos) 14694 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk 14697 #define TIM1_AF2_BK2INE_Pos (0U) 14698 #define TIM1_AF2_BK2INE_Msk (0x1U << TIM1_AF2_BK2INE_Pos) 14699 #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk 14700 #define TIM1_AF2_BK2DF1BKE_Pos (8U) 14701 #define TIM1_AF2_BK2DF1BKE_Msk (0x1U << TIM1_AF2_BK2DF1BKE_Pos) 14702 #define TIM1_AF2_BK2DF1BKE TIM1_AF2_BK2DF1BKE_Msk 14703 #define TIM1_AF2_BK2INP_Pos (9U) 14704 #define TIM1_AF2_BK2INP_Msk (0x1U << TIM1_AF2_BK2INP_Pos) 14705 #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk 14708 #define TIM8_AF1_BKINE_Pos (0U) 14709 #define TIM8_AF1_BKINE_Msk (0x1U << TIM8_AF1_BKINE_Pos) 14710 #define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk 14711 #define TIM8_AF1_BKDF1BKE_Pos (8U) 14712 #define TIM8_AF1_BKDF1BKE_Msk (0x1U << TIM8_AF1_BKDF1BKE_Pos) 14713 #define TIM8_AF1_BKDF1BKE TIM8_AF1_BKDF1BKE_Msk 14714 #define TIM8_AF1_BKINP_Pos (9U) 14715 #define TIM8_AF1_BKINP_Msk (0x1U << TIM8_AF1_BKINP_Pos) 14716 #define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk 14719 #define TIM8_AF2_BK2INE_Pos (0U) 14720 #define TIM8_AF2_BK2INE_Msk (0x1U << TIM8_AF2_BK2INE_Pos) 14721 #define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk 14722 #define TIM8_AF2_BK2DF1BKE_Pos (8U) 14723 #define TIM8_AF2_BK2DF1BKE_Msk (0x1U << TIM8_AF2_BK2DF1BKE_Pos) 14724 #define TIM8_AF2_BK2DF1BKE TIM8_AF2_BK2DF1BKE_Msk 14725 #define TIM8_AF2_BK2INP_Pos (9U) 14726 #define TIM8_AF2_BK2INP_Msk (0x1U << TIM8_AF2_BK2INP_Pos) 14727 #define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk 14736 #define LPTIM_ISR_CMPM_Pos (0U) 14737 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) 14738 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk 14739 #define LPTIM_ISR_ARRM_Pos (1U) 14740 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) 14741 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk 14742 #define LPTIM_ISR_EXTTRIG_Pos (2U) 14743 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) 14744 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk 14745 #define LPTIM_ISR_CMPOK_Pos (3U) 14746 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) 14747 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk 14748 #define LPTIM_ISR_ARROK_Pos (4U) 14749 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) 14750 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk 14751 #define LPTIM_ISR_UP_Pos (5U) 14752 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) 14753 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk 14754 #define LPTIM_ISR_DOWN_Pos (6U) 14755 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) 14756 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk 14759 #define LPTIM_ICR_CMPMCF_Pos (0U) 14760 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) 14761 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk 14762 #define LPTIM_ICR_ARRMCF_Pos (1U) 14763 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) 14764 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk 14765 #define LPTIM_ICR_EXTTRIGCF_Pos (2U) 14766 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) 14767 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk 14768 #define LPTIM_ICR_CMPOKCF_Pos (3U) 14769 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) 14770 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk 14771 #define LPTIM_ICR_ARROKCF_Pos (4U) 14772 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) 14773 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk 14774 #define LPTIM_ICR_UPCF_Pos (5U) 14775 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) 14776 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk 14777 #define LPTIM_ICR_DOWNCF_Pos (6U) 14778 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) 14779 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk 14782 #define LPTIM_IER_CMPMIE_Pos (0U) 14783 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) 14784 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk 14785 #define LPTIM_IER_ARRMIE_Pos (1U) 14786 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) 14787 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk 14788 #define LPTIM_IER_EXTTRIGIE_Pos (2U) 14789 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) 14790 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk 14791 #define LPTIM_IER_CMPOKIE_Pos (3U) 14792 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) 14793 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk 14794 #define LPTIM_IER_ARROKIE_Pos (4U) 14795 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) 14796 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk 14797 #define LPTIM_IER_UPIE_Pos (5U) 14798 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) 14799 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk 14800 #define LPTIM_IER_DOWNIE_Pos (6U) 14801 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) 14802 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk 14805 #define LPTIM_CFGR_CKSEL_Pos (0U) 14806 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) 14807 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk 14809 #define LPTIM_CFGR_CKPOL_Pos (1U) 14810 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) 14811 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk 14812 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) 14813 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) 14815 #define LPTIM_CFGR_CKFLT_Pos (3U) 14816 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) 14817 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk 14818 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) 14819 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) 14821 #define LPTIM_CFGR_TRGFLT_Pos (6U) 14822 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) 14823 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk 14824 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) 14825 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) 14827 #define LPTIM_CFGR_PRESC_Pos (9U) 14828 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) 14829 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk 14830 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) 14831 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) 14832 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) 14834 #define LPTIM_CFGR_TRIGSEL_Pos (13U) 14835 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) 14836 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk 14837 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) 14838 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) 14839 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) 14841 #define LPTIM_CFGR_TRIGEN_Pos (17U) 14842 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) 14843 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk 14844 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) 14845 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) 14847 #define LPTIM_CFGR_TIMOUT_Pos (19U) 14848 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) 14849 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk 14850 #define LPTIM_CFGR_WAVE_Pos (20U) 14851 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) 14852 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk 14853 #define LPTIM_CFGR_WAVPOL_Pos (21U) 14854 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) 14855 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk 14856 #define LPTIM_CFGR_PRELOAD_Pos (22U) 14857 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) 14858 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk 14859 #define LPTIM_CFGR_COUNTMODE_Pos (23U) 14860 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) 14861 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk 14862 #define LPTIM_CFGR_ENC_Pos (24U) 14863 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) 14864 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk 14867 #define LPTIM_CR_ENABLE_Pos (0U) 14868 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) 14869 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk 14870 #define LPTIM_CR_SNGSTRT_Pos (1U) 14871 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) 14872 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk 14873 #define LPTIM_CR_CNTSTRT_Pos (2U) 14874 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) 14875 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk 14878 #define LPTIM_CMP_CMP_Pos (0U) 14879 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) 14880 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk 14883 #define LPTIM_ARR_ARR_Pos (0U) 14884 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) 14885 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk 14888 #define LPTIM_CNT_CNT_Pos (0U) 14889 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) 14890 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk 14897 #define USART_CR1_UE_Pos (0U) 14898 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) 14899 #define USART_CR1_UE USART_CR1_UE_Msk 14900 #define USART_CR1_RE_Pos (2U) 14901 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) 14902 #define USART_CR1_RE USART_CR1_RE_Msk 14903 #define USART_CR1_TE_Pos (3U) 14904 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) 14905 #define USART_CR1_TE USART_CR1_TE_Msk 14906 #define USART_CR1_IDLEIE_Pos (4U) 14907 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) 14908 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk 14909 #define USART_CR1_RXNEIE_Pos (5U) 14910 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) 14911 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk 14912 #define USART_CR1_TCIE_Pos (6U) 14913 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) 14914 #define USART_CR1_TCIE USART_CR1_TCIE_Msk 14915 #define USART_CR1_TXEIE_Pos (7U) 14916 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) 14917 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk 14918 #define USART_CR1_PEIE_Pos (8U) 14919 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) 14920 #define USART_CR1_PEIE USART_CR1_PEIE_Msk 14921 #define USART_CR1_PS_Pos (9U) 14922 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) 14923 #define USART_CR1_PS USART_CR1_PS_Msk 14924 #define USART_CR1_PCE_Pos (10U) 14925 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) 14926 #define USART_CR1_PCE USART_CR1_PCE_Msk 14927 #define USART_CR1_WAKE_Pos (11U) 14928 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) 14929 #define USART_CR1_WAKE USART_CR1_WAKE_Msk 14930 #define USART_CR1_M_Pos (12U) 14931 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) 14932 #define USART_CR1_M USART_CR1_M_Msk 14933 #define USART_CR1_M0 (0x00001U << USART_CR1_M_Pos) 14934 #define USART_CR1_MME_Pos (13U) 14935 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) 14936 #define USART_CR1_MME USART_CR1_MME_Msk 14937 #define USART_CR1_CMIE_Pos (14U) 14938 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) 14939 #define USART_CR1_CMIE USART_CR1_CMIE_Msk 14940 #define USART_CR1_OVER8_Pos (15U) 14941 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) 14942 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk 14943 #define USART_CR1_DEDT_Pos (16U) 14944 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) 14945 #define USART_CR1_DEDT USART_CR1_DEDT_Msk 14946 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) 14947 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) 14948 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) 14949 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) 14950 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) 14951 #define USART_CR1_DEAT_Pos (21U) 14952 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) 14953 #define USART_CR1_DEAT USART_CR1_DEAT_Msk 14954 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) 14955 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) 14956 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) 14957 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) 14958 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) 14959 #define USART_CR1_RTOIE_Pos (26U) 14960 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) 14961 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk 14962 #define USART_CR1_EOBIE_Pos (27U) 14963 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) 14964 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk 14965 #define USART_CR1_M1 0x10000000U 14968 #define USART_CR1_M_0 USART_CR1_M0 14969 #define USART_CR1_M_1 USART_CR1_M1 14972 #define USART_CR2_ADDM7_Pos (4U) 14973 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) 14974 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk 14975 #define USART_CR2_LBDL_Pos (5U) 14976 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) 14977 #define USART_CR2_LBDL USART_CR2_LBDL_Msk 14978 #define USART_CR2_LBDIE_Pos (6U) 14979 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) 14980 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk 14981 #define USART_CR2_LBCL_Pos (8U) 14982 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) 14983 #define USART_CR2_LBCL USART_CR2_LBCL_Msk 14984 #define USART_CR2_CPHA_Pos (9U) 14985 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) 14986 #define USART_CR2_CPHA USART_CR2_CPHA_Msk 14987 #define USART_CR2_CPOL_Pos (10U) 14988 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) 14989 #define USART_CR2_CPOL USART_CR2_CPOL_Msk 14990 #define USART_CR2_CLKEN_Pos (11U) 14991 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) 14992 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk 14993 #define USART_CR2_STOP_Pos (12U) 14994 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) 14995 #define USART_CR2_STOP USART_CR2_STOP_Msk 14996 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) 14997 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) 14998 #define USART_CR2_LINEN_Pos (14U) 14999 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) 15000 #define USART_CR2_LINEN USART_CR2_LINEN_Msk 15001 #define USART_CR2_SWAP_Pos (15U) 15002 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) 15003 #define USART_CR2_SWAP USART_CR2_SWAP_Msk 15004 #define USART_CR2_RXINV_Pos (16U) 15005 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) 15006 #define USART_CR2_RXINV USART_CR2_RXINV_Msk 15007 #define USART_CR2_TXINV_Pos (17U) 15008 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) 15009 #define USART_CR2_TXINV USART_CR2_TXINV_Msk 15010 #define USART_CR2_DATAINV_Pos (18U) 15011 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) 15012 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk 15013 #define USART_CR2_MSBFIRST_Pos (19U) 15014 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) 15015 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk 15016 #define USART_CR2_ABREN_Pos (20U) 15017 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) 15018 #define USART_CR2_ABREN USART_CR2_ABREN_Msk 15019 #define USART_CR2_ABRMODE_Pos (21U) 15020 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) 15021 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk 15022 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) 15023 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) 15024 #define USART_CR2_RTOEN_Pos (23U) 15025 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) 15026 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk 15027 #define USART_CR2_ADD_Pos (24U) 15028 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) 15029 #define USART_CR2_ADD USART_CR2_ADD_Msk 15032 #define USART_CR3_EIE_Pos (0U) 15033 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) 15034 #define USART_CR3_EIE USART_CR3_EIE_Msk 15035 #define USART_CR3_IREN_Pos (1U) 15036 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) 15037 #define USART_CR3_IREN USART_CR3_IREN_Msk 15038 #define USART_CR3_IRLP_Pos (2U) 15039 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) 15040 #define USART_CR3_IRLP USART_CR3_IRLP_Msk 15041 #define USART_CR3_HDSEL_Pos (3U) 15042 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) 15043 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk 15044 #define USART_CR3_NACK_Pos (4U) 15045 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) 15046 #define USART_CR3_NACK USART_CR3_NACK_Msk 15047 #define USART_CR3_SCEN_Pos (5U) 15048 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) 15049 #define USART_CR3_SCEN USART_CR3_SCEN_Msk 15050 #define USART_CR3_DMAR_Pos (6U) 15051 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) 15052 #define USART_CR3_DMAR USART_CR3_DMAR_Msk 15053 #define USART_CR3_DMAT_Pos (7U) 15054 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) 15055 #define USART_CR3_DMAT USART_CR3_DMAT_Msk 15056 #define USART_CR3_RTSE_Pos (8U) 15057 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) 15058 #define USART_CR3_RTSE USART_CR3_RTSE_Msk 15059 #define USART_CR3_CTSE_Pos (9U) 15060 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) 15061 #define USART_CR3_CTSE USART_CR3_CTSE_Msk 15062 #define USART_CR3_CTSIE_Pos (10U) 15063 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) 15064 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk 15065 #define USART_CR3_ONEBIT_Pos (11U) 15066 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) 15067 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk 15068 #define USART_CR3_OVRDIS_Pos (12U) 15069 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) 15070 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk 15071 #define USART_CR3_DDRE_Pos (13U) 15072 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) 15073 #define USART_CR3_DDRE USART_CR3_DDRE_Msk 15074 #define USART_CR3_DEM_Pos (14U) 15075 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) 15076 #define USART_CR3_DEM USART_CR3_DEM_Msk 15077 #define USART_CR3_DEP_Pos (15U) 15078 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) 15079 #define USART_CR3_DEP USART_CR3_DEP_Msk 15080 #define USART_CR3_SCARCNT_Pos (17U) 15081 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) 15082 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk 15083 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) 15084 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) 15085 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) 15088 #define USART_BRR_DIV_FRACTION_Pos (0U) 15089 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) 15090 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk 15091 #define USART_BRR_DIV_MANTISSA_Pos (4U) 15092 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) 15093 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk 15096 #define USART_GTPR_PSC_Pos (0U) 15097 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) 15098 #define USART_GTPR_PSC USART_GTPR_PSC_Msk 15099 #define USART_GTPR_GT_Pos (8U) 15100 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) 15101 #define USART_GTPR_GT USART_GTPR_GT_Msk 15105 #define USART_RTOR_RTO_Pos (0U) 15106 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) 15107 #define USART_RTOR_RTO USART_RTOR_RTO_Msk 15108 #define USART_RTOR_BLEN_Pos (24U) 15109 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) 15110 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk 15113 #define USART_RQR_ABRRQ_Pos (0U) 15114 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) 15115 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk 15116 #define USART_RQR_SBKRQ_Pos (1U) 15117 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) 15118 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk 15119 #define USART_RQR_MMRQ_Pos (2U) 15120 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) 15121 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk 15122 #define USART_RQR_RXFRQ_Pos (3U) 15123 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) 15124 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk 15125 #define USART_RQR_TXFRQ_Pos (4U) 15126 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) 15127 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk 15130 #define USART_ISR_PE_Pos (0U) 15131 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) 15132 #define USART_ISR_PE USART_ISR_PE_Msk 15133 #define USART_ISR_FE_Pos (1U) 15134 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) 15135 #define USART_ISR_FE USART_ISR_FE_Msk 15136 #define USART_ISR_NE_Pos (2U) 15137 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) 15138 #define USART_ISR_NE USART_ISR_NE_Msk 15139 #define USART_ISR_ORE_Pos (3U) 15140 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) 15141 #define USART_ISR_ORE USART_ISR_ORE_Msk 15142 #define USART_ISR_IDLE_Pos (4U) 15143 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) 15144 #define USART_ISR_IDLE USART_ISR_IDLE_Msk 15145 #define USART_ISR_RXNE_Pos (5U) 15146 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) 15147 #define USART_ISR_RXNE USART_ISR_RXNE_Msk 15148 #define USART_ISR_TC_Pos (6U) 15149 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) 15150 #define USART_ISR_TC USART_ISR_TC_Msk 15151 #define USART_ISR_TXE_Pos (7U) 15152 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) 15153 #define USART_ISR_TXE USART_ISR_TXE_Msk 15154 #define USART_ISR_LBDF_Pos (8U) 15155 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) 15156 #define USART_ISR_LBDF USART_ISR_LBDF_Msk 15157 #define USART_ISR_CTSIF_Pos (9U) 15158 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) 15159 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk 15160 #define USART_ISR_CTS_Pos (10U) 15161 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) 15162 #define USART_ISR_CTS USART_ISR_CTS_Msk 15163 #define USART_ISR_RTOF_Pos (11U) 15164 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) 15165 #define USART_ISR_RTOF USART_ISR_RTOF_Msk 15166 #define USART_ISR_EOBF_Pos (12U) 15167 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) 15168 #define USART_ISR_EOBF USART_ISR_EOBF_Msk 15169 #define USART_ISR_ABRE_Pos (14U) 15170 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) 15171 #define USART_ISR_ABRE USART_ISR_ABRE_Msk 15172 #define USART_ISR_ABRF_Pos (15U) 15173 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) 15174 #define USART_ISR_ABRF USART_ISR_ABRF_Msk 15175 #define USART_ISR_BUSY_Pos (16U) 15176 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) 15177 #define USART_ISR_BUSY USART_ISR_BUSY_Msk 15178 #define USART_ISR_CMF_Pos (17U) 15179 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) 15180 #define USART_ISR_CMF USART_ISR_CMF_Msk 15181 #define USART_ISR_SBKF_Pos (18U) 15182 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) 15183 #define USART_ISR_SBKF USART_ISR_SBKF_Msk 15184 #define USART_ISR_RWU_Pos (19U) 15185 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) 15186 #define USART_ISR_RWU USART_ISR_RWU_Msk 15187 #define USART_ISR_TEACK_Pos (21U) 15188 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) 15189 #define USART_ISR_TEACK USART_ISR_TEACK_Msk 15192 #define USART_ICR_PECF_Pos (0U) 15193 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) 15194 #define USART_ICR_PECF USART_ICR_PECF_Msk 15195 #define USART_ICR_FECF_Pos (1U) 15196 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) 15197 #define USART_ICR_FECF USART_ICR_FECF_Msk 15198 #define USART_ICR_NCF_Pos (2U) 15199 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) 15200 #define USART_ICR_NCF USART_ICR_NCF_Msk 15201 #define USART_ICR_ORECF_Pos (3U) 15202 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) 15203 #define USART_ICR_ORECF USART_ICR_ORECF_Msk 15204 #define USART_ICR_IDLECF_Pos (4U) 15205 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) 15206 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk 15207 #define USART_ICR_TCCF_Pos (6U) 15208 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) 15209 #define USART_ICR_TCCF USART_ICR_TCCF_Msk 15210 #define USART_ICR_LBDCF_Pos (8U) 15211 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) 15212 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk 15213 #define USART_ICR_CTSCF_Pos (9U) 15214 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) 15215 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk 15216 #define USART_ICR_RTOCF_Pos (11U) 15217 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) 15218 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk 15219 #define USART_ICR_EOBCF_Pos (12U) 15220 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) 15221 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk 15222 #define USART_ICR_CMCF_Pos (17U) 15223 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) 15224 #define USART_ICR_CMCF USART_ICR_CMCF_Msk 15227 #define USART_RDR_RDR_Pos (0U) 15228 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) 15229 #define USART_RDR_RDR USART_RDR_RDR_Msk 15232 #define USART_TDR_TDR_Pos (0U) 15233 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) 15234 #define USART_TDR_TDR USART_TDR_TDR_Msk 15242 #define WWDG_CR_T_Pos (0U) 15243 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) 15244 #define WWDG_CR_T WWDG_CR_T_Msk 15245 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) 15246 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) 15247 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) 15248 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) 15249 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) 15250 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) 15251 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) 15254 #define WWDG_CR_WDGA_Pos (7U) 15255 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) 15256 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk 15259 #define WWDG_CFR_W_Pos (0U) 15260 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) 15261 #define WWDG_CFR_W WWDG_CFR_W_Msk 15262 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) 15263 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) 15264 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) 15265 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) 15266 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) 15267 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) 15268 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) 15271 #define WWDG_CFR_WDGTB_Pos (7U) 15272 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) 15273 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk 15274 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) 15275 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) 15278 #define WWDG_CFR_EWI_Pos (9U) 15279 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) 15280 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk 15283 #define WWDG_SR_EWIF_Pos (0U) 15284 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) 15285 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk 15293 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 15294 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) 15295 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk 15296 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 15297 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) 15298 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk 15301 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 15302 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) 15303 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk 15304 #define DBGMCU_CR_DBG_STOP_Pos (1U) 15305 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) 15306 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk 15307 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 15308 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) 15309 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk 15310 #define DBGMCU_CR_TRACE_IOEN_Pos (5U) 15311 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) 15312 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk 15314 #define DBGMCU_CR_TRACE_MODE_Pos (6U) 15315 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) 15316 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk 15317 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) 15318 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) 15321 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) 15322 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) 15323 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk 15324 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) 15325 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) 15326 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk 15327 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U) 15328 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) 15329 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk 15330 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U) 15331 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) 15332 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk 15333 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) 15334 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) 15335 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk 15336 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) 15337 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) 15338 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk 15339 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U) 15340 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) 15341 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk 15342 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U) 15343 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) 15344 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk 15345 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U) 15346 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) 15347 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk 15348 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos (9U) 15349 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos) 15350 #define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk 15351 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) 15352 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) 15353 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk 15354 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) 15355 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) 15356 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk 15357 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) 15358 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) 15359 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk 15360 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos (13U) 15361 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos) 15362 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk 15363 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) 15364 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) 15365 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk 15366 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U) 15367 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) 15368 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk 15369 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U) 15370 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) 15371 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk 15372 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U) 15373 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) 15374 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk 15375 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U) 15376 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) 15377 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk 15378 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U) 15379 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) 15380 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk 15383 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U) 15384 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) 15385 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk 15386 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U) 15387 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) 15388 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk 15389 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U) 15390 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) 15391 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk 15392 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U) 15393 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) 15394 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk 15395 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U) 15396 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) 15397 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk 15405 #define ETH_MACCR_WD_Pos (23U) 15406 #define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) 15407 #define ETH_MACCR_WD ETH_MACCR_WD_Msk 15408 #define ETH_MACCR_JD_Pos (22U) 15409 #define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) 15410 #define ETH_MACCR_JD ETH_MACCR_JD_Msk 15411 #define ETH_MACCR_IFG_Pos (17U) 15412 #define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) 15413 #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk 15414 #define ETH_MACCR_IFG_96Bit 0x00000000U 15415 #define ETH_MACCR_IFG_88Bit 0x00020000U 15416 #define ETH_MACCR_IFG_80Bit 0x00040000U 15417 #define ETH_MACCR_IFG_72Bit 0x00060000U 15418 #define ETH_MACCR_IFG_64Bit 0x00080000U 15419 #define ETH_MACCR_IFG_56Bit 0x000A0000U 15420 #define ETH_MACCR_IFG_48Bit 0x000C0000U 15421 #define ETH_MACCR_IFG_40Bit 0x000E0000U 15422 #define ETH_MACCR_CSD_Pos (16U) 15423 #define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) 15424 #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk 15425 #define ETH_MACCR_FES_Pos (14U) 15426 #define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) 15427 #define ETH_MACCR_FES ETH_MACCR_FES_Msk 15428 #define ETH_MACCR_ROD_Pos (13U) 15429 #define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) 15430 #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk 15431 #define ETH_MACCR_LM_Pos (12U) 15432 #define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) 15433 #define ETH_MACCR_LM ETH_MACCR_LM_Msk 15434 #define ETH_MACCR_DM_Pos (11U) 15435 #define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) 15436 #define ETH_MACCR_DM ETH_MACCR_DM_Msk 15437 #define ETH_MACCR_IPCO_Pos (10U) 15438 #define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) 15439 #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk 15440 #define ETH_MACCR_RD_Pos (9U) 15441 #define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) 15442 #define ETH_MACCR_RD ETH_MACCR_RD_Msk 15443 #define ETH_MACCR_APCS_Pos (7U) 15444 #define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) 15445 #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk 15446 #define ETH_MACCR_BL_Pos (5U) 15447 #define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) 15448 #define ETH_MACCR_BL ETH_MACCR_BL_Msk 15450 #define ETH_MACCR_BL_10 0x00000000U 15451 #define ETH_MACCR_BL_8 0x00000020U 15452 #define ETH_MACCR_BL_4 0x00000040U 15453 #define ETH_MACCR_BL_1 0x00000060U 15454 #define ETH_MACCR_DC_Pos (4U) 15455 #define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) 15456 #define ETH_MACCR_DC ETH_MACCR_DC_Msk 15457 #define ETH_MACCR_TE_Pos (3U) 15458 #define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) 15459 #define ETH_MACCR_TE ETH_MACCR_TE_Msk 15460 #define ETH_MACCR_RE_Pos (2U) 15461 #define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) 15462 #define ETH_MACCR_RE ETH_MACCR_RE_Msk 15465 #define ETH_MACFFR_RA_Pos (31U) 15466 #define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) 15467 #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk 15468 #define ETH_MACFFR_HPF_Pos (10U) 15469 #define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) 15470 #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk 15471 #define ETH_MACFFR_SAF_Pos (9U) 15472 #define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) 15473 #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk 15474 #define ETH_MACFFR_SAIF_Pos (8U) 15475 #define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) 15476 #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk 15477 #define ETH_MACFFR_PCF_Pos (6U) 15478 #define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) 15479 #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk 15480 #define ETH_MACFFR_PCF_BlockAll_Pos (6U) 15481 #define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) 15482 #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk 15483 #define ETH_MACFFR_PCF_ForwardAll_Pos (7U) 15484 #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) 15485 #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk 15486 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U) 15487 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) 15488 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk 15489 #define ETH_MACFFR_BFD_Pos (5U) 15490 #define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) 15491 #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk 15492 #define ETH_MACFFR_PAM_Pos (4U) 15493 #define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) 15494 #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk 15495 #define ETH_MACFFR_DAIF_Pos (3U) 15496 #define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) 15497 #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk 15498 #define ETH_MACFFR_HM_Pos (2U) 15499 #define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) 15500 #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk 15501 #define ETH_MACFFR_HU_Pos (1U) 15502 #define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) 15503 #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk 15504 #define ETH_MACFFR_PM_Pos (0U) 15505 #define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) 15506 #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk 15509 #define ETH_MACHTHR_HTH_Pos (0U) 15510 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) 15511 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk 15514 #define ETH_MACHTLR_HTL_Pos (0U) 15515 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) 15516 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk 15519 #define ETH_MACMIIAR_PA_Pos (11U) 15520 #define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) 15521 #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk 15522 #define ETH_MACMIIAR_MR_Pos (6U) 15523 #define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) 15524 #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk 15525 #define ETH_MACMIIAR_CR_Pos (2U) 15526 #define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) 15527 #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk 15528 #define ETH_MACMIIAR_CR_Div42 0x00000000U 15529 #define ETH_MACMIIAR_CR_Div62_Pos (2U) 15530 #define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) 15531 #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk 15532 #define ETH_MACMIIAR_CR_Div16_Pos (3U) 15533 #define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) 15534 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk 15535 #define ETH_MACMIIAR_CR_Div26_Pos (2U) 15536 #define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) 15537 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk 15538 #define ETH_MACMIIAR_CR_Div102_Pos (4U) 15539 #define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) 15540 #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk 15541 #define ETH_MACMIIAR_MW_Pos (1U) 15542 #define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) 15543 #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk 15544 #define ETH_MACMIIAR_MB_Pos (0U) 15545 #define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) 15546 #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk 15549 #define ETH_MACMIIDR_MD_Pos (0U) 15550 #define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) 15551 #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk 15554 #define ETH_MACFCR_PT_Pos (16U) 15555 #define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) 15556 #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk 15557 #define ETH_MACFCR_ZQPD_Pos (7U) 15558 #define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) 15559 #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk 15560 #define ETH_MACFCR_PLT_Pos (4U) 15561 #define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) 15562 #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk 15563 #define ETH_MACFCR_PLT_Minus4 0x00000000U 15564 #define ETH_MACFCR_PLT_Minus28_Pos (4U) 15565 #define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) 15566 #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk 15567 #define ETH_MACFCR_PLT_Minus144_Pos (5U) 15568 #define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) 15569 #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk 15570 #define ETH_MACFCR_PLT_Minus256_Pos (4U) 15571 #define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) 15572 #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk 15573 #define ETH_MACFCR_UPFD_Pos (3U) 15574 #define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) 15575 #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk 15576 #define ETH_MACFCR_RFCE_Pos (2U) 15577 #define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) 15578 #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk 15579 #define ETH_MACFCR_TFCE_Pos (1U) 15580 #define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) 15581 #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk 15582 #define ETH_MACFCR_FCBBPA_Pos (0U) 15583 #define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) 15584 #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk 15587 #define ETH_MACVLANTR_VLANTC_Pos (16U) 15588 #define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) 15589 #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk 15590 #define ETH_MACVLANTR_VLANTI_Pos (0U) 15591 #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) 15592 #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk 15595 #define ETH_MACRWUFFR_D_Pos (0U) 15596 #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) 15597 #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk 15611 #define ETH_MACPMTCSR_WFFRPR_Pos (31U) 15612 #define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) 15613 #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk 15614 #define ETH_MACPMTCSR_GU_Pos (9U) 15615 #define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) 15616 #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk 15617 #define ETH_MACPMTCSR_WFR_Pos (6U) 15618 #define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) 15619 #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk 15620 #define ETH_MACPMTCSR_MPR_Pos (5U) 15621 #define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) 15622 #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk 15623 #define ETH_MACPMTCSR_WFE_Pos (2U) 15624 #define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) 15625 #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk 15626 #define ETH_MACPMTCSR_MPE_Pos (1U) 15627 #define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) 15628 #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk 15629 #define ETH_MACPMTCSR_PD_Pos (0U) 15630 #define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) 15631 #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk 15634 #define ETH_MACDBGR_TFF_Pos (25U) 15635 #define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) 15636 #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk 15637 #define ETH_MACDBGR_TFNE_Pos (24U) 15638 #define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) 15639 #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk 15640 #define ETH_MACDBGR_TPWA_Pos (22U) 15641 #define ETH_MACDBGR_TPWA_Msk (0x1U << ETH_MACDBGR_TPWA_Pos) 15642 #define ETH_MACDBGR_TPWA ETH_MACDBGR_TPWA_Msk 15643 #define ETH_MACDBGR_TFRS_Pos (20U) 15644 #define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) 15645 #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk 15646 #define ETH_MACDBGR_TFRS_WRITING_Pos (20U) 15647 #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) 15648 #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk 15649 #define ETH_MACDBGR_TFRS_WAITING_Pos (21U) 15650 #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) 15651 #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk 15652 #define ETH_MACDBGR_TFRS_READ_Pos (20U) 15653 #define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) 15654 #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk 15655 #define ETH_MACDBGR_TFRS_IDLE 0x00000000U 15656 #define ETH_MACDBGR_MTP_Pos (19U) 15657 #define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) 15658 #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk 15659 #define ETH_MACDBGR_MTFCS_Pos (17U) 15660 #define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) 15661 #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk 15662 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U) 15663 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) 15664 #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk 15665 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U) 15666 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) 15667 #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk 15668 #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U) 15669 #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) 15670 #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk 15671 #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U 15672 #define ETH_MACDBGR_MMTEA_Pos (16U) 15673 #define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) 15674 #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk 15675 #define ETH_MACDBGR_RFFL_Pos (8U) 15676 #define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) 15677 #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk 15678 #define ETH_MACDBGR_RFFL_FULL_Pos (8U) 15679 #define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) 15680 #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk 15681 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U) 15682 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) 15683 #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk 15684 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U) 15685 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) 15686 #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk 15687 #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U 15688 #define ETH_MACDBGR_RFRCS_Pos (5U) 15689 #define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) 15690 #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk 15691 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U) 15692 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) 15693 #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk 15694 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U) 15695 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) 15696 #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk 15697 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U) 15698 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) 15699 #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk 15700 #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U 15701 #define ETH_MACDBGR_RFWRA_Pos (4U) 15702 #define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) 15703 #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk 15704 #define ETH_MACDBGR_MSFRWCS_Pos (1U) 15705 #define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) 15706 #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk 15707 #define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) 15708 #define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) 15709 #define ETH_MACDBGR_MMRPEA_Pos (0U) 15710 #define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) 15711 #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk 15714 #define ETH_MACSR_TSTS_Pos (9U) 15715 #define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) 15716 #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk 15717 #define ETH_MACSR_MMCTS_Pos (6U) 15718 #define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) 15719 #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk 15720 #define ETH_MACSR_MMMCRS_Pos (5U) 15721 #define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) 15722 #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk 15723 #define ETH_MACSR_MMCS_Pos (4U) 15724 #define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) 15725 #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk 15726 #define ETH_MACSR_PMTS_Pos (3U) 15727 #define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) 15728 #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk 15731 #define ETH_MACIMR_TSTIM_Pos (9U) 15732 #define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) 15733 #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk 15734 #define ETH_MACIMR_PMTIM_Pos (3U) 15735 #define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) 15736 #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk 15739 #define ETH_MACA0HR_MACA0H_Pos (0U) 15740 #define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) 15741 #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk 15744 #define ETH_MACA0LR_MACA0L_Pos (0U) 15745 #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) 15746 #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk 15749 #define ETH_MACA1HR_AE_Pos (31U) 15750 #define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) 15751 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk 15752 #define ETH_MACA1HR_SA_Pos (30U) 15753 #define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) 15754 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk 15755 #define ETH_MACA1HR_MBC_Pos (24U) 15756 #define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) 15757 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk 15758 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U 15759 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U 15760 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U 15761 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U 15762 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U 15763 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U 15764 #define ETH_MACA1HR_MACA1H_Pos (0U) 15765 #define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) 15766 #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk 15769 #define ETH_MACA1LR_MACA1L_Pos (0U) 15770 #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) 15771 #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk 15774 #define ETH_MACA2HR_AE_Pos (31U) 15775 #define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) 15776 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk 15777 #define ETH_MACA2HR_SA_Pos (30U) 15778 #define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) 15779 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk 15780 #define ETH_MACA2HR_MBC_Pos (24U) 15781 #define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) 15782 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk 15783 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U 15784 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U 15785 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U 15786 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U 15787 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U 15788 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U 15789 #define ETH_MACA2HR_MACA2H_Pos (0U) 15790 #define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) 15791 #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk 15794 #define ETH_MACA2LR_MACA2L_Pos (0U) 15795 #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) 15796 #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk 15799 #define ETH_MACA3HR_AE_Pos (31U) 15800 #define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) 15801 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk 15802 #define ETH_MACA3HR_SA_Pos (30U) 15803 #define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) 15804 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk 15805 #define ETH_MACA3HR_MBC_Pos (24U) 15806 #define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) 15807 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk 15808 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U 15809 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U 15810 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U 15811 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U 15812 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U 15813 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U 15814 #define ETH_MACA3HR_MACA3H_Pos (0U) 15815 #define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) 15816 #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk 15819 #define ETH_MACA3LR_MACA3L_Pos (0U) 15820 #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) 15821 #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk 15828 #define ETH_MMCCR_MCFHP_Pos (5U) 15829 #define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) 15830 #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk 15831 #define ETH_MMCCR_MCP_Pos (4U) 15832 #define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) 15833 #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk 15834 #define ETH_MMCCR_MCF_Pos (3U) 15835 #define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) 15836 #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk 15837 #define ETH_MMCCR_ROR_Pos (2U) 15838 #define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) 15839 #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk 15840 #define ETH_MMCCR_CSR_Pos (1U) 15841 #define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) 15842 #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk 15843 #define ETH_MMCCR_CR_Pos (0U) 15844 #define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) 15845 #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk 15848 #define ETH_MMCRIR_RGUFS_Pos (17U) 15849 #define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) 15850 #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk 15851 #define ETH_MMCRIR_RFAES_Pos (6U) 15852 #define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) 15853 #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk 15854 #define ETH_MMCRIR_RFCES_Pos (5U) 15855 #define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) 15856 #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk 15859 #define ETH_MMCTIR_TGFS_Pos (21U) 15860 #define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) 15861 #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk 15862 #define ETH_MMCTIR_TGFMSCS_Pos (15U) 15863 #define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) 15864 #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk 15865 #define ETH_MMCTIR_TGFSCS_Pos (14U) 15866 #define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) 15867 #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk 15870 #define ETH_MMCRIMR_RGUFM_Pos (17U) 15871 #define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) 15872 #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk 15873 #define ETH_MMCRIMR_RFAEM_Pos (6U) 15874 #define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) 15875 #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk 15876 #define ETH_MMCRIMR_RFCEM_Pos (5U) 15877 #define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) 15878 #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk 15881 #define ETH_MMCTIMR_TGFM_Pos (21U) 15882 #define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) 15883 #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk 15884 #define ETH_MMCTIMR_TGFMSCM_Pos (15U) 15885 #define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) 15886 #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk 15887 #define ETH_MMCTIMR_TGFSCM_Pos (14U) 15888 #define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) 15889 #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk 15892 #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U) 15893 #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) 15894 #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk 15897 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U) 15898 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) 15899 #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk 15902 #define ETH_MMCTGFCR_TGFC_Pos (0U) 15903 #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) 15904 #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk 15907 #define ETH_MMCRFCECR_RFCEC_Pos (0U) 15908 #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) 15909 #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk 15912 #define ETH_MMCRFAECR_RFAEC_Pos (0U) 15913 #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) 15914 #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk 15917 #define ETH_MMCRGUFCR_RGUFC_Pos (0U) 15918 #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) 15919 #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk 15926 #define ETH_PTPTSCR_TSCNT_Pos (16U) 15927 #define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) 15928 #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk 15929 #define ETH_PTPTSSR_TSSMRME_Pos (15U) 15930 #define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) 15931 #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk 15932 #define ETH_PTPTSSR_TSSEME_Pos (14U) 15933 #define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) 15934 #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk 15935 #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U) 15936 #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) 15937 #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk 15938 #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U) 15939 #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) 15940 #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk 15941 #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U) 15942 #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) 15943 #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk 15944 #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U) 15945 #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) 15946 #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk 15947 #define ETH_PTPTSSR_TSSSR_Pos (9U) 15948 #define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) 15949 #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk 15950 #define ETH_PTPTSSR_TSSARFE_Pos (8U) 15951 #define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) 15952 #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk 15954 #define ETH_PTPTSCR_TSARU_Pos (5U) 15955 #define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) 15956 #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk 15957 #define ETH_PTPTSCR_TSITE_Pos (4U) 15958 #define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) 15959 #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk 15960 #define ETH_PTPTSCR_TSSTU_Pos (3U) 15961 #define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) 15962 #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk 15963 #define ETH_PTPTSCR_TSSTI_Pos (2U) 15964 #define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) 15965 #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk 15966 #define ETH_PTPTSCR_TSFCU_Pos (1U) 15967 #define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) 15968 #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk 15969 #define ETH_PTPTSCR_TSE_Pos (0U) 15970 #define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) 15971 #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk 15974 #define ETH_PTPSSIR_STSSI_Pos (0U) 15975 #define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) 15976 #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk 15979 #define ETH_PTPTSHR_STS_Pos (0U) 15980 #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) 15981 #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk 15984 #define ETH_PTPTSLR_STPNS_Pos (31U) 15985 #define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) 15986 #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk 15987 #define ETH_PTPTSLR_STSS_Pos (0U) 15988 #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) 15989 #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk 15992 #define ETH_PTPTSHUR_TSUS_Pos (0U) 15993 #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) 15994 #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk 15997 #define ETH_PTPTSLUR_TSUPNS_Pos (31U) 15998 #define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) 15999 #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk 16000 #define ETH_PTPTSLUR_TSUSS_Pos (0U) 16001 #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) 16002 #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk 16005 #define ETH_PTPTSAR_TSA_Pos (0U) 16006 #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) 16007 #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk 16010 #define ETH_PTPTTHR_TTSH_Pos (0U) 16011 #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) 16012 #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk 16015 #define ETH_PTPTTLR_TTSL_Pos (0U) 16016 #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) 16017 #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk 16020 #define ETH_PTPTSSR_TSTTR_Pos (5U) 16021 #define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) 16022 #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk 16023 #define ETH_PTPTSSR_TSSO_Pos (4U) 16024 #define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) 16025 #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk 16032 #define ETH_DMABMR_AAB_Pos (25U) 16033 #define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) 16034 #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk 16035 #define ETH_DMABMR_FPM_Pos (24U) 16036 #define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) 16037 #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk 16038 #define ETH_DMABMR_USP_Pos (23U) 16039 #define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) 16040 #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk 16041 #define ETH_DMABMR_RDP_Pos (17U) 16042 #define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) 16043 #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk 16044 #define ETH_DMABMR_RDP_1Beat 0x00020000U 16045 #define ETH_DMABMR_RDP_2Beat 0x00040000U 16046 #define ETH_DMABMR_RDP_4Beat 0x00080000U 16047 #define ETH_DMABMR_RDP_8Beat 0x00100000U 16048 #define ETH_DMABMR_RDP_16Beat 0x00200000U 16049 #define ETH_DMABMR_RDP_32Beat 0x00400000U 16050 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U 16051 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U 16052 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U 16053 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U 16054 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U 16055 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U 16056 #define ETH_DMABMR_FB_Pos (16U) 16057 #define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) 16058 #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk 16059 #define ETH_DMABMR_RTPR_Pos (14U) 16060 #define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) 16061 #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk 16062 #define ETH_DMABMR_RTPR_1_1 0x00000000U 16063 #define ETH_DMABMR_RTPR_2_1 0x00004000U 16064 #define ETH_DMABMR_RTPR_3_1 0x00008000U 16065 #define ETH_DMABMR_RTPR_4_1 0x0000C000U 16066 #define ETH_DMABMR_PBL_Pos (8U) 16067 #define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) 16068 #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk 16069 #define ETH_DMABMR_PBL_1Beat 0x00000100U 16070 #define ETH_DMABMR_PBL_2Beat 0x00000200U 16071 #define ETH_DMABMR_PBL_4Beat 0x00000400U 16072 #define ETH_DMABMR_PBL_8Beat 0x00000800U 16073 #define ETH_DMABMR_PBL_16Beat 0x00001000U 16074 #define ETH_DMABMR_PBL_32Beat 0x00002000U 16075 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U 16076 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U 16077 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U 16078 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U 16079 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U 16080 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U 16081 #define ETH_DMABMR_EDE_Pos (7U) 16082 #define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) 16083 #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk 16084 #define ETH_DMABMR_DSL_Pos (2U) 16085 #define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) 16086 #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk 16087 #define ETH_DMABMR_DA_Pos (1U) 16088 #define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) 16089 #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk 16090 #define ETH_DMABMR_SR_Pos (0U) 16091 #define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) 16092 #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk 16095 #define ETH_DMATPDR_TPD_Pos (0U) 16096 #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) 16097 #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk 16100 #define ETH_DMARPDR_RPD_Pos (0U) 16101 #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) 16102 #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk 16105 #define ETH_DMARDLAR_SRL_Pos (0U) 16106 #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) 16107 #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk 16110 #define ETH_DMATDLAR_STL_Pos (0U) 16111 #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) 16112 #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk 16115 #define ETH_DMASR_TSTS_Pos (29U) 16116 #define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) 16117 #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk 16118 #define ETH_DMASR_PMTS_Pos (28U) 16119 #define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) 16120 #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk 16121 #define ETH_DMASR_MMCS_Pos (27U) 16122 #define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) 16123 #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk 16124 #define ETH_DMASR_EBS_Pos (23U) 16125 #define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) 16126 #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk 16128 #define ETH_DMASR_EBS_DescAccess_Pos (25U) 16129 #define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) 16130 #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk 16131 #define ETH_DMASR_EBS_ReadTransf_Pos (24U) 16132 #define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) 16133 #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk 16134 #define ETH_DMASR_EBS_DataTransfTx_Pos (23U) 16135 #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) 16136 #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk 16137 #define ETH_DMASR_TPS_Pos (20U) 16138 #define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) 16139 #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk 16140 #define ETH_DMASR_TPS_Stopped 0x00000000U 16141 #define ETH_DMASR_TPS_Fetching_Pos (20U) 16142 #define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) 16143 #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk 16144 #define ETH_DMASR_TPS_Waiting_Pos (21U) 16145 #define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) 16146 #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk 16147 #define ETH_DMASR_TPS_Reading_Pos (20U) 16148 #define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) 16149 #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk 16150 #define ETH_DMASR_TPS_Suspended_Pos (21U) 16151 #define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) 16152 #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk 16153 #define ETH_DMASR_TPS_Closing_Pos (20U) 16154 #define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) 16155 #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk 16156 #define ETH_DMASR_RPS_Pos (17U) 16157 #define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) 16158 #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk 16159 #define ETH_DMASR_RPS_Stopped 0x00000000U 16160 #define ETH_DMASR_RPS_Fetching_Pos (17U) 16161 #define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) 16162 #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk 16163 #define ETH_DMASR_RPS_Waiting_Pos (17U) 16164 #define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) 16165 #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk 16166 #define ETH_DMASR_RPS_Suspended_Pos (19U) 16167 #define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) 16168 #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk 16169 #define ETH_DMASR_RPS_Closing_Pos (17U) 16170 #define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) 16171 #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk 16172 #define ETH_DMASR_RPS_Queuing_Pos (17U) 16173 #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) 16174 #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk 16175 #define ETH_DMASR_NIS_Pos (16U) 16176 #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) 16177 #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk 16178 #define ETH_DMASR_AIS_Pos (15U) 16179 #define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) 16180 #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk 16181 #define ETH_DMASR_ERS_Pos (14U) 16182 #define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) 16183 #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk 16184 #define ETH_DMASR_FBES_Pos (13U) 16185 #define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) 16186 #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk 16187 #define ETH_DMASR_ETS_Pos (10U) 16188 #define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) 16189 #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk 16190 #define ETH_DMASR_RWTS_Pos (9U) 16191 #define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) 16192 #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk 16193 #define ETH_DMASR_RPSS_Pos (8U) 16194 #define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) 16195 #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk 16196 #define ETH_DMASR_RBUS_Pos (7U) 16197 #define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) 16198 #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk 16199 #define ETH_DMASR_RS_Pos (6U) 16200 #define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) 16201 #define ETH_DMASR_RS ETH_DMASR_RS_Msk 16202 #define ETH_DMASR_TUS_Pos (5U) 16203 #define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) 16204 #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk 16205 #define ETH_DMASR_ROS_Pos (4U) 16206 #define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) 16207 #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk 16208 #define ETH_DMASR_TJTS_Pos (3U) 16209 #define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) 16210 #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk 16211 #define ETH_DMASR_TBUS_Pos (2U) 16212 #define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) 16213 #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk 16214 #define ETH_DMASR_TPSS_Pos (1U) 16215 #define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) 16216 #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk 16217 #define ETH_DMASR_TS_Pos (0U) 16218 #define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) 16219 #define ETH_DMASR_TS ETH_DMASR_TS_Msk 16222 #define ETH_DMAOMR_DTCEFD_Pos (26U) 16223 #define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) 16224 #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk 16225 #define ETH_DMAOMR_RSF_Pos (25U) 16226 #define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) 16227 #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk 16228 #define ETH_DMAOMR_DFRF_Pos (24U) 16229 #define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) 16230 #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk 16231 #define ETH_DMAOMR_TSF_Pos (21U) 16232 #define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) 16233 #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk 16234 #define ETH_DMAOMR_FTF_Pos (20U) 16235 #define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) 16236 #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk 16237 #define ETH_DMAOMR_TTC_Pos (14U) 16238 #define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) 16239 #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk 16240 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U 16241 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U 16242 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U 16243 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U 16244 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U 16245 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U 16246 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U 16247 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U 16248 #define ETH_DMAOMR_ST_Pos (13U) 16249 #define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) 16250 #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk 16251 #define ETH_DMAOMR_FEF_Pos (7U) 16252 #define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) 16253 #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk 16254 #define ETH_DMAOMR_FUGF_Pos (6U) 16255 #define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) 16256 #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk 16257 #define ETH_DMAOMR_RTC_Pos (3U) 16258 #define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) 16259 #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk 16260 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U 16261 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U 16262 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U 16263 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U 16264 #define ETH_DMAOMR_OSF_Pos (2U) 16265 #define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) 16266 #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk 16267 #define ETH_DMAOMR_SR_Pos (1U) 16268 #define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) 16269 #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk 16272 #define ETH_DMAIER_NISE_Pos (16U) 16273 #define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) 16274 #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk 16275 #define ETH_DMAIER_AISE_Pos (15U) 16276 #define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) 16277 #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk 16278 #define ETH_DMAIER_ERIE_Pos (14U) 16279 #define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) 16280 #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk 16281 #define ETH_DMAIER_FBEIE_Pos (13U) 16282 #define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) 16283 #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk 16284 #define ETH_DMAIER_ETIE_Pos (10U) 16285 #define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) 16286 #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk 16287 #define ETH_DMAIER_RWTIE_Pos (9U) 16288 #define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) 16289 #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk 16290 #define ETH_DMAIER_RPSIE_Pos (8U) 16291 #define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) 16292 #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk 16293 #define ETH_DMAIER_RBUIE_Pos (7U) 16294 #define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) 16295 #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk 16296 #define ETH_DMAIER_RIE_Pos (6U) 16297 #define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) 16298 #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk 16299 #define ETH_DMAIER_TUIE_Pos (5U) 16300 #define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) 16301 #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk 16302 #define ETH_DMAIER_ROIE_Pos (4U) 16303 #define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) 16304 #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk 16305 #define ETH_DMAIER_TJTIE_Pos (3U) 16306 #define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) 16307 #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk 16308 #define ETH_DMAIER_TBUIE_Pos (2U) 16309 #define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) 16310 #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk 16311 #define ETH_DMAIER_TPSIE_Pos (1U) 16312 #define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) 16313 #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk 16314 #define ETH_DMAIER_TIE_Pos (0U) 16315 #define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) 16316 #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk 16319 #define ETH_DMAMFBOCR_OFOC_Pos (28U) 16320 #define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) 16321 #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk 16322 #define ETH_DMAMFBOCR_MFA_Pos (17U) 16323 #define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) 16324 #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk 16325 #define ETH_DMAMFBOCR_OMFC_Pos (16U) 16326 #define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) 16327 #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk 16328 #define ETH_DMAMFBOCR_MFC_Pos (0U) 16329 #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) 16330 #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk 16333 #define ETH_DMACHTDR_HTDAP_Pos (0U) 16334 #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) 16335 #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk 16338 #define ETH_DMACHRDR_HRDAP_Pos (0U) 16339 #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) 16340 #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk 16343 #define ETH_DMACHTBAR_HTBAP_Pos (0U) 16344 #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) 16345 #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk 16348 #define ETH_DMACHRBAR_HRBAP_Pos (0U) 16349 #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) 16350 #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk 16358 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) 16359 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) 16360 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk 16361 #define USB_OTG_GOTGCTL_SRQ_Pos (1U) 16362 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) 16363 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk 16364 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U) 16365 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) 16366 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk 16367 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U) 16368 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) 16369 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk 16370 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U) 16371 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) 16372 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk 16373 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U) 16374 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) 16375 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk 16376 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U) 16377 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) 16378 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk 16379 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) 16380 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) 16381 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk 16382 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) 16383 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) 16384 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk 16385 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) 16386 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) 16387 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk 16388 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) 16389 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) 16390 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk 16391 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) 16392 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) 16393 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk 16394 #define USB_OTG_GOTGCTL_EHEN_Pos (12U) 16395 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) 16396 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk 16397 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) 16398 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) 16399 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk 16400 #define USB_OTG_GOTGCTL_DBCT_Pos (17U) 16401 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) 16402 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk 16403 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U) 16404 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) 16405 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk 16406 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) 16407 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) 16408 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk 16409 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) 16410 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) 16411 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk 16414 #define USB_OTG_HCFG_FSLSPCS_Pos (0U) 16415 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) 16416 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk 16417 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) 16418 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) 16419 #define USB_OTG_HCFG_FSLSS_Pos (2U) 16420 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) 16421 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk 16424 #define USB_OTG_DCFG_DSPD_Pos (0U) 16425 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) 16426 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk 16427 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) 16428 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) 16429 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U) 16430 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) 16431 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk 16433 #define USB_OTG_DCFG_DAD_Pos (4U) 16434 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) 16435 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk 16436 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) 16437 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) 16438 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) 16439 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) 16440 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) 16441 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) 16442 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) 16444 #define USB_OTG_DCFG_PFIVL_Pos (11U) 16445 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) 16446 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk 16447 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) 16448 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) 16450 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) 16451 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) 16452 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk 16453 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) 16454 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) 16457 #define USB_OTG_PCGCR_STPPCLK_Pos (0U) 16458 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) 16459 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk 16460 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U) 16461 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) 16462 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk 16463 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U) 16464 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) 16465 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk 16468 #define USB_OTG_GOTGINT_SEDET_Pos (2U) 16469 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) 16470 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk 16471 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) 16472 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) 16473 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk 16474 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) 16475 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) 16476 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk 16477 #define USB_OTG_GOTGINT_HNGDET_Pos (17U) 16478 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) 16479 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk 16480 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) 16481 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) 16482 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk 16483 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U) 16484 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) 16485 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk 16486 #define USB_OTG_GOTGINT_IDCHNG_Pos (20U) 16487 #define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) 16488 #define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk 16491 #define USB_OTG_DCTL_RWUSIG_Pos (0U) 16492 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) 16493 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk 16494 #define USB_OTG_DCTL_SDIS_Pos (1U) 16495 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) 16496 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk 16497 #define USB_OTG_DCTL_GINSTS_Pos (2U) 16498 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) 16499 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk 16500 #define USB_OTG_DCTL_GONSTS_Pos (3U) 16501 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) 16502 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk 16504 #define USB_OTG_DCTL_TCTL_Pos (4U) 16505 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) 16506 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk 16507 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) 16508 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) 16509 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) 16510 #define USB_OTG_DCTL_SGINAK_Pos (7U) 16511 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) 16512 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk 16513 #define USB_OTG_DCTL_CGINAK_Pos (8U) 16514 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) 16515 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk 16516 #define USB_OTG_DCTL_SGONAK_Pos (9U) 16517 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) 16518 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk 16519 #define USB_OTG_DCTL_CGONAK_Pos (10U) 16520 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) 16521 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk 16522 #define USB_OTG_DCTL_POPRGDNE_Pos (11U) 16523 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) 16524 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk 16527 #define USB_OTG_HFIR_FRIVL_Pos (0U) 16528 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) 16529 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk 16532 #define USB_OTG_HFNUM_FRNUM_Pos (0U) 16533 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) 16534 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk 16535 #define USB_OTG_HFNUM_FTREM_Pos (16U) 16536 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) 16537 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk 16540 #define USB_OTG_DSTS_SUSPSTS_Pos (0U) 16541 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) 16542 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk 16544 #define USB_OTG_DSTS_ENUMSPD_Pos (1U) 16545 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) 16546 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk 16547 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) 16548 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) 16549 #define USB_OTG_DSTS_EERR_Pos (3U) 16550 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) 16551 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk 16552 #define USB_OTG_DSTS_FNSOF_Pos (8U) 16553 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) 16554 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk 16557 #define USB_OTG_GAHBCFG_GINT_Pos (0U) 16558 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) 16559 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk 16560 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) 16561 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) 16562 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk 16563 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) 16564 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) 16565 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) 16566 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) 16567 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) 16568 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U) 16569 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) 16570 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk 16571 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) 16572 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) 16573 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk 16574 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) 16575 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) 16576 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk 16579 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U) 16580 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) 16581 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk 16582 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) 16583 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) 16584 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) 16585 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) 16586 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) 16587 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk 16588 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) 16589 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) 16590 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk 16591 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) 16592 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) 16593 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk 16594 #define USB_OTG_GUSBCFG_TRDT_Pos (10U) 16595 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) 16596 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk 16597 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) 16598 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) 16599 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) 16600 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) 16601 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) 16602 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) 16603 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk 16604 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) 16605 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) 16606 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk 16607 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) 16608 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) 16609 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk 16610 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) 16611 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) 16612 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk 16613 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) 16614 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) 16615 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk 16616 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) 16617 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) 16618 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk 16619 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U) 16620 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) 16621 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk 16622 #define USB_OTG_GUSBCFG_PCCI_Pos (23U) 16623 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) 16624 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk 16625 #define USB_OTG_GUSBCFG_PTCI_Pos (24U) 16626 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) 16627 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk 16628 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) 16629 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) 16630 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk 16631 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U) 16632 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) 16633 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk 16634 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U) 16635 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) 16636 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk 16637 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) 16638 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) 16639 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk 16642 #define USB_OTG_GRSTCTL_CSRST_Pos (0U) 16643 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) 16644 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk 16645 #define USB_OTG_GRSTCTL_HSRST_Pos (1U) 16646 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) 16647 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk 16648 #define USB_OTG_GRSTCTL_FCRST_Pos (2U) 16649 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) 16650 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk 16651 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) 16652 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) 16653 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk 16654 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) 16655 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) 16656 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk 16657 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) 16658 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) 16659 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk 16660 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) 16661 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) 16662 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) 16663 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) 16664 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) 16665 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) 16666 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) 16667 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk 16668 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) 16669 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) 16670 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk 16673 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U) 16674 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) 16675 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk 16676 #define USB_OTG_DIEPMSK_EPDM_Pos (1U) 16677 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) 16678 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk 16679 #define USB_OTG_DIEPMSK_TOM_Pos (3U) 16680 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) 16681 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk 16682 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) 16683 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) 16684 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk 16685 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) 16686 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) 16687 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk 16688 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) 16689 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) 16690 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk 16691 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U) 16692 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) 16693 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk 16694 #define USB_OTG_DIEPMSK_BIM_Pos (9U) 16695 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) 16696 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk 16699 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) 16700 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) 16701 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk 16702 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) 16703 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) 16704 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk 16705 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) 16706 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) 16707 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) 16708 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) 16709 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) 16710 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) 16711 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) 16712 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) 16714 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) 16715 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) 16716 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk 16717 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) 16718 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) 16719 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) 16720 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) 16721 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) 16722 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) 16723 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) 16724 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) 16727 #define USB_OTG_HAINT_HAINT_Pos (0U) 16728 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) 16729 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk 16732 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U) 16733 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) 16734 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk 16735 #define USB_OTG_DOEPMSK_EPDM_Pos (1U) 16736 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) 16737 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk 16738 #define USB_OTG_DOEPMSK_STUPM_Pos (3U) 16739 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) 16740 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk 16741 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) 16742 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) 16743 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk 16744 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) 16745 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) 16746 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk 16747 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) 16748 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) 16749 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk 16750 #define USB_OTG_DOEPMSK_OPEM_Pos (8U) 16751 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) 16752 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk 16753 #define USB_OTG_DOEPMSK_BOIM_Pos (9U) 16754 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) 16755 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk 16758 #define USB_OTG_GINTSTS_CMOD_Pos (0U) 16759 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) 16760 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk 16761 #define USB_OTG_GINTSTS_MMIS_Pos (1U) 16762 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) 16763 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk 16764 #define USB_OTG_GINTSTS_OTGINT_Pos (2U) 16765 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) 16766 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk 16767 #define USB_OTG_GINTSTS_SOF_Pos (3U) 16768 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) 16769 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk 16770 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U) 16771 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) 16772 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk 16773 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U) 16774 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) 16775 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk 16776 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) 16777 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) 16778 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk 16779 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) 16780 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) 16781 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk 16782 #define USB_OTG_GINTSTS_ESUSP_Pos (10U) 16783 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) 16784 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk 16785 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U) 16786 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) 16787 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk 16788 #define USB_OTG_GINTSTS_USBRST_Pos (12U) 16789 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) 16790 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk 16791 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) 16792 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) 16793 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk 16794 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U) 16795 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) 16796 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk 16797 #define USB_OTG_GINTSTS_EOPF_Pos (15U) 16798 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) 16799 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk 16800 #define USB_OTG_GINTSTS_IEPINT_Pos (18U) 16801 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) 16802 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk 16803 #define USB_OTG_GINTSTS_OEPINT_Pos (19U) 16804 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) 16805 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk 16806 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) 16807 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) 16808 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk 16809 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) 16810 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) 16811 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk 16812 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) 16813 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) 16814 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk 16815 #define USB_OTG_GINTSTS_RSTDET_Pos (23U) 16816 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) 16817 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk 16818 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) 16819 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) 16820 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk 16821 #define USB_OTG_GINTSTS_HCINT_Pos (25U) 16822 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) 16823 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk 16824 #define USB_OTG_GINTSTS_PTXFE_Pos (26U) 16825 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) 16826 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk 16827 #define USB_OTG_GINTSTS_LPMINT_Pos (27U) 16828 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) 16829 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk 16830 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) 16831 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) 16832 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk 16833 #define USB_OTG_GINTSTS_DISCINT_Pos (29U) 16834 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) 16835 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk 16836 #define USB_OTG_GINTSTS_SRQINT_Pos (30U) 16837 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) 16838 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk 16839 #define USB_OTG_GINTSTS_WKUINT_Pos (31U) 16840 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) 16841 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk 16844 #define USB_OTG_GINTMSK_MMISM_Pos (1U) 16845 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) 16846 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk 16847 #define USB_OTG_GINTMSK_OTGINT_Pos (2U) 16848 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) 16849 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk 16850 #define USB_OTG_GINTMSK_SOFM_Pos (3U) 16851 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) 16852 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk 16853 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) 16854 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) 16855 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk 16856 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) 16857 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) 16858 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk 16859 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) 16860 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) 16861 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk 16862 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) 16863 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) 16864 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk 16865 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U) 16866 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) 16867 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk 16868 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) 16869 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) 16870 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk 16871 #define USB_OTG_GINTMSK_USBRST_Pos (12U) 16872 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) 16873 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk 16874 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) 16875 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) 16876 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk 16877 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) 16878 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) 16879 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk 16880 #define USB_OTG_GINTMSK_EOPFM_Pos (15U) 16881 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) 16882 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk 16883 #define USB_OTG_GINTMSK_EPMISM_Pos (17U) 16884 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) 16885 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk 16886 #define USB_OTG_GINTMSK_IEPINT_Pos (18U) 16887 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) 16888 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk 16889 #define USB_OTG_GINTMSK_OEPINT_Pos (19U) 16890 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) 16891 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk 16892 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) 16893 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) 16894 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk 16895 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) 16896 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) 16897 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk 16898 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) 16899 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) 16900 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk 16901 #define USB_OTG_GINTMSK_RSTDEM_Pos (23U) 16902 #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) 16903 #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk 16904 #define USB_OTG_GINTMSK_PRTIM_Pos (24U) 16905 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) 16906 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk 16907 #define USB_OTG_GINTMSK_HCIM_Pos (25U) 16908 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) 16909 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk 16910 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U) 16911 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) 16912 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk 16913 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U) 16914 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) 16915 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk 16916 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) 16917 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) 16918 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk 16919 #define USB_OTG_GINTMSK_DISCINT_Pos (29U) 16920 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) 16921 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk 16922 #define USB_OTG_GINTMSK_SRQIM_Pos (30U) 16923 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) 16924 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk 16925 #define USB_OTG_GINTMSK_WUIM_Pos (31U) 16926 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) 16927 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk 16930 #define USB_OTG_DAINT_IEPINT_Pos (0U) 16931 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) 16932 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk 16933 #define USB_OTG_DAINT_OEPINT_Pos (16U) 16934 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) 16935 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk 16938 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U) 16939 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) 16940 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk 16943 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U) 16944 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) 16945 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk 16946 #define USB_OTG_GRXSTSP_BCNT_Pos (4U) 16947 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) 16948 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk 16949 #define USB_OTG_GRXSTSP_DPID_Pos (15U) 16950 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) 16951 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk 16952 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) 16953 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) 16954 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk 16957 #define USB_OTG_DAINTMSK_IEPM_Pos (0U) 16958 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) 16959 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk 16960 #define USB_OTG_DAINTMSK_OEPM_Pos (16U) 16961 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) 16962 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk 16966 #define USB_OTG_CHNUM_Pos (0U) 16967 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) 16968 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk 16969 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) 16970 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) 16971 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) 16972 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) 16973 #define USB_OTG_BCNT_Pos (4U) 16974 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) 16975 #define USB_OTG_BCNT USB_OTG_BCNT_Msk 16977 #define USB_OTG_DPID_Pos (15U) 16978 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) 16979 #define USB_OTG_DPID USB_OTG_DPID_Msk 16980 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) 16981 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) 16983 #define USB_OTG_PKTSTS_Pos (17U) 16984 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) 16985 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk 16986 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) 16987 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) 16988 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) 16989 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) 16991 #define USB_OTG_EPNUM_Pos (0U) 16992 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) 16993 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk 16994 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) 16995 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) 16996 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) 16997 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) 16999 #define USB_OTG_FRMNUM_Pos (21U) 17000 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) 17001 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk 17002 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) 17003 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) 17004 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) 17005 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) 17009 #define USB_OTG_CHNUM_Pos (0U) 17010 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) 17011 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk 17012 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) 17013 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) 17014 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) 17015 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) 17016 #define USB_OTG_BCNT_Pos (4U) 17017 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) 17018 #define USB_OTG_BCNT USB_OTG_BCNT_Msk 17020 #define USB_OTG_DPID_Pos (15U) 17021 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) 17022 #define USB_OTG_DPID USB_OTG_DPID_Msk 17023 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) 17024 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) 17026 #define USB_OTG_PKTSTS_Pos (17U) 17027 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) 17028 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk 17029 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) 17030 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) 17031 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) 17032 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) 17034 #define USB_OTG_EPNUM_Pos (0U) 17035 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) 17036 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk 17037 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) 17038 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) 17039 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) 17040 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) 17042 #define USB_OTG_FRMNUM_Pos (21U) 17043 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) 17044 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk 17045 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) 17046 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) 17047 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) 17048 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) 17051 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) 17052 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) 17053 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk 17056 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) 17057 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) 17058 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk 17061 #define USB_OTG_NPTXFSA_Pos (0U) 17062 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) 17063 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk 17064 #define USB_OTG_NPTXFD_Pos (16U) 17065 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) 17066 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk 17067 #define USB_OTG_TX0FSA_Pos (0U) 17068 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) 17069 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk 17070 #define USB_OTG_TX0FD_Pos (16U) 17071 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) 17072 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk 17075 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) 17076 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) 17077 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk 17080 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) 17081 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) 17082 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk 17084 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) 17085 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) 17086 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk 17087 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) 17088 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) 17089 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) 17090 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) 17091 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) 17092 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) 17093 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) 17094 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) 17096 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) 17097 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) 17098 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk 17099 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) 17100 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) 17101 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) 17102 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) 17103 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) 17104 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) 17105 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) 17108 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) 17109 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) 17110 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk 17111 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) 17112 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) 17113 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk 17115 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) 17116 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) 17117 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk 17118 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) 17119 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) 17120 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) 17121 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) 17122 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) 17123 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) 17124 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) 17125 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) 17126 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) 17127 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) 17128 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) 17129 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk 17131 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) 17132 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) 17133 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk 17134 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) 17135 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) 17136 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) 17137 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) 17138 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) 17139 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) 17140 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) 17141 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) 17142 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) 17143 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U) 17144 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) 17145 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk 17148 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) 17149 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) 17150 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk 17153 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U) 17154 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) 17155 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk 17156 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U) 17157 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) 17158 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk 17161 #define USB_OTG_GCCFG_PWRDWN_Pos (16U) 17162 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) 17163 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk 17164 #define USB_OTG_GCCFG_VBDEN_Pos (21U) 17165 #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) 17166 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk 17169 #define USB_OTG_GPWRDN_ADPMEN_Pos (0U) 17170 #define USB_OTG_GPWRDN_ADPMEN_Msk (0x1U << USB_OTG_GPWRDN_ADPMEN_Pos) 17171 #define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk 17172 #define USB_OTG_GPWRDN_ADPIF_Pos (23U) 17173 #define USB_OTG_GPWRDN_ADPIF_Msk (0x1U << USB_OTG_GPWRDN_ADPIF_Pos) 17174 #define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk 17177 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) 17178 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) 17179 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk 17180 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) 17181 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) 17182 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk 17185 #define USB_OTG_CID_PRODUCT_ID_Pos (0U) 17186 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) 17187 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk 17190 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) 17191 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) 17192 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk 17193 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U) 17194 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) 17195 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk 17196 #define USB_OTG_GLPMCFG_BESL_Pos (2U) 17197 #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) 17198 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk 17199 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) 17200 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) 17201 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk 17202 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) 17203 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) 17204 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk 17205 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) 17206 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) 17207 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk 17208 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) 17209 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) 17210 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk 17211 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) 17212 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) 17213 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk 17214 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) 17215 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) 17216 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk 17217 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) 17218 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) 17219 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk 17220 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) 17221 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) 17222 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk 17223 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) 17224 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) 17225 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk 17226 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) 17227 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) 17228 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk 17229 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) 17230 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) 17231 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk 17232 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U) 17233 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) 17234 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk 17237 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) 17238 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) 17239 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk 17240 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) 17241 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) 17242 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk 17243 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) 17244 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) 17245 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk 17246 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) 17247 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) 17248 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk 17249 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) 17250 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) 17251 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk 17252 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) 17253 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) 17254 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk 17255 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) 17256 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) 17257 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk 17258 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) 17259 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) 17260 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk 17261 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) 17262 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) 17263 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk 17266 #define USB_OTG_HPRT_PCSTS_Pos (0U) 17267 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) 17268 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk 17269 #define USB_OTG_HPRT_PCDET_Pos (1U) 17270 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) 17271 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk 17272 #define USB_OTG_HPRT_PENA_Pos (2U) 17273 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) 17274 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk 17275 #define USB_OTG_HPRT_PENCHNG_Pos (3U) 17276 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) 17277 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk 17278 #define USB_OTG_HPRT_POCA_Pos (4U) 17279 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) 17280 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk 17281 #define USB_OTG_HPRT_POCCHNG_Pos (5U) 17282 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) 17283 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk 17284 #define USB_OTG_HPRT_PRES_Pos (6U) 17285 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) 17286 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk 17287 #define USB_OTG_HPRT_PSUSP_Pos (7U) 17288 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) 17289 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk 17290 #define USB_OTG_HPRT_PRST_Pos (8U) 17291 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) 17292 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk 17294 #define USB_OTG_HPRT_PLSTS_Pos (10U) 17295 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) 17296 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk 17297 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) 17298 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) 17299 #define USB_OTG_HPRT_PPWR_Pos (12U) 17300 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) 17301 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk 17303 #define USB_OTG_HPRT_PTCTL_Pos (13U) 17304 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) 17305 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk 17306 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) 17307 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) 17308 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) 17309 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) 17311 #define USB_OTG_HPRT_PSPD_Pos (17U) 17312 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) 17313 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk 17314 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) 17315 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) 17318 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) 17319 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) 17320 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk 17321 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) 17322 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) 17323 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk 17324 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) 17325 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) 17326 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk 17327 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) 17328 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) 17329 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk 17330 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) 17331 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) 17332 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk 17333 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) 17334 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) 17335 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk 17336 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) 17337 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) 17338 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk 17339 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) 17340 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) 17341 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk 17342 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) 17343 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) 17344 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk 17345 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) 17346 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) 17347 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk 17348 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) 17349 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) 17350 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk 17353 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) 17354 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) 17355 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk 17356 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) 17357 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) 17358 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk 17361 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) 17362 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) 17363 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk 17364 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U) 17365 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) 17366 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk 17367 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) 17368 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) 17369 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk 17370 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) 17371 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) 17372 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk 17374 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U) 17375 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) 17376 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk 17377 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) 17378 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) 17379 #define USB_OTG_DIEPCTL_STALL_Pos (21U) 17380 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) 17381 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk 17383 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) 17384 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) 17385 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk 17386 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) 17387 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) 17388 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) 17389 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) 17390 #define USB_OTG_DIEPCTL_CNAK_Pos (26U) 17391 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) 17392 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk 17393 #define USB_OTG_DIEPCTL_SNAK_Pos (27U) 17394 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) 17395 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk 17396 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) 17397 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) 17398 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk 17399 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) 17400 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) 17401 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk 17402 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) 17403 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) 17404 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk 17405 #define USB_OTG_DIEPCTL_EPENA_Pos (31U) 17406 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) 17407 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk 17410 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) 17411 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) 17412 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk 17414 #define USB_OTG_HCCHAR_EPNUM_Pos (11U) 17415 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) 17416 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk 17417 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) 17418 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) 17419 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) 17420 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) 17421 #define USB_OTG_HCCHAR_EPDIR_Pos (15U) 17422 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) 17423 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk 17424 #define USB_OTG_HCCHAR_LSDEV_Pos (17U) 17425 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) 17426 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk 17428 #define USB_OTG_HCCHAR_EPTYP_Pos (18U) 17429 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) 17430 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk 17431 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) 17432 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) 17434 #define USB_OTG_HCCHAR_MC_Pos (20U) 17435 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) 17436 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk 17437 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) 17438 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) 17440 #define USB_OTG_HCCHAR_DAD_Pos (22U) 17441 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) 17442 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk 17443 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) 17444 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) 17445 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) 17446 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) 17447 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) 17448 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) 17449 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) 17450 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U) 17451 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) 17452 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk 17453 #define USB_OTG_HCCHAR_CHDIS_Pos (30U) 17454 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) 17455 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk 17456 #define USB_OTG_HCCHAR_CHENA_Pos (31U) 17457 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) 17458 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk 17462 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U) 17463 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) 17464 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk 17465 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) 17466 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) 17467 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) 17468 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) 17469 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) 17470 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) 17471 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) 17473 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U) 17474 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) 17475 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk 17476 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) 17477 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) 17478 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) 17479 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) 17480 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) 17481 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) 17482 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) 17484 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U) 17485 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) 17486 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk 17487 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) 17488 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) 17489 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) 17490 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) 17491 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk 17492 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U) 17493 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) 17494 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk 17497 #define USB_OTG_HCINT_XFRC_Pos (0U) 17498 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) 17499 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk 17500 #define USB_OTG_HCINT_CHH_Pos (1U) 17501 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) 17502 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk 17503 #define USB_OTG_HCINT_AHBERR_Pos (2U) 17504 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) 17505 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk 17506 #define USB_OTG_HCINT_STALL_Pos (3U) 17507 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) 17508 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk 17509 #define USB_OTG_HCINT_NAK_Pos (4U) 17510 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) 17511 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk 17512 #define USB_OTG_HCINT_ACK_Pos (5U) 17513 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) 17514 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk 17515 #define USB_OTG_HCINT_NYET_Pos (6U) 17516 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) 17517 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk 17518 #define USB_OTG_HCINT_TXERR_Pos (7U) 17519 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) 17520 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk 17521 #define USB_OTG_HCINT_BBERR_Pos (8U) 17522 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) 17523 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk 17524 #define USB_OTG_HCINT_FRMOR_Pos (9U) 17525 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) 17526 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk 17527 #define USB_OTG_HCINT_DTERR_Pos (10U) 17528 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) 17529 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk 17532 #define USB_OTG_DIEPINT_XFRC_Pos (0U) 17533 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) 17534 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk 17535 #define USB_OTG_DIEPINT_EPDISD_Pos (1U) 17536 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) 17537 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk 17538 #define USB_OTG_DIEPINT_TOC_Pos (3U) 17539 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) 17540 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk 17541 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) 17542 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) 17543 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk 17544 #define USB_OTG_DIEPINT_INEPNE_Pos (6U) 17545 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) 17546 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk 17547 #define USB_OTG_DIEPINT_TXFE_Pos (7U) 17548 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) 17549 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk 17550 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) 17551 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) 17552 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk 17553 #define USB_OTG_DIEPINT_BNA_Pos (9U) 17554 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) 17555 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk 17556 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) 17557 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) 17558 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk 17559 #define USB_OTG_DIEPINT_BERR_Pos (12U) 17560 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) 17561 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk 17562 #define USB_OTG_DIEPINT_NAK_Pos (13U) 17563 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) 17564 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk 17567 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U) 17568 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) 17569 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk 17570 #define USB_OTG_HCINTMSK_CHHM_Pos (1U) 17571 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) 17572 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk 17573 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U) 17574 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) 17575 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk 17576 #define USB_OTG_HCINTMSK_STALLM_Pos (3U) 17577 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) 17578 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk 17579 #define USB_OTG_HCINTMSK_NAKM_Pos (4U) 17580 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) 17581 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk 17582 #define USB_OTG_HCINTMSK_ACKM_Pos (5U) 17583 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) 17584 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk 17585 #define USB_OTG_HCINTMSK_NYET_Pos (6U) 17586 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) 17587 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk 17588 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U) 17589 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) 17590 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk 17591 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U) 17592 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) 17593 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk 17594 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U) 17595 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) 17596 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk 17597 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U) 17598 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) 17599 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk 17603 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) 17604 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) 17605 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk 17606 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) 17607 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) 17608 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk 17609 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) 17610 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) 17611 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk 17613 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) 17614 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) 17615 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk 17616 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) 17617 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) 17618 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk 17619 #define USB_OTG_HCTSIZ_DOPING_Pos (31U) 17620 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) 17621 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk 17622 #define USB_OTG_HCTSIZ_DPID_Pos (29U) 17623 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) 17624 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk 17625 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) 17626 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) 17629 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) 17630 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) 17631 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk 17634 #define USB_OTG_HCDMA_DMAADDR_Pos (0U) 17635 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) 17636 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk 17639 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) 17640 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) 17641 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk 17644 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) 17645 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) 17646 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk 17647 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) 17648 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) 17649 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk 17652 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) 17653 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) 17654 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk 17655 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) 17656 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) 17657 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk 17658 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) 17659 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) 17660 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk 17661 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) 17662 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) 17663 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk 17664 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) 17665 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) 17666 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk 17667 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) 17668 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) 17669 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk 17670 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) 17671 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) 17672 #define USB_OTG_DOEPCTL_SNPM_Pos (20U) 17673 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) 17674 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk 17675 #define USB_OTG_DOEPCTL_STALL_Pos (21U) 17676 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) 17677 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk 17678 #define USB_OTG_DOEPCTL_CNAK_Pos (26U) 17679 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) 17680 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk 17681 #define USB_OTG_DOEPCTL_SNAK_Pos (27U) 17682 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) 17683 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk 17684 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) 17685 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) 17686 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk 17687 #define USB_OTG_DOEPCTL_EPENA_Pos (31U) 17688 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) 17689 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk 17692 #define USB_OTG_DOEPINT_XFRC_Pos (0U) 17693 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) 17694 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk 17695 #define USB_OTG_DOEPINT_EPDISD_Pos (1U) 17696 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) 17697 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk 17698 #define USB_OTG_DOEPINT_STUP_Pos (3U) 17699 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) 17700 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk 17701 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) 17702 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) 17703 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk 17704 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U) 17705 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) 17706 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk 17707 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) 17708 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) 17709 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk 17710 #define USB_OTG_DOEPINT_NYET_Pos (14U) 17711 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) 17712 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk 17715 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) 17716 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) 17717 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk 17718 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U) 17719 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) 17720 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk 17722 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) 17723 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) 17724 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk 17725 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) 17726 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) 17729 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) 17730 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) 17731 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk 17732 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U) 17733 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) 17734 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk 17735 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U) 17736 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) 17737 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk 17746 #define JPEG_CONFR0_START_Pos (0U) 17747 #define JPEG_CONFR0_START_Msk (0x1U << JPEG_CONFR0_START_Pos) 17748 #define JPEG_CONFR0_START JPEG_CONFR0_START_Msk 17751 #define JPEG_CONFR1_NF_Pos (0U) 17752 #define JPEG_CONFR1_NF_Msk (0x3U << JPEG_CONFR1_NF_Pos) 17753 #define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk 17754 #define JPEG_CONFR1_NF_0 (0x1U << JPEG_CONFR1_NF_Pos) 17755 #define JPEG_CONFR1_NF_1 (0x2U << JPEG_CONFR1_NF_Pos) 17756 #define JPEG_CONFR1_RE_Pos (2U) 17757 #define JPEG_CONFR1_RE_Msk (0x1U << JPEG_CONFR1_RE_Pos) 17758 #define JPEG_CONFR1_RE JPEG_CONFR1_RE_Msk 17759 #define JPEG_CONFR1_DE_Pos (3U) 17760 #define JPEG_CONFR1_DE_Msk (0x1U << JPEG_CONFR1_DE_Pos) 17761 #define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk 17762 #define JPEG_CONFR1_COLORSPACE_Pos (4U) 17763 #define JPEG_CONFR1_COLORSPACE_Msk (0x3U << JPEG_CONFR1_COLORSPACE_Pos) 17764 #define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk 17765 #define JPEG_CONFR1_COLORSPACE_0 (0x1U << JPEG_CONFR1_COLORSPACE_Pos) 17766 #define JPEG_CONFR1_COLORSPACE_1 (0x2U << JPEG_CONFR1_COLORSPACE_Pos) 17767 #define JPEG_CONFR1_NS_Pos (6U) 17768 #define JPEG_CONFR1_NS_Msk (0x3U << JPEG_CONFR1_NS_Pos) 17769 #define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk 17770 #define JPEG_CONFR1_NS_0 (0x1U << JPEG_CONFR1_NS_Pos) 17771 #define JPEG_CONFR1_NS_1 (0x2U << JPEG_CONFR1_NS_Pos) 17772 #define JPEG_CONFR1_HDR_Pos (8U) 17773 #define JPEG_CONFR1_HDR_Msk (0x1U << JPEG_CONFR1_HDR_Pos) 17774 #define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk 17775 #define JPEG_CONFR1_YSIZE_Pos (16U) 17776 #define JPEG_CONFR1_YSIZE_Msk (0xFFFFU << JPEG_CONFR1_YSIZE_Pos) 17777 #define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk 17780 #define JPEG_CONFR2_NMCU_Pos (0U) 17781 #define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFU << JPEG_CONFR2_NMCU_Pos) 17782 #define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk 17785 #define JPEG_CONFR3_NRST_Pos (0U) 17786 #define JPEG_CONFR3_NRST_Msk (0xFFFFU << JPEG_CONFR3_NRST_Pos) 17787 #define JPEG_CONFR3_NRST JPEG_CONFR3_NRST_Msk 17788 #define JPEG_CONFR3_XSIZE_Pos (16U) 17789 #define JPEG_CONFR3_XSIZE_Msk (0xFFFFU << JPEG_CONFR3_XSIZE_Pos) 17790 #define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk 17793 #define JPEG_CONFR4_HD_Pos (0U) 17794 #define JPEG_CONFR4_HD_Msk (0x1U << JPEG_CONFR4_HD_Pos) 17795 #define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk 17796 #define JPEG_CONFR4_HA_Pos (1U) 17797 #define JPEG_CONFR4_HA_Msk (0x1U << JPEG_CONFR4_HA_Pos) 17798 #define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk 17799 #define JPEG_CONFR4_QT_Pos (2U) 17800 #define JPEG_CONFR4_QT_Msk (0x3U << JPEG_CONFR4_QT_Pos) 17801 #define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk 17802 #define JPEG_CONFR4_QT_0 (0x1U << JPEG_CONFR4_QT_Pos) 17803 #define JPEG_CONFR4_QT_1 (0x2U << JPEG_CONFR4_QT_Pos) 17804 #define JPEG_CONFR4_NB_Pos (4U) 17805 #define JPEG_CONFR4_NB_Msk (0xFU << JPEG_CONFR4_NB_Pos) 17806 #define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk 17807 #define JPEG_CONFR4_NB_0 (0x1U << JPEG_CONFR4_NB_Pos) 17808 #define JPEG_CONFR4_NB_1 (0x2U << JPEG_CONFR4_NB_Pos) 17809 #define JPEG_CONFR4_NB_2 (0x4U << JPEG_CONFR4_NB_Pos) 17810 #define JPEG_CONFR4_NB_3 (0x8U << JPEG_CONFR4_NB_Pos) 17811 #define JPEG_CONFR4_VSF_Pos (8U) 17812 #define JPEG_CONFR4_VSF_Msk (0xFU << JPEG_CONFR4_VSF_Pos) 17813 #define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk 17814 #define JPEG_CONFR4_VSF_0 (0x1U << JPEG_CONFR4_VSF_Pos) 17815 #define JPEG_CONFR4_VSF_1 (0x2U << JPEG_CONFR4_VSF_Pos) 17816 #define JPEG_CONFR4_VSF_2 (0x4U << JPEG_CONFR4_VSF_Pos) 17817 #define JPEG_CONFR4_VSF_3 (0x8U << JPEG_CONFR4_VSF_Pos) 17818 #define JPEG_CONFR4_HSF_Pos (12U) 17819 #define JPEG_CONFR4_HSF_Msk (0xFU << JPEG_CONFR4_HSF_Pos) 17820 #define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk 17821 #define JPEG_CONFR4_HSF_0 (0x1U << JPEG_CONFR4_HSF_Pos) 17822 #define JPEG_CONFR4_HSF_1 (0x2U << JPEG_CONFR4_HSF_Pos) 17823 #define JPEG_CONFR4_HSF_2 (0x4U << JPEG_CONFR4_HSF_Pos) 17824 #define JPEG_CONFR4_HSF_3 (0x8U << JPEG_CONFR4_HSF_Pos) 17827 #define JPEG_CONFR5_HD_Pos (0U) 17828 #define JPEG_CONFR5_HD_Msk (0x1U << JPEG_CONFR5_HD_Pos) 17829 #define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk 17830 #define JPEG_CONFR5_HA_Pos (1U) 17831 #define JPEG_CONFR5_HA_Msk (0x1U << JPEG_CONFR5_HA_Pos) 17832 #define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk 17833 #define JPEG_CONFR5_QT_Pos (2U) 17834 #define JPEG_CONFR5_QT_Msk (0x3U << JPEG_CONFR5_QT_Pos) 17835 #define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk 17836 #define JPEG_CONFR5_QT_0 (0x1U << JPEG_CONFR5_QT_Pos) 17837 #define JPEG_CONFR5_QT_1 (0x2U << JPEG_CONFR5_QT_Pos) 17838 #define JPEG_CONFR5_NB_Pos (4U) 17839 #define JPEG_CONFR5_NB_Msk (0xFU << JPEG_CONFR5_NB_Pos) 17840 #define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk 17841 #define JPEG_CONFR5_NB_0 (0x1U << JPEG_CONFR5_NB_Pos) 17842 #define JPEG_CONFR5_NB_1 (0x2U << JPEG_CONFR5_NB_Pos) 17843 #define JPEG_CONFR5_NB_2 (0x4U << JPEG_CONFR5_NB_Pos) 17844 #define JPEG_CONFR5_NB_3 (0x8U << JPEG_CONFR5_NB_Pos) 17845 #define JPEG_CONFR5_VSF_Pos (8U) 17846 #define JPEG_CONFR5_VSF_Msk (0xFU << JPEG_CONFR5_VSF_Pos) 17847 #define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk 17848 #define JPEG_CONFR5_VSF_0 (0x1U << JPEG_CONFR5_VSF_Pos) 17849 #define JPEG_CONFR5_VSF_1 (0x2U << JPEG_CONFR5_VSF_Pos) 17850 #define JPEG_CONFR5_VSF_2 (0x4U << JPEG_CONFR5_VSF_Pos) 17851 #define JPEG_CONFR5_VSF_3 (0x8U << JPEG_CONFR5_VSF_Pos) 17852 #define JPEG_CONFR5_HSF_Pos (12U) 17853 #define JPEG_CONFR5_HSF_Msk (0xFU << JPEG_CONFR5_HSF_Pos) 17854 #define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk 17855 #define JPEG_CONFR5_HSF_0 (0x1U << JPEG_CONFR5_HSF_Pos) 17856 #define JPEG_CONFR5_HSF_1 (0x2U << JPEG_CONFR5_HSF_Pos) 17857 #define JPEG_CONFR5_HSF_2 (0x4U << JPEG_CONFR5_HSF_Pos) 17858 #define JPEG_CONFR5_HSF_3 (0x8U << JPEG_CONFR5_HSF_Pos) 17861 #define JPEG_CONFR6_HD_Pos (0U) 17862 #define JPEG_CONFR6_HD_Msk (0x1U << JPEG_CONFR6_HD_Pos) 17863 #define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk 17864 #define JPEG_CONFR6_HA_Pos (1U) 17865 #define JPEG_CONFR6_HA_Msk (0x1U << JPEG_CONFR6_HA_Pos) 17866 #define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk 17867 #define JPEG_CONFR6_QT_Pos (2U) 17868 #define JPEG_CONFR6_QT_Msk (0x3U << JPEG_CONFR6_QT_Pos) 17869 #define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk 17870 #define JPEG_CONFR6_QT_0 (0x1U << JPEG_CONFR6_QT_Pos) 17871 #define JPEG_CONFR6_QT_1 (0x2U << JPEG_CONFR6_QT_Pos) 17872 #define JPEG_CONFR6_NB_Pos (4U) 17873 #define JPEG_CONFR6_NB_Msk (0xFU << JPEG_CONFR6_NB_Pos) 17874 #define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk 17875 #define JPEG_CONFR6_NB_0 (0x1U << JPEG_CONFR6_NB_Pos) 17876 #define JPEG_CONFR6_NB_1 (0x2U << JPEG_CONFR6_NB_Pos) 17877 #define JPEG_CONFR6_NB_2 (0x4U << JPEG_CONFR6_NB_Pos) 17878 #define JPEG_CONFR6_NB_3 (0x8U << JPEG_CONFR6_NB_Pos) 17879 #define JPEG_CONFR6_VSF_Pos (8U) 17880 #define JPEG_CONFR6_VSF_Msk (0xFU << JPEG_CONFR6_VSF_Pos) 17881 #define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk 17882 #define JPEG_CONFR6_VSF_0 (0x1U << JPEG_CONFR6_VSF_Pos) 17883 #define JPEG_CONFR6_VSF_1 (0x2U << JPEG_CONFR6_VSF_Pos) 17884 #define JPEG_CONFR6_VSF_2 (0x4U << JPEG_CONFR6_VSF_Pos) 17885 #define JPEG_CONFR6_VSF_3 (0x8U << JPEG_CONFR6_VSF_Pos) 17886 #define JPEG_CONFR6_HSF_Pos (12U) 17887 #define JPEG_CONFR6_HSF_Msk (0xFU << JPEG_CONFR6_HSF_Pos) 17888 #define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk 17889 #define JPEG_CONFR6_HSF_0 (0x1U << JPEG_CONFR6_HSF_Pos) 17890 #define JPEG_CONFR6_HSF_1 (0x2U << JPEG_CONFR6_HSF_Pos) 17891 #define JPEG_CONFR6_HSF_2 (0x4U << JPEG_CONFR6_HSF_Pos) 17892 #define JPEG_CONFR6_HSF_3 (0x8U << JPEG_CONFR6_HSF_Pos) 17895 #define JPEG_CONFR7_HD_Pos (0U) 17896 #define JPEG_CONFR7_HD_Msk (0x1U << JPEG_CONFR7_HD_Pos) 17897 #define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk 17898 #define JPEG_CONFR7_HA_Pos (1U) 17899 #define JPEG_CONFR7_HA_Msk (0x1U << JPEG_CONFR7_HA_Pos) 17900 #define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk 17901 #define JPEG_CONFR7_QT_Pos (2U) 17902 #define JPEG_CONFR7_QT_Msk (0x3U << JPEG_CONFR7_QT_Pos) 17903 #define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk 17904 #define JPEG_CONFR7_QT_0 (0x1U << JPEG_CONFR7_QT_Pos) 17905 #define JPEG_CONFR7_QT_1 (0x2U << JPEG_CONFR7_QT_Pos) 17906 #define JPEG_CONFR7_NB_Pos (4U) 17907 #define JPEG_CONFR7_NB_Msk (0xFU << JPEG_CONFR7_NB_Pos) 17908 #define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk 17909 #define JPEG_CONFR7_NB_0 (0x1U << JPEG_CONFR7_NB_Pos) 17910 #define JPEG_CONFR7_NB_1 (0x2U << JPEG_CONFR7_NB_Pos) 17911 #define JPEG_CONFR7_NB_2 (0x4U << JPEG_CONFR7_NB_Pos) 17912 #define JPEG_CONFR7_NB_3 (0x8U << JPEG_CONFR7_NB_Pos) 17913 #define JPEG_CONFR7_VSF_Pos (8U) 17914 #define JPEG_CONFR7_VSF_Msk (0xFU << JPEG_CONFR7_VSF_Pos) 17915 #define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk 17916 #define JPEG_CONFR7_VSF_0 (0x1U << JPEG_CONFR7_VSF_Pos) 17917 #define JPEG_CONFR7_VSF_1 (0x2U << JPEG_CONFR7_VSF_Pos) 17918 #define JPEG_CONFR7_VSF_2 (0x4U << JPEG_CONFR7_VSF_Pos) 17919 #define JPEG_CONFR7_VSF_3 (0x8U << JPEG_CONFR7_VSF_Pos) 17920 #define JPEG_CONFR7_HSF_Pos (12U) 17921 #define JPEG_CONFR7_HSF_Msk (0xFU << JPEG_CONFR7_HSF_Pos) 17922 #define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk 17923 #define JPEG_CONFR7_HSF_0 (0x1U << JPEG_CONFR7_HSF_Pos) 17924 #define JPEG_CONFR7_HSF_1 (0x2U << JPEG_CONFR7_HSF_Pos) 17925 #define JPEG_CONFR7_HSF_2 (0x4U << JPEG_CONFR7_HSF_Pos) 17926 #define JPEG_CONFR7_HSF_3 (0x8U << JPEG_CONFR7_HSF_Pos) 17929 #define JPEG_CR_JCEN_Pos (0U) 17930 #define JPEG_CR_JCEN_Msk (0x1U << JPEG_CR_JCEN_Pos) 17931 #define JPEG_CR_JCEN JPEG_CR_JCEN_Msk 17932 #define JPEG_CR_IFTIE_Pos (1U) 17933 #define JPEG_CR_IFTIE_Msk (0x1U << JPEG_CR_IFTIE_Pos) 17934 #define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk 17935 #define JPEG_CR_IFNFIE_Pos (2U) 17936 #define JPEG_CR_IFNFIE_Msk (0x1U << JPEG_CR_IFNFIE_Pos) 17937 #define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk 17938 #define JPEG_CR_OFTIE_Pos (3U) 17939 #define JPEG_CR_OFTIE_Msk (0x1U << JPEG_CR_OFTIE_Pos) 17940 #define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk 17941 #define JPEG_CR_OFNEIE_Pos (4U) 17942 #define JPEG_CR_OFNEIE_Msk (0x1U << JPEG_CR_OFNEIE_Pos) 17943 #define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk 17944 #define JPEG_CR_EOCIE_Pos (5U) 17945 #define JPEG_CR_EOCIE_Msk (0x1U << JPEG_CR_EOCIE_Pos) 17946 #define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk 17947 #define JPEG_CR_HPDIE_Pos (6U) 17948 #define JPEG_CR_HPDIE_Msk (0x1U << JPEG_CR_HPDIE_Pos) 17949 #define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk 17950 #define JPEG_CR_IDMAEN_Pos (11U) 17951 #define JPEG_CR_IDMAEN_Msk (0x1U << JPEG_CR_IDMAEN_Pos) 17952 #define JPEG_CR_IDMAEN JPEG_CR_IDMAEN_Msk 17953 #define JPEG_CR_ODMAEN_Pos (12U) 17954 #define JPEG_CR_ODMAEN_Msk (0x1U << JPEG_CR_ODMAEN_Pos) 17955 #define JPEG_CR_ODMAEN JPEG_CR_ODMAEN_Msk 17956 #define JPEG_CR_IFF_Pos (13U) 17957 #define JPEG_CR_IFF_Msk (0x1U << JPEG_CR_IFF_Pos) 17958 #define JPEG_CR_IFF JPEG_CR_IFF_Msk 17959 #define JPEG_CR_OFF_Pos (14U) 17960 #define JPEG_CR_OFF_Msk (0x1U << JPEG_CR_OFF_Pos) 17961 #define JPEG_CR_OFF JPEG_CR_OFF_Msk 17964 #define JPEG_SR_IFTF_Pos (1U) 17965 #define JPEG_SR_IFTF_Msk (0x1U << JPEG_SR_IFTF_Pos) 17966 #define JPEG_SR_IFTF JPEG_SR_IFTF_Msk 17967 #define JPEG_SR_IFNFF_Pos (2U) 17968 #define JPEG_SR_IFNFF_Msk (0x1U << JPEG_SR_IFNFF_Pos) 17969 #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk 17970 #define JPEG_SR_OFTF_Pos (3U) 17971 #define JPEG_SR_OFTF_Msk (0x1U << JPEG_SR_OFTF_Pos) 17972 #define JPEG_SR_OFTF JPEG_SR_OFTF_Msk 17973 #define JPEG_SR_OFNEF_Pos (4U) 17974 #define JPEG_SR_OFNEF_Msk (0x1U << JPEG_SR_OFNEF_Pos) 17975 #define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk 17976 #define JPEG_SR_EOCF_Pos (5U) 17977 #define JPEG_SR_EOCF_Msk (0x1U << JPEG_SR_EOCF_Pos) 17978 #define JPEG_SR_EOCF JPEG_SR_EOCF_Msk 17979 #define JPEG_SR_HPDF_Pos (6U) 17980 #define JPEG_SR_HPDF_Msk (0x1U << JPEG_SR_HPDF_Pos) 17981 #define JPEG_SR_HPDF JPEG_SR_HPDF_Msk 17982 #define JPEG_SR_COF_Pos (7U) 17983 #define JPEG_SR_COF_Msk (0x1U << JPEG_SR_COF_Pos) 17984 #define JPEG_SR_COF JPEG_SR_COF_Msk 17987 #define JPEG_CFR_CEOCF_Pos (5U) 17988 #define JPEG_CFR_CEOCF_Msk (0x1U << JPEG_CFR_CEOCF_Pos) 17989 #define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk 17990 #define JPEG_CFR_CHPDF_Pos (6U) 17991 #define JPEG_CFR_CHPDF_Msk (0x1U << JPEG_CFR_CHPDF_Pos) 17992 #define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk 17995 #define JPEG_DIR_DATAIN_Pos (0U) 17996 #define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFU << JPEG_DIR_DATAIN_Pos) 17997 #define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk 18000 #define JPEG_DOR_DATAOUT_Pos (0U) 18001 #define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFU << JPEG_DOR_DATAOUT_Pos) 18002 #define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk 18010 #define MDIOS_CR_EN_Pos (0U) 18011 #define MDIOS_CR_EN_Msk (0x1U << MDIOS_CR_EN_Pos) 18012 #define MDIOS_CR_EN MDIOS_CR_EN_Msk 18013 #define MDIOS_CR_WRIE_Pos (1U) 18014 #define MDIOS_CR_WRIE_Msk (0x1U << MDIOS_CR_WRIE_Pos) 18015 #define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk 18016 #define MDIOS_CR_RDIE_Pos (2U) 18017 #define MDIOS_CR_RDIE_Msk (0x1U << MDIOS_CR_RDIE_Pos) 18018 #define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk 18019 #define MDIOS_CR_EIE_Pos (3U) 18020 #define MDIOS_CR_EIE_Msk (0x1U << MDIOS_CR_EIE_Pos) 18021 #define MDIOS_CR_EIE MDIOS_CR_EIE_Msk 18022 #define MDIOS_CR_DPC_Pos (7U) 18023 #define MDIOS_CR_DPC_Msk (0x1U << MDIOS_CR_DPC_Pos) 18024 #define MDIOS_CR_DPC MDIOS_CR_DPC_Msk 18025 #define MDIOS_CR_PORT_ADDRESS_Pos (8U) 18026 #define MDIOS_CR_PORT_ADDRESS_Msk (0x1FU << MDIOS_CR_PORT_ADDRESS_Pos) 18027 #define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk 18028 #define MDIOS_CR_PORT_ADDRESS_0 (0x01U << MDIOS_CR_PORT_ADDRESS_Pos) 18029 #define MDIOS_CR_PORT_ADDRESS_1 (0x02U << MDIOS_CR_PORT_ADDRESS_Pos) 18030 #define MDIOS_CR_PORT_ADDRESS_2 (0x04U << MDIOS_CR_PORT_ADDRESS_Pos) 18031 #define MDIOS_CR_PORT_ADDRESS_3 (0x08U << MDIOS_CR_PORT_ADDRESS_Pos) 18032 #define MDIOS_CR_PORT_ADDRESS_4 (0x10U << MDIOS_CR_PORT_ADDRESS_Pos) 18035 #define MDIOS_WRFR_WRF_Pos (0U) 18036 #define MDIOS_WRFR_WRF_Msk (0xFFFFFFFFU << MDIOS_WRFR_WRF_Pos) 18037 #define MDIOS_WRFR_WRF MDIOS_WRFR_WRF_Msk 18040 #define MDIOS_CWRFR_CWRF_Pos (0U) 18041 #define MDIOS_CWRFR_CWRF_Msk (0xFFFFFFFFU << MDIOS_CWRFR_CWRF_Pos) 18042 #define MDIOS_CWRFR_CWRF MDIOS_CWRFR_CWRF_Msk 18045 #define MDIOS_RDFR_RDF_Pos (0U) 18046 #define MDIOS_RDFR_RDF_Msk (0xFFFFFFFFU << MDIOS_RDFR_RDF_Pos) 18047 #define MDIOS_RDFR_RDF MDIOS_RDFR_RDF_Msk 18050 #define MDIOS_CRDFR_CRDF_Pos (0U) 18051 #define MDIOS_CRDFR_CRDF_Msk (0xFFFFFFFFU << MDIOS_CRDFR_CRDF_Pos) 18052 #define MDIOS_CRDFR_CRDF MDIOS_CRDFR_CRDF_Msk 18055 #define MDIOS_SR_PERF_Pos (0U) 18056 #define MDIOS_SR_PERF_Msk (0x1U << MDIOS_SR_PERF_Pos) 18057 #define MDIOS_SR_PERF MDIOS_SR_PERF_Msk 18058 #define MDIOS_SR_SERF_Pos (1U) 18059 #define MDIOS_SR_SERF_Msk (0x1U << MDIOS_SR_SERF_Pos) 18060 #define MDIOS_SR_SERF MDIOS_SR_SERF_Msk 18061 #define MDIOS_SR_TERF_Pos (2U) 18062 #define MDIOS_SR_TERF_Msk (0x1U << MDIOS_SR_TERF_Pos) 18063 #define MDIOS_SR_TERF MDIOS_SR_TERF_Msk 18066 #define MDIOS_CLRFR_CPERF_Pos (0U) 18067 #define MDIOS_CLRFR_CPERF_Msk (0x1U << MDIOS_CLRFR_CPERF_Pos) 18068 #define MDIOS_CLRFR_CPERF MDIOS_CLRFR_CPERF_Msk 18069 #define MDIOS_CLRFR_CSERF_Pos (1U) 18070 #define MDIOS_CLRFR_CSERF_Msk (0x1U << MDIOS_CLRFR_CSERF_Pos) 18071 #define MDIOS_CLRFR_CSERF MDIOS_CLRFR_CSERF_Msk 18072 #define MDIOS_CLRFR_CTERF_Pos (2U) 18073 #define MDIOS_CLRFR_CTERF_Msk (0x1U << MDIOS_CLRFR_CTERF_Pos) 18074 #define MDIOS_CLRFR_CTERF MDIOS_CLRFR_CTERF_Msk 18082 #define DSI_VR_Pos (1U) 18083 #define DSI_VR_Msk (0x18999815U << DSI_VR_Pos) 18084 #define DSI_VR DSI_VR_Msk 18087 #define DSI_CR_EN_Pos (0U) 18088 #define DSI_CR_EN_Msk (0x1U << DSI_CR_EN_Pos) 18089 #define DSI_CR_EN DSI_CR_EN_Msk 18092 #define DSI_CCR_TXECKDIV_Pos (0U) 18093 #define DSI_CCR_TXECKDIV_Msk (0xFFU << DSI_CCR_TXECKDIV_Pos) 18094 #define DSI_CCR_TXECKDIV DSI_CCR_TXECKDIV_Msk 18095 #define DSI_CCR_TXECKDIV0_Pos (0U) 18096 #define DSI_CCR_TXECKDIV0_Msk (0x1U << DSI_CCR_TXECKDIV0_Pos) 18097 #define DSI_CCR_TXECKDIV0 DSI_CCR_TXECKDIV0_Msk 18098 #define DSI_CCR_TXECKDIV1_Pos (1U) 18099 #define DSI_CCR_TXECKDIV1_Msk (0x1U << DSI_CCR_TXECKDIV1_Pos) 18100 #define DSI_CCR_TXECKDIV1 DSI_CCR_TXECKDIV1_Msk 18101 #define DSI_CCR_TXECKDIV2_Pos (2U) 18102 #define DSI_CCR_TXECKDIV2_Msk (0x1U << DSI_CCR_TXECKDIV2_Pos) 18103 #define DSI_CCR_TXECKDIV2 DSI_CCR_TXECKDIV2_Msk 18104 #define DSI_CCR_TXECKDIV3_Pos (3U) 18105 #define DSI_CCR_TXECKDIV3_Msk (0x1U << DSI_CCR_TXECKDIV3_Pos) 18106 #define DSI_CCR_TXECKDIV3 DSI_CCR_TXECKDIV3_Msk 18107 #define DSI_CCR_TXECKDIV4_Pos (4U) 18108 #define DSI_CCR_TXECKDIV4_Msk (0x1U << DSI_CCR_TXECKDIV4_Pos) 18109 #define DSI_CCR_TXECKDIV4 DSI_CCR_TXECKDIV4_Msk 18110 #define DSI_CCR_TXECKDIV5_Pos (5U) 18111 #define DSI_CCR_TXECKDIV5_Msk (0x1U << DSI_CCR_TXECKDIV5_Pos) 18112 #define DSI_CCR_TXECKDIV5 DSI_CCR_TXECKDIV5_Msk 18113 #define DSI_CCR_TXECKDIV6_Pos (6U) 18114 #define DSI_CCR_TXECKDIV6_Msk (0x1U << DSI_CCR_TXECKDIV6_Pos) 18115 #define DSI_CCR_TXECKDIV6 DSI_CCR_TXECKDIV6_Msk 18116 #define DSI_CCR_TXECKDIV7_Pos (7U) 18117 #define DSI_CCR_TXECKDIV7_Msk (0x1U << DSI_CCR_TXECKDIV7_Pos) 18118 #define DSI_CCR_TXECKDIV7 DSI_CCR_TXECKDIV7_Msk 18120 #define DSI_CCR_TOCKDIV_Pos (8U) 18121 #define DSI_CCR_TOCKDIV_Msk (0xFFU << DSI_CCR_TOCKDIV_Pos) 18122 #define DSI_CCR_TOCKDIV DSI_CCR_TOCKDIV_Msk 18123 #define DSI_CCR_TOCKDIV0_Pos (8U) 18124 #define DSI_CCR_TOCKDIV0_Msk (0x1U << DSI_CCR_TOCKDIV0_Pos) 18125 #define DSI_CCR_TOCKDIV0 DSI_CCR_TOCKDIV0_Msk 18126 #define DSI_CCR_TOCKDIV1_Pos (9U) 18127 #define DSI_CCR_TOCKDIV1_Msk (0x1U << DSI_CCR_TOCKDIV1_Pos) 18128 #define DSI_CCR_TOCKDIV1 DSI_CCR_TOCKDIV1_Msk 18129 #define DSI_CCR_TOCKDIV2_Pos (10U) 18130 #define DSI_CCR_TOCKDIV2_Msk (0x1U << DSI_CCR_TOCKDIV2_Pos) 18131 #define DSI_CCR_TOCKDIV2 DSI_CCR_TOCKDIV2_Msk 18132 #define DSI_CCR_TOCKDIV3_Pos (11U) 18133 #define DSI_CCR_TOCKDIV3_Msk (0x1U << DSI_CCR_TOCKDIV3_Pos) 18134 #define DSI_CCR_TOCKDIV3 DSI_CCR_TOCKDIV3_Msk 18135 #define DSI_CCR_TOCKDIV4_Pos (12U) 18136 #define DSI_CCR_TOCKDIV4_Msk (0x1U << DSI_CCR_TOCKDIV4_Pos) 18137 #define DSI_CCR_TOCKDIV4 DSI_CCR_TOCKDIV4_Msk 18138 #define DSI_CCR_TOCKDIV5_Pos (13U) 18139 #define DSI_CCR_TOCKDIV5_Msk (0x1U << DSI_CCR_TOCKDIV5_Pos) 18140 #define DSI_CCR_TOCKDIV5 DSI_CCR_TOCKDIV5_Msk 18141 #define DSI_CCR_TOCKDIV6_Pos (14U) 18142 #define DSI_CCR_TOCKDIV6_Msk (0x1U << DSI_CCR_TOCKDIV6_Pos) 18143 #define DSI_CCR_TOCKDIV6 DSI_CCR_TOCKDIV6_Msk 18144 #define DSI_CCR_TOCKDIV7_Pos (15U) 18145 #define DSI_CCR_TOCKDIV7_Msk (0x1U << DSI_CCR_TOCKDIV7_Pos) 18146 #define DSI_CCR_TOCKDIV7 DSI_CCR_TOCKDIV7_Msk 18149 #define DSI_LVCIDR_VCID_Pos (0U) 18150 #define DSI_LVCIDR_VCID_Msk (0x3U << DSI_LVCIDR_VCID_Pos) 18151 #define DSI_LVCIDR_VCID DSI_LVCIDR_VCID_Msk 18152 #define DSI_LVCIDR_VCID0_Pos (0U) 18153 #define DSI_LVCIDR_VCID0_Msk (0x1U << DSI_LVCIDR_VCID0_Pos) 18154 #define DSI_LVCIDR_VCID0 DSI_LVCIDR_VCID0_Msk 18155 #define DSI_LVCIDR_VCID1_Pos (1U) 18156 #define DSI_LVCIDR_VCID1_Msk (0x1U << DSI_LVCIDR_VCID1_Pos) 18157 #define DSI_LVCIDR_VCID1 DSI_LVCIDR_VCID1_Msk 18160 #define DSI_LCOLCR_COLC_Pos (0U) 18161 #define DSI_LCOLCR_COLC_Msk (0xFU << DSI_LCOLCR_COLC_Pos) 18162 #define DSI_LCOLCR_COLC DSI_LCOLCR_COLC_Msk 18163 #define DSI_LCOLCR_COLC0_Pos (0U) 18164 #define DSI_LCOLCR_COLC0_Msk (0x1U << DSI_LCOLCR_COLC0_Pos) 18165 #define DSI_LCOLCR_COLC0 DSI_LCOLCR_COLC0_Msk 18166 #define DSI_LCOLCR_COLC1_Pos (5U) 18167 #define DSI_LCOLCR_COLC1_Msk (0x1U << DSI_LCOLCR_COLC1_Pos) 18168 #define DSI_LCOLCR_COLC1 DSI_LCOLCR_COLC1_Msk 18169 #define DSI_LCOLCR_COLC2_Pos (6U) 18170 #define DSI_LCOLCR_COLC2_Msk (0x1U << DSI_LCOLCR_COLC2_Pos) 18171 #define DSI_LCOLCR_COLC2 DSI_LCOLCR_COLC2_Msk 18172 #define DSI_LCOLCR_COLC3_Pos (7U) 18173 #define DSI_LCOLCR_COLC3_Msk (0x1U << DSI_LCOLCR_COLC3_Pos) 18174 #define DSI_LCOLCR_COLC3 DSI_LCOLCR_COLC3_Msk 18176 #define DSI_LCOLCR_LPE_Pos (8U) 18177 #define DSI_LCOLCR_LPE_Msk (0x1U << DSI_LCOLCR_LPE_Pos) 18178 #define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk 18181 #define DSI_LPCR_DEP_Pos (0U) 18182 #define DSI_LPCR_DEP_Msk (0x1U << DSI_LPCR_DEP_Pos) 18183 #define DSI_LPCR_DEP DSI_LPCR_DEP_Msk 18184 #define DSI_LPCR_VSP_Pos (1U) 18185 #define DSI_LPCR_VSP_Msk (0x1U << DSI_LPCR_VSP_Pos) 18186 #define DSI_LPCR_VSP DSI_LPCR_VSP_Msk 18187 #define DSI_LPCR_HSP_Pos (2U) 18188 #define DSI_LPCR_HSP_Msk (0x1U << DSI_LPCR_HSP_Pos) 18189 #define DSI_LPCR_HSP DSI_LPCR_HSP_Msk 18192 #define DSI_LPMCR_VLPSIZE_Pos (0U) 18193 #define DSI_LPMCR_VLPSIZE_Msk (0xFFU << DSI_LPMCR_VLPSIZE_Pos) 18194 #define DSI_LPMCR_VLPSIZE DSI_LPMCR_VLPSIZE_Msk 18195 #define DSI_LPMCR_VLPSIZE0_Pos (0U) 18196 #define DSI_LPMCR_VLPSIZE0_Msk (0x1U << DSI_LPMCR_VLPSIZE0_Pos) 18197 #define DSI_LPMCR_VLPSIZE0 DSI_LPMCR_VLPSIZE0_Msk 18198 #define DSI_LPMCR_VLPSIZE1_Pos (1U) 18199 #define DSI_LPMCR_VLPSIZE1_Msk (0x1U << DSI_LPMCR_VLPSIZE1_Pos) 18200 #define DSI_LPMCR_VLPSIZE1 DSI_LPMCR_VLPSIZE1_Msk 18201 #define DSI_LPMCR_VLPSIZE2_Pos (2U) 18202 #define DSI_LPMCR_VLPSIZE2_Msk (0x1U << DSI_LPMCR_VLPSIZE2_Pos) 18203 #define DSI_LPMCR_VLPSIZE2 DSI_LPMCR_VLPSIZE2_Msk 18204 #define DSI_LPMCR_VLPSIZE3_Pos (3U) 18205 #define DSI_LPMCR_VLPSIZE3_Msk (0x1U << DSI_LPMCR_VLPSIZE3_Pos) 18206 #define DSI_LPMCR_VLPSIZE3 DSI_LPMCR_VLPSIZE3_Msk 18207 #define DSI_LPMCR_VLPSIZE4_Pos (4U) 18208 #define DSI_LPMCR_VLPSIZE4_Msk (0x1U << DSI_LPMCR_VLPSIZE4_Pos) 18209 #define DSI_LPMCR_VLPSIZE4 DSI_LPMCR_VLPSIZE4_Msk 18210 #define DSI_LPMCR_VLPSIZE5_Pos (5U) 18211 #define DSI_LPMCR_VLPSIZE5_Msk (0x1U << DSI_LPMCR_VLPSIZE5_Pos) 18212 #define DSI_LPMCR_VLPSIZE5 DSI_LPMCR_VLPSIZE5_Msk 18213 #define DSI_LPMCR_VLPSIZE6_Pos (6U) 18214 #define DSI_LPMCR_VLPSIZE6_Msk (0x1U << DSI_LPMCR_VLPSIZE6_Pos) 18215 #define DSI_LPMCR_VLPSIZE6 DSI_LPMCR_VLPSIZE6_Msk 18216 #define DSI_LPMCR_VLPSIZE7_Pos (7U) 18217 #define DSI_LPMCR_VLPSIZE7_Msk (0x1U << DSI_LPMCR_VLPSIZE7_Pos) 18218 #define DSI_LPMCR_VLPSIZE7 DSI_LPMCR_VLPSIZE7_Msk 18220 #define DSI_LPMCR_LPSIZE_Pos (16U) 18221 #define DSI_LPMCR_LPSIZE_Msk (0xFFU << DSI_LPMCR_LPSIZE_Pos) 18222 #define DSI_LPMCR_LPSIZE DSI_LPMCR_LPSIZE_Msk 18223 #define DSI_LPMCR_LPSIZE0_Pos (16U) 18224 #define DSI_LPMCR_LPSIZE0_Msk (0x1U << DSI_LPMCR_LPSIZE0_Pos) 18225 #define DSI_LPMCR_LPSIZE0 DSI_LPMCR_LPSIZE0_Msk 18226 #define DSI_LPMCR_LPSIZE1_Pos (17U) 18227 #define DSI_LPMCR_LPSIZE1_Msk (0x1U << DSI_LPMCR_LPSIZE1_Pos) 18228 #define DSI_LPMCR_LPSIZE1 DSI_LPMCR_LPSIZE1_Msk 18229 #define DSI_LPMCR_LPSIZE2_Pos (18U) 18230 #define DSI_LPMCR_LPSIZE2_Msk (0x1U << DSI_LPMCR_LPSIZE2_Pos) 18231 #define DSI_LPMCR_LPSIZE2 DSI_LPMCR_LPSIZE2_Msk 18232 #define DSI_LPMCR_LPSIZE3_Pos (19U) 18233 #define DSI_LPMCR_LPSIZE3_Msk (0x1U << DSI_LPMCR_LPSIZE3_Pos) 18234 #define DSI_LPMCR_LPSIZE3 DSI_LPMCR_LPSIZE3_Msk 18235 #define DSI_LPMCR_LPSIZE4_Pos (20U) 18236 #define DSI_LPMCR_LPSIZE4_Msk (0x1U << DSI_LPMCR_LPSIZE4_Pos) 18237 #define DSI_LPMCR_LPSIZE4 DSI_LPMCR_LPSIZE4_Msk 18238 #define DSI_LPMCR_LPSIZE5_Pos (21U) 18239 #define DSI_LPMCR_LPSIZE5_Msk (0x1U << DSI_LPMCR_LPSIZE5_Pos) 18240 #define DSI_LPMCR_LPSIZE5 DSI_LPMCR_LPSIZE5_Msk 18241 #define DSI_LPMCR_LPSIZE6_Pos (22U) 18242 #define DSI_LPMCR_LPSIZE6_Msk (0x1U << DSI_LPMCR_LPSIZE6_Pos) 18243 #define DSI_LPMCR_LPSIZE6 DSI_LPMCR_LPSIZE6_Msk 18244 #define DSI_LPMCR_LPSIZE7_Pos (23U) 18245 #define DSI_LPMCR_LPSIZE7_Msk (0x1U << DSI_LPMCR_LPSIZE7_Pos) 18246 #define DSI_LPMCR_LPSIZE7 DSI_LPMCR_LPSIZE7_Msk 18249 #define DSI_PCR_ETTXE_Pos (0U) 18250 #define DSI_PCR_ETTXE_Msk (0x1U << DSI_PCR_ETTXE_Pos) 18251 #define DSI_PCR_ETTXE DSI_PCR_ETTXE_Msk 18252 #define DSI_PCR_ETRXE_Pos (1U) 18253 #define DSI_PCR_ETRXE_Msk (0x1U << DSI_PCR_ETRXE_Pos) 18254 #define DSI_PCR_ETRXE DSI_PCR_ETRXE_Msk 18255 #define DSI_PCR_BTAE_Pos (2U) 18256 #define DSI_PCR_BTAE_Msk (0x1U << DSI_PCR_BTAE_Pos) 18257 #define DSI_PCR_BTAE DSI_PCR_BTAE_Msk 18258 #define DSI_PCR_ECCRXE_Pos (3U) 18259 #define DSI_PCR_ECCRXE_Msk (0x1U << DSI_PCR_ECCRXE_Pos) 18260 #define DSI_PCR_ECCRXE DSI_PCR_ECCRXE_Msk 18261 #define DSI_PCR_CRCRXE_Pos (4U) 18262 #define DSI_PCR_CRCRXE_Msk (0x1U << DSI_PCR_CRCRXE_Pos) 18263 #define DSI_PCR_CRCRXE DSI_PCR_CRCRXE_Msk 18266 #define DSI_GVCIDR_VCID_Pos (0U) 18267 #define DSI_GVCIDR_VCID_Msk (0x3U << DSI_GVCIDR_VCID_Pos) 18268 #define DSI_GVCIDR_VCID DSI_GVCIDR_VCID_Msk 18269 #define DSI_GVCIDR_VCID0_Pos (0U) 18270 #define DSI_GVCIDR_VCID0_Msk (0x1U << DSI_GVCIDR_VCID0_Pos) 18271 #define DSI_GVCIDR_VCID0 DSI_GVCIDR_VCID0_Msk 18272 #define DSI_GVCIDR_VCID1_Pos (1U) 18273 #define DSI_GVCIDR_VCID1_Msk (0x1U << DSI_GVCIDR_VCID1_Pos) 18274 #define DSI_GVCIDR_VCID1 DSI_GVCIDR_VCID1_Msk 18277 #define DSI_MCR_CMDM_Pos (0U) 18278 #define DSI_MCR_CMDM_Msk (0x1U << DSI_MCR_CMDM_Pos) 18279 #define DSI_MCR_CMDM DSI_MCR_CMDM_Msk 18282 #define DSI_VMCR_VMT_Pos (0U) 18283 #define DSI_VMCR_VMT_Msk (0x3U << DSI_VMCR_VMT_Pos) 18284 #define DSI_VMCR_VMT DSI_VMCR_VMT_Msk 18285 #define DSI_VMCR_VMT0_Pos (0U) 18286 #define DSI_VMCR_VMT0_Msk (0x1U << DSI_VMCR_VMT0_Pos) 18287 #define DSI_VMCR_VMT0 DSI_VMCR_VMT0_Msk 18288 #define DSI_VMCR_VMT1_Pos (1U) 18289 #define DSI_VMCR_VMT1_Msk (0x1U << DSI_VMCR_VMT1_Pos) 18290 #define DSI_VMCR_VMT1 DSI_VMCR_VMT1_Msk 18292 #define DSI_VMCR_LPVSAE_Pos (8U) 18293 #define DSI_VMCR_LPVSAE_Msk (0x1U << DSI_VMCR_LPVSAE_Pos) 18294 #define DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk 18295 #define DSI_VMCR_LPVBPE_Pos (9U) 18296 #define DSI_VMCR_LPVBPE_Msk (0x1U << DSI_VMCR_LPVBPE_Pos) 18297 #define DSI_VMCR_LPVBPE DSI_VMCR_LPVBPE_Msk 18298 #define DSI_VMCR_LPVFPE_Pos (10U) 18299 #define DSI_VMCR_LPVFPE_Msk (0x1U << DSI_VMCR_LPVFPE_Pos) 18300 #define DSI_VMCR_LPVFPE DSI_VMCR_LPVFPE_Msk 18301 #define DSI_VMCR_LPVAE_Pos (11U) 18302 #define DSI_VMCR_LPVAE_Msk (0x1U << DSI_VMCR_LPVAE_Pos) 18303 #define DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk 18304 #define DSI_VMCR_LPHBPE_Pos (12U) 18305 #define DSI_VMCR_LPHBPE_Msk (0x1U << DSI_VMCR_LPHBPE_Pos) 18306 #define DSI_VMCR_LPHBPE DSI_VMCR_LPHBPE_Msk 18307 #define DSI_VMCR_LPHFPE_Pos (13U) 18308 #define DSI_VMCR_LPHFPE_Msk (0x1U << DSI_VMCR_LPHFPE_Pos) 18309 #define DSI_VMCR_LPHFPE DSI_VMCR_LPHFPE_Msk 18310 #define DSI_VMCR_FBTAAE_Pos (14U) 18311 #define DSI_VMCR_FBTAAE_Msk (0x1U << DSI_VMCR_FBTAAE_Pos) 18312 #define DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk 18313 #define DSI_VMCR_LPCE_Pos (15U) 18314 #define DSI_VMCR_LPCE_Msk (0x1U << DSI_VMCR_LPCE_Pos) 18315 #define DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk 18316 #define DSI_VMCR_PGE_Pos (16U) 18317 #define DSI_VMCR_PGE_Msk (0x1U << DSI_VMCR_PGE_Pos) 18318 #define DSI_VMCR_PGE DSI_VMCR_PGE_Msk 18319 #define DSI_VMCR_PGM_Pos (20U) 18320 #define DSI_VMCR_PGM_Msk (0x1U << DSI_VMCR_PGM_Pos) 18321 #define DSI_VMCR_PGM DSI_VMCR_PGM_Msk 18322 #define DSI_VMCR_PGO_Pos (24U) 18323 #define DSI_VMCR_PGO_Msk (0x1U << DSI_VMCR_PGO_Pos) 18324 #define DSI_VMCR_PGO DSI_VMCR_PGO_Msk 18327 #define DSI_VPCR_VPSIZE_Pos (0U) 18328 #define DSI_VPCR_VPSIZE_Msk (0x3FFFU << DSI_VPCR_VPSIZE_Pos) 18329 #define DSI_VPCR_VPSIZE DSI_VPCR_VPSIZE_Msk 18330 #define DSI_VPCR_VPSIZE0_Pos (0U) 18331 #define DSI_VPCR_VPSIZE0_Msk (0x1U << DSI_VPCR_VPSIZE0_Pos) 18332 #define DSI_VPCR_VPSIZE0 DSI_VPCR_VPSIZE0_Msk 18333 #define DSI_VPCR_VPSIZE1_Pos (1U) 18334 #define DSI_VPCR_VPSIZE1_Msk (0x1U << DSI_VPCR_VPSIZE1_Pos) 18335 #define DSI_VPCR_VPSIZE1 DSI_VPCR_VPSIZE1_Msk 18336 #define DSI_VPCR_VPSIZE2_Pos (2U) 18337 #define DSI_VPCR_VPSIZE2_Msk (0x1U << DSI_VPCR_VPSIZE2_Pos) 18338 #define DSI_VPCR_VPSIZE2 DSI_VPCR_VPSIZE2_Msk 18339 #define DSI_VPCR_VPSIZE3_Pos (3U) 18340 #define DSI_VPCR_VPSIZE3_Msk (0x1U << DSI_VPCR_VPSIZE3_Pos) 18341 #define DSI_VPCR_VPSIZE3 DSI_VPCR_VPSIZE3_Msk 18342 #define DSI_VPCR_VPSIZE4_Pos (4U) 18343 #define DSI_VPCR_VPSIZE4_Msk (0x1U << DSI_VPCR_VPSIZE4_Pos) 18344 #define DSI_VPCR_VPSIZE4 DSI_VPCR_VPSIZE4_Msk 18345 #define DSI_VPCR_VPSIZE5_Pos (5U) 18346 #define DSI_VPCR_VPSIZE5_Msk (0x1U << DSI_VPCR_VPSIZE5_Pos) 18347 #define DSI_VPCR_VPSIZE5 DSI_VPCR_VPSIZE5_Msk 18348 #define DSI_VPCR_VPSIZE6_Pos (6U) 18349 #define DSI_VPCR_VPSIZE6_Msk (0x1U << DSI_VPCR_VPSIZE6_Pos) 18350 #define DSI_VPCR_VPSIZE6 DSI_VPCR_VPSIZE6_Msk 18351 #define DSI_VPCR_VPSIZE7_Pos (7U) 18352 #define DSI_VPCR_VPSIZE7_Msk (0x1U << DSI_VPCR_VPSIZE7_Pos) 18353 #define DSI_VPCR_VPSIZE7 DSI_VPCR_VPSIZE7_Msk 18354 #define DSI_VPCR_VPSIZE8_Pos (8U) 18355 #define DSI_VPCR_VPSIZE8_Msk (0x1U << DSI_VPCR_VPSIZE8_Pos) 18356 #define DSI_VPCR_VPSIZE8 DSI_VPCR_VPSIZE8_Msk 18357 #define DSI_VPCR_VPSIZE9_Pos (9U) 18358 #define DSI_VPCR_VPSIZE9_Msk (0x1U << DSI_VPCR_VPSIZE9_Pos) 18359 #define DSI_VPCR_VPSIZE9 DSI_VPCR_VPSIZE9_Msk 18360 #define DSI_VPCR_VPSIZE10_Pos (10U) 18361 #define DSI_VPCR_VPSIZE10_Msk (0x1U << DSI_VPCR_VPSIZE10_Pos) 18362 #define DSI_VPCR_VPSIZE10 DSI_VPCR_VPSIZE10_Msk 18363 #define DSI_VPCR_VPSIZE11_Pos (11U) 18364 #define DSI_VPCR_VPSIZE11_Msk (0x1U << DSI_VPCR_VPSIZE11_Pos) 18365 #define DSI_VPCR_VPSIZE11 DSI_VPCR_VPSIZE11_Msk 18366 #define DSI_VPCR_VPSIZE12_Pos (12U) 18367 #define DSI_VPCR_VPSIZE12_Msk (0x1U << DSI_VPCR_VPSIZE12_Pos) 18368 #define DSI_VPCR_VPSIZE12 DSI_VPCR_VPSIZE12_Msk 18369 #define DSI_VPCR_VPSIZE13_Pos (13U) 18370 #define DSI_VPCR_VPSIZE13_Msk (0x1U << DSI_VPCR_VPSIZE13_Pos) 18371 #define DSI_VPCR_VPSIZE13 DSI_VPCR_VPSIZE13_Msk 18374 #define DSI_VCCR_NUMC_Pos (0U) 18375 #define DSI_VCCR_NUMC_Msk (0x1FFFU << DSI_VCCR_NUMC_Pos) 18376 #define DSI_VCCR_NUMC DSI_VCCR_NUMC_Msk 18377 #define DSI_VCCR_NUMC0_Pos (0U) 18378 #define DSI_VCCR_NUMC0_Msk (0x1U << DSI_VCCR_NUMC0_Pos) 18379 #define DSI_VCCR_NUMC0 DSI_VCCR_NUMC0_Msk 18380 #define DSI_VCCR_NUMC1_Pos (1U) 18381 #define DSI_VCCR_NUMC1_Msk (0x1U << DSI_VCCR_NUMC1_Pos) 18382 #define DSI_VCCR_NUMC1 DSI_VCCR_NUMC1_Msk 18383 #define DSI_VCCR_NUMC2_Pos (2U) 18384 #define DSI_VCCR_NUMC2_Msk (0x1U << DSI_VCCR_NUMC2_Pos) 18385 #define DSI_VCCR_NUMC2 DSI_VCCR_NUMC2_Msk 18386 #define DSI_VCCR_NUMC3_Pos (3U) 18387 #define DSI_VCCR_NUMC3_Msk (0x1U << DSI_VCCR_NUMC3_Pos) 18388 #define DSI_VCCR_NUMC3 DSI_VCCR_NUMC3_Msk 18389 #define DSI_VCCR_NUMC4_Pos (4U) 18390 #define DSI_VCCR_NUMC4_Msk (0x1U << DSI_VCCR_NUMC4_Pos) 18391 #define DSI_VCCR_NUMC4 DSI_VCCR_NUMC4_Msk 18392 #define DSI_VCCR_NUMC5_Pos (5U) 18393 #define DSI_VCCR_NUMC5_Msk (0x1U << DSI_VCCR_NUMC5_Pos) 18394 #define DSI_VCCR_NUMC5 DSI_VCCR_NUMC5_Msk 18395 #define DSI_VCCR_NUMC6_Pos (6U) 18396 #define DSI_VCCR_NUMC6_Msk (0x1U << DSI_VCCR_NUMC6_Pos) 18397 #define DSI_VCCR_NUMC6 DSI_VCCR_NUMC6_Msk 18398 #define DSI_VCCR_NUMC7_Pos (7U) 18399 #define DSI_VCCR_NUMC7_Msk (0x1U << DSI_VCCR_NUMC7_Pos) 18400 #define DSI_VCCR_NUMC7 DSI_VCCR_NUMC7_Msk 18401 #define DSI_VCCR_NUMC8_Pos (8U) 18402 #define DSI_VCCR_NUMC8_Msk (0x1U << DSI_VCCR_NUMC8_Pos) 18403 #define DSI_VCCR_NUMC8 DSI_VCCR_NUMC8_Msk 18404 #define DSI_VCCR_NUMC9_Pos (9U) 18405 #define DSI_VCCR_NUMC9_Msk (0x1U << DSI_VCCR_NUMC9_Pos) 18406 #define DSI_VCCR_NUMC9 DSI_VCCR_NUMC9_Msk 18407 #define DSI_VCCR_NUMC10_Pos (10U) 18408 #define DSI_VCCR_NUMC10_Msk (0x1U << DSI_VCCR_NUMC10_Pos) 18409 #define DSI_VCCR_NUMC10 DSI_VCCR_NUMC10_Msk 18410 #define DSI_VCCR_NUMC11_Pos (11U) 18411 #define DSI_VCCR_NUMC11_Msk (0x1U << DSI_VCCR_NUMC11_Pos) 18412 #define DSI_VCCR_NUMC11 DSI_VCCR_NUMC11_Msk 18413 #define DSI_VCCR_NUMC12_Pos (12U) 18414 #define DSI_VCCR_NUMC12_Msk (0x1U << DSI_VCCR_NUMC12_Pos) 18415 #define DSI_VCCR_NUMC12 DSI_VCCR_NUMC12_Msk 18418 #define DSI_VNPCR_NPSIZE_Pos (0U) 18419 #define DSI_VNPCR_NPSIZE_Msk (0x1FFFU << DSI_VNPCR_NPSIZE_Pos) 18420 #define DSI_VNPCR_NPSIZE DSI_VNPCR_NPSIZE_Msk 18421 #define DSI_VNPCR_NPSIZE0_Pos (0U) 18422 #define DSI_VNPCR_NPSIZE0_Msk (0x1U << DSI_VNPCR_NPSIZE0_Pos) 18423 #define DSI_VNPCR_NPSIZE0 DSI_VNPCR_NPSIZE0_Msk 18424 #define DSI_VNPCR_NPSIZE1_Pos (1U) 18425 #define DSI_VNPCR_NPSIZE1_Msk (0x1U << DSI_VNPCR_NPSIZE1_Pos) 18426 #define DSI_VNPCR_NPSIZE1 DSI_VNPCR_NPSIZE1_Msk 18427 #define DSI_VNPCR_NPSIZE2_Pos (2U) 18428 #define DSI_VNPCR_NPSIZE2_Msk (0x1U << DSI_VNPCR_NPSIZE2_Pos) 18429 #define DSI_VNPCR_NPSIZE2 DSI_VNPCR_NPSIZE2_Msk 18430 #define DSI_VNPCR_NPSIZE3_Pos (3U) 18431 #define DSI_VNPCR_NPSIZE3_Msk (0x1U << DSI_VNPCR_NPSIZE3_Pos) 18432 #define DSI_VNPCR_NPSIZE3 DSI_VNPCR_NPSIZE3_Msk 18433 #define DSI_VNPCR_NPSIZE4_Pos (4U) 18434 #define DSI_VNPCR_NPSIZE4_Msk (0x1U << DSI_VNPCR_NPSIZE4_Pos) 18435 #define DSI_VNPCR_NPSIZE4 DSI_VNPCR_NPSIZE4_Msk 18436 #define DSI_VNPCR_NPSIZE5_Pos (5U) 18437 #define DSI_VNPCR_NPSIZE5_Msk (0x1U << DSI_VNPCR_NPSIZE5_Pos) 18438 #define DSI_VNPCR_NPSIZE5 DSI_VNPCR_NPSIZE5_Msk 18439 #define DSI_VNPCR_NPSIZE6_Pos (6U) 18440 #define DSI_VNPCR_NPSIZE6_Msk (0x1U << DSI_VNPCR_NPSIZE6_Pos) 18441 #define DSI_VNPCR_NPSIZE6 DSI_VNPCR_NPSIZE6_Msk 18442 #define DSI_VNPCR_NPSIZE7_Pos (7U) 18443 #define DSI_VNPCR_NPSIZE7_Msk (0x1U << DSI_VNPCR_NPSIZE7_Pos) 18444 #define DSI_VNPCR_NPSIZE7 DSI_VNPCR_NPSIZE7_Msk 18445 #define DSI_VNPCR_NPSIZE8_Pos (8U) 18446 #define DSI_VNPCR_NPSIZE8_Msk (0x1U << DSI_VNPCR_NPSIZE8_Pos) 18447 #define DSI_VNPCR_NPSIZE8 DSI_VNPCR_NPSIZE8_Msk 18448 #define DSI_VNPCR_NPSIZE9_Pos (9U) 18449 #define DSI_VNPCR_NPSIZE9_Msk (0x1U << DSI_VNPCR_NPSIZE9_Pos) 18450 #define DSI_VNPCR_NPSIZE9 DSI_VNPCR_NPSIZE9_Msk 18451 #define DSI_VNPCR_NPSIZE10_Pos (10U) 18452 #define DSI_VNPCR_NPSIZE10_Msk (0x1U << DSI_VNPCR_NPSIZE10_Pos) 18453 #define DSI_VNPCR_NPSIZE10 DSI_VNPCR_NPSIZE10_Msk 18454 #define DSI_VNPCR_NPSIZE11_Pos (11U) 18455 #define DSI_VNPCR_NPSIZE11_Msk (0x1U << DSI_VNPCR_NPSIZE11_Pos) 18456 #define DSI_VNPCR_NPSIZE11 DSI_VNPCR_NPSIZE11_Msk 18457 #define DSI_VNPCR_NPSIZE12_Pos (12U) 18458 #define DSI_VNPCR_NPSIZE12_Msk (0x1U << DSI_VNPCR_NPSIZE12_Pos) 18459 #define DSI_VNPCR_NPSIZE12 DSI_VNPCR_NPSIZE12_Msk 18462 #define DSI_VHSACR_HSA_Pos (0U) 18463 #define DSI_VHSACR_HSA_Msk (0xFFFU << DSI_VHSACR_HSA_Pos) 18464 #define DSI_VHSACR_HSA DSI_VHSACR_HSA_Msk 18465 #define DSI_VHSACR_HSA0_Pos (0U) 18466 #define DSI_VHSACR_HSA0_Msk (0x1U << DSI_VHSACR_HSA0_Pos) 18467 #define DSI_VHSACR_HSA0 DSI_VHSACR_HSA0_Msk 18468 #define DSI_VHSACR_HSA1_Pos (1U) 18469 #define DSI_VHSACR_HSA1_Msk (0x1U << DSI_VHSACR_HSA1_Pos) 18470 #define DSI_VHSACR_HSA1 DSI_VHSACR_HSA1_Msk 18471 #define DSI_VHSACR_HSA2_Pos (2U) 18472 #define DSI_VHSACR_HSA2_Msk (0x1U << DSI_VHSACR_HSA2_Pos) 18473 #define DSI_VHSACR_HSA2 DSI_VHSACR_HSA2_Msk 18474 #define DSI_VHSACR_HSA3_Pos (3U) 18475 #define DSI_VHSACR_HSA3_Msk (0x1U << DSI_VHSACR_HSA3_Pos) 18476 #define DSI_VHSACR_HSA3 DSI_VHSACR_HSA3_Msk 18477 #define DSI_VHSACR_HSA4_Pos (4U) 18478 #define DSI_VHSACR_HSA4_Msk (0x1U << DSI_VHSACR_HSA4_Pos) 18479 #define DSI_VHSACR_HSA4 DSI_VHSACR_HSA4_Msk 18480 #define DSI_VHSACR_HSA5_Pos (5U) 18481 #define DSI_VHSACR_HSA5_Msk (0x1U << DSI_VHSACR_HSA5_Pos) 18482 #define DSI_VHSACR_HSA5 DSI_VHSACR_HSA5_Msk 18483 #define DSI_VHSACR_HSA6_Pos (6U) 18484 #define DSI_VHSACR_HSA6_Msk (0x1U << DSI_VHSACR_HSA6_Pos) 18485 #define DSI_VHSACR_HSA6 DSI_VHSACR_HSA6_Msk 18486 #define DSI_VHSACR_HSA7_Pos (7U) 18487 #define DSI_VHSACR_HSA7_Msk (0x1U << DSI_VHSACR_HSA7_Pos) 18488 #define DSI_VHSACR_HSA7 DSI_VHSACR_HSA7_Msk 18489 #define DSI_VHSACR_HSA8_Pos (8U) 18490 #define DSI_VHSACR_HSA8_Msk (0x1U << DSI_VHSACR_HSA8_Pos) 18491 #define DSI_VHSACR_HSA8 DSI_VHSACR_HSA8_Msk 18492 #define DSI_VHSACR_HSA9_Pos (9U) 18493 #define DSI_VHSACR_HSA9_Msk (0x1U << DSI_VHSACR_HSA9_Pos) 18494 #define DSI_VHSACR_HSA9 DSI_VHSACR_HSA9_Msk 18495 #define DSI_VHSACR_HSA10_Pos (10U) 18496 #define DSI_VHSACR_HSA10_Msk (0x1U << DSI_VHSACR_HSA10_Pos) 18497 #define DSI_VHSACR_HSA10 DSI_VHSACR_HSA10_Msk 18498 #define DSI_VHSACR_HSA11_Pos (11U) 18499 #define DSI_VHSACR_HSA11_Msk (0x1U << DSI_VHSACR_HSA11_Pos) 18500 #define DSI_VHSACR_HSA11 DSI_VHSACR_HSA11_Msk 18503 #define DSI_VHBPCR_HBP_Pos (0U) 18504 #define DSI_VHBPCR_HBP_Msk (0xFFFU << DSI_VHBPCR_HBP_Pos) 18505 #define DSI_VHBPCR_HBP DSI_VHBPCR_HBP_Msk 18506 #define DSI_VHBPCR_HBP0_Pos (0U) 18507 #define DSI_VHBPCR_HBP0_Msk (0x1U << DSI_VHBPCR_HBP0_Pos) 18508 #define DSI_VHBPCR_HBP0 DSI_VHBPCR_HBP0_Msk 18509 #define DSI_VHBPCR_HBP1_Pos (1U) 18510 #define DSI_VHBPCR_HBP1_Msk (0x1U << DSI_VHBPCR_HBP1_Pos) 18511 #define DSI_VHBPCR_HBP1 DSI_VHBPCR_HBP1_Msk 18512 #define DSI_VHBPCR_HBP2_Pos (2U) 18513 #define DSI_VHBPCR_HBP2_Msk (0x1U << DSI_VHBPCR_HBP2_Pos) 18514 #define DSI_VHBPCR_HBP2 DSI_VHBPCR_HBP2_Msk 18515 #define DSI_VHBPCR_HBP3_Pos (3U) 18516 #define DSI_VHBPCR_HBP3_Msk (0x1U << DSI_VHBPCR_HBP3_Pos) 18517 #define DSI_VHBPCR_HBP3 DSI_VHBPCR_HBP3_Msk 18518 #define DSI_VHBPCR_HBP4_Pos (4U) 18519 #define DSI_VHBPCR_HBP4_Msk (0x1U << DSI_VHBPCR_HBP4_Pos) 18520 #define DSI_VHBPCR_HBP4 DSI_VHBPCR_HBP4_Msk 18521 #define DSI_VHBPCR_HBP5_Pos (5U) 18522 #define DSI_VHBPCR_HBP5_Msk (0x1U << DSI_VHBPCR_HBP5_Pos) 18523 #define DSI_VHBPCR_HBP5 DSI_VHBPCR_HBP5_Msk 18524 #define DSI_VHBPCR_HBP6_Pos (6U) 18525 #define DSI_VHBPCR_HBP6_Msk (0x1U << DSI_VHBPCR_HBP6_Pos) 18526 #define DSI_VHBPCR_HBP6 DSI_VHBPCR_HBP6_Msk 18527 #define DSI_VHBPCR_HBP7_Pos (7U) 18528 #define DSI_VHBPCR_HBP7_Msk (0x1U << DSI_VHBPCR_HBP7_Pos) 18529 #define DSI_VHBPCR_HBP7 DSI_VHBPCR_HBP7_Msk 18530 #define DSI_VHBPCR_HBP8_Pos (8U) 18531 #define DSI_VHBPCR_HBP8_Msk (0x1U << DSI_VHBPCR_HBP8_Pos) 18532 #define DSI_VHBPCR_HBP8 DSI_VHBPCR_HBP8_Msk 18533 #define DSI_VHBPCR_HBP9_Pos (9U) 18534 #define DSI_VHBPCR_HBP9_Msk (0x1U << DSI_VHBPCR_HBP9_Pos) 18535 #define DSI_VHBPCR_HBP9 DSI_VHBPCR_HBP9_Msk 18536 #define DSI_VHBPCR_HBP10_Pos (10U) 18537 #define DSI_VHBPCR_HBP10_Msk (0x1U << DSI_VHBPCR_HBP10_Pos) 18538 #define DSI_VHBPCR_HBP10 DSI_VHBPCR_HBP10_Msk 18539 #define DSI_VHBPCR_HBP11_Pos (11U) 18540 #define DSI_VHBPCR_HBP11_Msk (0x1U << DSI_VHBPCR_HBP11_Pos) 18541 #define DSI_VHBPCR_HBP11 DSI_VHBPCR_HBP11_Msk 18544 #define DSI_VLCR_HLINE_Pos (0U) 18545 #define DSI_VLCR_HLINE_Msk (0x7FFFU << DSI_VLCR_HLINE_Pos) 18546 #define DSI_VLCR_HLINE DSI_VLCR_HLINE_Msk 18547 #define DSI_VLCR_HLINE0_Pos (0U) 18548 #define DSI_VLCR_HLINE0_Msk (0x1U << DSI_VLCR_HLINE0_Pos) 18549 #define DSI_VLCR_HLINE0 DSI_VLCR_HLINE0_Msk 18550 #define DSI_VLCR_HLINE1_Pos (1U) 18551 #define DSI_VLCR_HLINE1_Msk (0x1U << DSI_VLCR_HLINE1_Pos) 18552 #define DSI_VLCR_HLINE1 DSI_VLCR_HLINE1_Msk 18553 #define DSI_VLCR_HLINE2_Pos (2U) 18554 #define DSI_VLCR_HLINE2_Msk (0x1U << DSI_VLCR_HLINE2_Pos) 18555 #define DSI_VLCR_HLINE2 DSI_VLCR_HLINE2_Msk 18556 #define DSI_VLCR_HLINE3_Pos (3U) 18557 #define DSI_VLCR_HLINE3_Msk (0x1U << DSI_VLCR_HLINE3_Pos) 18558 #define DSI_VLCR_HLINE3 DSI_VLCR_HLINE3_Msk 18559 #define DSI_VLCR_HLINE4_Pos (4U) 18560 #define DSI_VLCR_HLINE4_Msk (0x1U << DSI_VLCR_HLINE4_Pos) 18561 #define DSI_VLCR_HLINE4 DSI_VLCR_HLINE4_Msk 18562 #define DSI_VLCR_HLINE5_Pos (5U) 18563 #define DSI_VLCR_HLINE5_Msk (0x1U << DSI_VLCR_HLINE5_Pos) 18564 #define DSI_VLCR_HLINE5 DSI_VLCR_HLINE5_Msk 18565 #define DSI_VLCR_HLINE6_Pos (6U) 18566 #define DSI_VLCR_HLINE6_Msk (0x1U << DSI_VLCR_HLINE6_Pos) 18567 #define DSI_VLCR_HLINE6 DSI_VLCR_HLINE6_Msk 18568 #define DSI_VLCR_HLINE7_Pos (7U) 18569 #define DSI_VLCR_HLINE7_Msk (0x1U << DSI_VLCR_HLINE7_Pos) 18570 #define DSI_VLCR_HLINE7 DSI_VLCR_HLINE7_Msk 18571 #define DSI_VLCR_HLINE8_Pos (8U) 18572 #define DSI_VLCR_HLINE8_Msk (0x1U << DSI_VLCR_HLINE8_Pos) 18573 #define DSI_VLCR_HLINE8 DSI_VLCR_HLINE8_Msk 18574 #define DSI_VLCR_HLINE9_Pos (9U) 18575 #define DSI_VLCR_HLINE9_Msk (0x1U << DSI_VLCR_HLINE9_Pos) 18576 #define DSI_VLCR_HLINE9 DSI_VLCR_HLINE9_Msk 18577 #define DSI_VLCR_HLINE10_Pos (10U) 18578 #define DSI_VLCR_HLINE10_Msk (0x1U << DSI_VLCR_HLINE10_Pos) 18579 #define DSI_VLCR_HLINE10 DSI_VLCR_HLINE10_Msk 18580 #define DSI_VLCR_HLINE11_Pos (11U) 18581 #define DSI_VLCR_HLINE11_Msk (0x1U << DSI_VLCR_HLINE11_Pos) 18582 #define DSI_VLCR_HLINE11 DSI_VLCR_HLINE11_Msk 18583 #define DSI_VLCR_HLINE12_Pos (12U) 18584 #define DSI_VLCR_HLINE12_Msk (0x1U << DSI_VLCR_HLINE12_Pos) 18585 #define DSI_VLCR_HLINE12 DSI_VLCR_HLINE12_Msk 18586 #define DSI_VLCR_HLINE13_Pos (13U) 18587 #define DSI_VLCR_HLINE13_Msk (0x1U << DSI_VLCR_HLINE13_Pos) 18588 #define DSI_VLCR_HLINE13 DSI_VLCR_HLINE13_Msk 18589 #define DSI_VLCR_HLINE14_Pos (14U) 18590 #define DSI_VLCR_HLINE14_Msk (0x1U << DSI_VLCR_HLINE14_Pos) 18591 #define DSI_VLCR_HLINE14 DSI_VLCR_HLINE14_Msk 18594 #define DSI_VVSACR_VSA_Pos (0U) 18595 #define DSI_VVSACR_VSA_Msk (0x3FFU << DSI_VVSACR_VSA_Pos) 18596 #define DSI_VVSACR_VSA DSI_VVSACR_VSA_Msk 18597 #define DSI_VVSACR_VSA0_Pos (0U) 18598 #define DSI_VVSACR_VSA0_Msk (0x1U << DSI_VVSACR_VSA0_Pos) 18599 #define DSI_VVSACR_VSA0 DSI_VVSACR_VSA0_Msk 18600 #define DSI_VVSACR_VSA1_Pos (1U) 18601 #define DSI_VVSACR_VSA1_Msk (0x1U << DSI_VVSACR_VSA1_Pos) 18602 #define DSI_VVSACR_VSA1 DSI_VVSACR_VSA1_Msk 18603 #define DSI_VVSACR_VSA2_Pos (2U) 18604 #define DSI_VVSACR_VSA2_Msk (0x1U << DSI_VVSACR_VSA2_Pos) 18605 #define DSI_VVSACR_VSA2 DSI_VVSACR_VSA2_Msk 18606 #define DSI_VVSACR_VSA3_Pos (3U) 18607 #define DSI_VVSACR_VSA3_Msk (0x1U << DSI_VVSACR_VSA3_Pos) 18608 #define DSI_VVSACR_VSA3 DSI_VVSACR_VSA3_Msk 18609 #define DSI_VVSACR_VSA4_Pos (4U) 18610 #define DSI_VVSACR_VSA4_Msk (0x1U << DSI_VVSACR_VSA4_Pos) 18611 #define DSI_VVSACR_VSA4 DSI_VVSACR_VSA4_Msk 18612 #define DSI_VVSACR_VSA5_Pos (5U) 18613 #define DSI_VVSACR_VSA5_Msk (0x1U << DSI_VVSACR_VSA5_Pos) 18614 #define DSI_VVSACR_VSA5 DSI_VVSACR_VSA5_Msk 18615 #define DSI_VVSACR_VSA6_Pos (6U) 18616 #define DSI_VVSACR_VSA6_Msk (0x1U << DSI_VVSACR_VSA6_Pos) 18617 #define DSI_VVSACR_VSA6 DSI_VVSACR_VSA6_Msk 18618 #define DSI_VVSACR_VSA7_Pos (7U) 18619 #define DSI_VVSACR_VSA7_Msk (0x1U << DSI_VVSACR_VSA7_Pos) 18620 #define DSI_VVSACR_VSA7 DSI_VVSACR_VSA7_Msk 18621 #define DSI_VVSACR_VSA8_Pos (8U) 18622 #define DSI_VVSACR_VSA8_Msk (0x1U << DSI_VVSACR_VSA8_Pos) 18623 #define DSI_VVSACR_VSA8 DSI_VVSACR_VSA8_Msk 18624 #define DSI_VVSACR_VSA9_Pos (9U) 18625 #define DSI_VVSACR_VSA9_Msk (0x1U << DSI_VVSACR_VSA9_Pos) 18626 #define DSI_VVSACR_VSA9 DSI_VVSACR_VSA9_Msk 18629 #define DSI_VVBPCR_VBP_Pos (0U) 18630 #define DSI_VVBPCR_VBP_Msk (0x3FFU << DSI_VVBPCR_VBP_Pos) 18631 #define DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk 18632 #define DSI_VVBPCR_VBP0_Pos (0U) 18633 #define DSI_VVBPCR_VBP0_Msk (0x1U << DSI_VVBPCR_VBP0_Pos) 18634 #define DSI_VVBPCR_VBP0 DSI_VVBPCR_VBP0_Msk 18635 #define DSI_VVBPCR_VBP1_Pos (1U) 18636 #define DSI_VVBPCR_VBP1_Msk (0x1U << DSI_VVBPCR_VBP1_Pos) 18637 #define DSI_VVBPCR_VBP1 DSI_VVBPCR_VBP1_Msk 18638 #define DSI_VVBPCR_VBP2_Pos (2U) 18639 #define DSI_VVBPCR_VBP2_Msk (0x1U << DSI_VVBPCR_VBP2_Pos) 18640 #define DSI_VVBPCR_VBP2 DSI_VVBPCR_VBP2_Msk 18641 #define DSI_VVBPCR_VBP3_Pos (3U) 18642 #define DSI_VVBPCR_VBP3_Msk (0x1U << DSI_VVBPCR_VBP3_Pos) 18643 #define DSI_VVBPCR_VBP3 DSI_VVBPCR_VBP3_Msk 18644 #define DSI_VVBPCR_VBP4_Pos (4U) 18645 #define DSI_VVBPCR_VBP4_Msk (0x1U << DSI_VVBPCR_VBP4_Pos) 18646 #define DSI_VVBPCR_VBP4 DSI_VVBPCR_VBP4_Msk 18647 #define DSI_VVBPCR_VBP5_Pos (5U) 18648 #define DSI_VVBPCR_VBP5_Msk (0x1U << DSI_VVBPCR_VBP5_Pos) 18649 #define DSI_VVBPCR_VBP5 DSI_VVBPCR_VBP5_Msk 18650 #define DSI_VVBPCR_VBP6_Pos (6U) 18651 #define DSI_VVBPCR_VBP6_Msk (0x1U << DSI_VVBPCR_VBP6_Pos) 18652 #define DSI_VVBPCR_VBP6 DSI_VVBPCR_VBP6_Msk 18653 #define DSI_VVBPCR_VBP7_Pos (7U) 18654 #define DSI_VVBPCR_VBP7_Msk (0x1U << DSI_VVBPCR_VBP7_Pos) 18655 #define DSI_VVBPCR_VBP7 DSI_VVBPCR_VBP7_Msk 18656 #define DSI_VVBPCR_VBP8_Pos (8U) 18657 #define DSI_VVBPCR_VBP8_Msk (0x1U << DSI_VVBPCR_VBP8_Pos) 18658 #define DSI_VVBPCR_VBP8 DSI_VVBPCR_VBP8_Msk 18659 #define DSI_VVBPCR_VBP9_Pos (9U) 18660 #define DSI_VVBPCR_VBP9_Msk (0x1U << DSI_VVBPCR_VBP9_Pos) 18661 #define DSI_VVBPCR_VBP9 DSI_VVBPCR_VBP9_Msk 18664 #define DSI_VVFPCR_VFP_Pos (0U) 18665 #define DSI_VVFPCR_VFP_Msk (0x3FFU << DSI_VVFPCR_VFP_Pos) 18666 #define DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk 18667 #define DSI_VVFPCR_VFP0_Pos (0U) 18668 #define DSI_VVFPCR_VFP0_Msk (0x1U << DSI_VVFPCR_VFP0_Pos) 18669 #define DSI_VVFPCR_VFP0 DSI_VVFPCR_VFP0_Msk 18670 #define DSI_VVFPCR_VFP1_Pos (1U) 18671 #define DSI_VVFPCR_VFP1_Msk (0x1U << DSI_VVFPCR_VFP1_Pos) 18672 #define DSI_VVFPCR_VFP1 DSI_VVFPCR_VFP1_Msk 18673 #define DSI_VVFPCR_VFP2_Pos (2U) 18674 #define DSI_VVFPCR_VFP2_Msk (0x1U << DSI_VVFPCR_VFP2_Pos) 18675 #define DSI_VVFPCR_VFP2 DSI_VVFPCR_VFP2_Msk 18676 #define DSI_VVFPCR_VFP3_Pos (3U) 18677 #define DSI_VVFPCR_VFP3_Msk (0x1U << DSI_VVFPCR_VFP3_Pos) 18678 #define DSI_VVFPCR_VFP3 DSI_VVFPCR_VFP3_Msk 18679 #define DSI_VVFPCR_VFP4_Pos (4U) 18680 #define DSI_VVFPCR_VFP4_Msk (0x1U << DSI_VVFPCR_VFP4_Pos) 18681 #define DSI_VVFPCR_VFP4 DSI_VVFPCR_VFP4_Msk 18682 #define DSI_VVFPCR_VFP5_Pos (5U) 18683 #define DSI_VVFPCR_VFP5_Msk (0x1U << DSI_VVFPCR_VFP5_Pos) 18684 #define DSI_VVFPCR_VFP5 DSI_VVFPCR_VFP5_Msk 18685 #define DSI_VVFPCR_VFP6_Pos (6U) 18686 #define DSI_VVFPCR_VFP6_Msk (0x1U << DSI_VVFPCR_VFP6_Pos) 18687 #define DSI_VVFPCR_VFP6 DSI_VVFPCR_VFP6_Msk 18688 #define DSI_VVFPCR_VFP7_Pos (7U) 18689 #define DSI_VVFPCR_VFP7_Msk (0x1U << DSI_VVFPCR_VFP7_Pos) 18690 #define DSI_VVFPCR_VFP7 DSI_VVFPCR_VFP7_Msk 18691 #define DSI_VVFPCR_VFP8_Pos (8U) 18692 #define DSI_VVFPCR_VFP8_Msk (0x1U << DSI_VVFPCR_VFP8_Pos) 18693 #define DSI_VVFPCR_VFP8 DSI_VVFPCR_VFP8_Msk 18694 #define DSI_VVFPCR_VFP9_Pos (9U) 18695 #define DSI_VVFPCR_VFP9_Msk (0x1U << DSI_VVFPCR_VFP9_Pos) 18696 #define DSI_VVFPCR_VFP9 DSI_VVFPCR_VFP9_Msk 18699 #define DSI_VVACR_VA_Pos (0U) 18700 #define DSI_VVACR_VA_Msk (0x3FFFU << DSI_VVACR_VA_Pos) 18701 #define DSI_VVACR_VA DSI_VVACR_VA_Msk 18702 #define DSI_VVACR_VA0_Pos (0U) 18703 #define DSI_VVACR_VA0_Msk (0x1U << DSI_VVACR_VA0_Pos) 18704 #define DSI_VVACR_VA0 DSI_VVACR_VA0_Msk 18705 #define DSI_VVACR_VA1_Pos (1U) 18706 #define DSI_VVACR_VA1_Msk (0x1U << DSI_VVACR_VA1_Pos) 18707 #define DSI_VVACR_VA1 DSI_VVACR_VA1_Msk 18708 #define DSI_VVACR_VA2_Pos (2U) 18709 #define DSI_VVACR_VA2_Msk (0x1U << DSI_VVACR_VA2_Pos) 18710 #define DSI_VVACR_VA2 DSI_VVACR_VA2_Msk 18711 #define DSI_VVACR_VA3_Pos (3U) 18712 #define DSI_VVACR_VA3_Msk (0x1U << DSI_VVACR_VA3_Pos) 18713 #define DSI_VVACR_VA3 DSI_VVACR_VA3_Msk 18714 #define DSI_VVACR_VA4_Pos (4U) 18715 #define DSI_VVACR_VA4_Msk (0x1U << DSI_VVACR_VA4_Pos) 18716 #define DSI_VVACR_VA4 DSI_VVACR_VA4_Msk 18717 #define DSI_VVACR_VA5_Pos (5U) 18718 #define DSI_VVACR_VA5_Msk (0x1U << DSI_VVACR_VA5_Pos) 18719 #define DSI_VVACR_VA5 DSI_VVACR_VA5_Msk 18720 #define DSI_VVACR_VA6_Pos (6U) 18721 #define DSI_VVACR_VA6_Msk (0x1U << DSI_VVACR_VA6_Pos) 18722 #define DSI_VVACR_VA6 DSI_VVACR_VA6_Msk 18723 #define DSI_VVACR_VA7_Pos (7U) 18724 #define DSI_VVACR_VA7_Msk (0x1U << DSI_VVACR_VA7_Pos) 18725 #define DSI_VVACR_VA7 DSI_VVACR_VA7_Msk 18726 #define DSI_VVACR_VA8_Pos (8U) 18727 #define DSI_VVACR_VA8_Msk (0x1U << DSI_VVACR_VA8_Pos) 18728 #define DSI_VVACR_VA8 DSI_VVACR_VA8_Msk 18729 #define DSI_VVACR_VA9_Pos (9U) 18730 #define DSI_VVACR_VA9_Msk (0x1U << DSI_VVACR_VA9_Pos) 18731 #define DSI_VVACR_VA9 DSI_VVACR_VA9_Msk 18732 #define DSI_VVACR_VA10_Pos (10U) 18733 #define DSI_VVACR_VA10_Msk (0x1U << DSI_VVACR_VA10_Pos) 18734 #define DSI_VVACR_VA10 DSI_VVACR_VA10_Msk 18735 #define DSI_VVACR_VA11_Pos (11U) 18736 #define DSI_VVACR_VA11_Msk (0x1U << DSI_VVACR_VA11_Pos) 18737 #define DSI_VVACR_VA11 DSI_VVACR_VA11_Msk 18738 #define DSI_VVACR_VA12_Pos (12U) 18739 #define DSI_VVACR_VA12_Msk (0x1U << DSI_VVACR_VA12_Pos) 18740 #define DSI_VVACR_VA12 DSI_VVACR_VA12_Msk 18741 #define DSI_VVACR_VA13_Pos (13U) 18742 #define DSI_VVACR_VA13_Msk (0x1U << DSI_VVACR_VA13_Pos) 18743 #define DSI_VVACR_VA13 DSI_VVACR_VA13_Msk 18746 #define DSI_LCCR_CMDSIZE_Pos (0U) 18747 #define DSI_LCCR_CMDSIZE_Msk (0xFFFFU << DSI_LCCR_CMDSIZE_Pos) 18748 #define DSI_LCCR_CMDSIZE DSI_LCCR_CMDSIZE_Msk 18749 #define DSI_LCCR_CMDSIZE0_Pos (0U) 18750 #define DSI_LCCR_CMDSIZE0_Msk (0x1U << DSI_LCCR_CMDSIZE0_Pos) 18751 #define DSI_LCCR_CMDSIZE0 DSI_LCCR_CMDSIZE0_Msk 18752 #define DSI_LCCR_CMDSIZE1_Pos (1U) 18753 #define DSI_LCCR_CMDSIZE1_Msk (0x1U << DSI_LCCR_CMDSIZE1_Pos) 18754 #define DSI_LCCR_CMDSIZE1 DSI_LCCR_CMDSIZE1_Msk 18755 #define DSI_LCCR_CMDSIZE2_Pos (2U) 18756 #define DSI_LCCR_CMDSIZE2_Msk (0x1U << DSI_LCCR_CMDSIZE2_Pos) 18757 #define DSI_LCCR_CMDSIZE2 DSI_LCCR_CMDSIZE2_Msk 18758 #define DSI_LCCR_CMDSIZE3_Pos (3U) 18759 #define DSI_LCCR_CMDSIZE3_Msk (0x1U << DSI_LCCR_CMDSIZE3_Pos) 18760 #define DSI_LCCR_CMDSIZE3 DSI_LCCR_CMDSIZE3_Msk 18761 #define DSI_LCCR_CMDSIZE4_Pos (4U) 18762 #define DSI_LCCR_CMDSIZE4_Msk (0x1U << DSI_LCCR_CMDSIZE4_Pos) 18763 #define DSI_LCCR_CMDSIZE4 DSI_LCCR_CMDSIZE4_Msk 18764 #define DSI_LCCR_CMDSIZE5_Pos (5U) 18765 #define DSI_LCCR_CMDSIZE5_Msk (0x1U << DSI_LCCR_CMDSIZE5_Pos) 18766 #define DSI_LCCR_CMDSIZE5 DSI_LCCR_CMDSIZE5_Msk 18767 #define DSI_LCCR_CMDSIZE6_Pos (6U) 18768 #define DSI_LCCR_CMDSIZE6_Msk (0x1U << DSI_LCCR_CMDSIZE6_Pos) 18769 #define DSI_LCCR_CMDSIZE6 DSI_LCCR_CMDSIZE6_Msk 18770 #define DSI_LCCR_CMDSIZE7_Pos (7U) 18771 #define DSI_LCCR_CMDSIZE7_Msk (0x1U << DSI_LCCR_CMDSIZE7_Pos) 18772 #define DSI_LCCR_CMDSIZE7 DSI_LCCR_CMDSIZE7_Msk 18773 #define DSI_LCCR_CMDSIZE8_Pos (8U) 18774 #define DSI_LCCR_CMDSIZE8_Msk (0x1U << DSI_LCCR_CMDSIZE8_Pos) 18775 #define DSI_LCCR_CMDSIZE8 DSI_LCCR_CMDSIZE8_Msk 18776 #define DSI_LCCR_CMDSIZE9_Pos (9U) 18777 #define DSI_LCCR_CMDSIZE9_Msk (0x1U << DSI_LCCR_CMDSIZE9_Pos) 18778 #define DSI_LCCR_CMDSIZE9 DSI_LCCR_CMDSIZE9_Msk 18779 #define DSI_LCCR_CMDSIZE10_Pos (10U) 18780 #define DSI_LCCR_CMDSIZE10_Msk (0x1U << DSI_LCCR_CMDSIZE10_Pos) 18781 #define DSI_LCCR_CMDSIZE10 DSI_LCCR_CMDSIZE10_Msk 18782 #define DSI_LCCR_CMDSIZE11_Pos (11U) 18783 #define DSI_LCCR_CMDSIZE11_Msk (0x1U << DSI_LCCR_CMDSIZE11_Pos) 18784 #define DSI_LCCR_CMDSIZE11 DSI_LCCR_CMDSIZE11_Msk 18785 #define DSI_LCCR_CMDSIZE12_Pos (12U) 18786 #define DSI_LCCR_CMDSIZE12_Msk (0x1U << DSI_LCCR_CMDSIZE12_Pos) 18787 #define DSI_LCCR_CMDSIZE12 DSI_LCCR_CMDSIZE12_Msk 18788 #define DSI_LCCR_CMDSIZE13_Pos (13U) 18789 #define DSI_LCCR_CMDSIZE13_Msk (0x1U << DSI_LCCR_CMDSIZE13_Pos) 18790 #define DSI_LCCR_CMDSIZE13 DSI_LCCR_CMDSIZE13_Msk 18791 #define DSI_LCCR_CMDSIZE14_Pos (14U) 18792 #define DSI_LCCR_CMDSIZE14_Msk (0x1U << DSI_LCCR_CMDSIZE14_Pos) 18793 #define DSI_LCCR_CMDSIZE14 DSI_LCCR_CMDSIZE14_Msk 18794 #define DSI_LCCR_CMDSIZE15_Pos (15U) 18795 #define DSI_LCCR_CMDSIZE15_Msk (0x1U << DSI_LCCR_CMDSIZE15_Pos) 18796 #define DSI_LCCR_CMDSIZE15 DSI_LCCR_CMDSIZE15_Msk 18799 #define DSI_CMCR_TEARE_Pos (0U) 18800 #define DSI_CMCR_TEARE_Msk (0x1U << DSI_CMCR_TEARE_Pos) 18801 #define DSI_CMCR_TEARE DSI_CMCR_TEARE_Msk 18802 #define DSI_CMCR_ARE_Pos (1U) 18803 #define DSI_CMCR_ARE_Msk (0x1U << DSI_CMCR_ARE_Pos) 18804 #define DSI_CMCR_ARE DSI_CMCR_ARE_Msk 18805 #define DSI_CMCR_GSW0TX_Pos (8U) 18806 #define DSI_CMCR_GSW0TX_Msk (0x1U << DSI_CMCR_GSW0TX_Pos) 18807 #define DSI_CMCR_GSW0TX DSI_CMCR_GSW0TX_Msk 18808 #define DSI_CMCR_GSW1TX_Pos (9U) 18809 #define DSI_CMCR_GSW1TX_Msk (0x1U << DSI_CMCR_GSW1TX_Pos) 18810 #define DSI_CMCR_GSW1TX DSI_CMCR_GSW1TX_Msk 18811 #define DSI_CMCR_GSW2TX_Pos (10U) 18812 #define DSI_CMCR_GSW2TX_Msk (0x1U << DSI_CMCR_GSW2TX_Pos) 18813 #define DSI_CMCR_GSW2TX DSI_CMCR_GSW2TX_Msk 18814 #define DSI_CMCR_GSR0TX_Pos (11U) 18815 #define DSI_CMCR_GSR0TX_Msk (0x1U << DSI_CMCR_GSR0TX_Pos) 18816 #define DSI_CMCR_GSR0TX DSI_CMCR_GSR0TX_Msk 18817 #define DSI_CMCR_GSR1TX_Pos (12U) 18818 #define DSI_CMCR_GSR1TX_Msk (0x1U << DSI_CMCR_GSR1TX_Pos) 18819 #define DSI_CMCR_GSR1TX DSI_CMCR_GSR1TX_Msk 18820 #define DSI_CMCR_GSR2TX_Pos (13U) 18821 #define DSI_CMCR_GSR2TX_Msk (0x1U << DSI_CMCR_GSR2TX_Pos) 18822 #define DSI_CMCR_GSR2TX DSI_CMCR_GSR2TX_Msk 18823 #define DSI_CMCR_GLWTX_Pos (14U) 18824 #define DSI_CMCR_GLWTX_Msk (0x1U << DSI_CMCR_GLWTX_Pos) 18825 #define DSI_CMCR_GLWTX DSI_CMCR_GLWTX_Msk 18826 #define DSI_CMCR_DSW0TX_Pos (16U) 18827 #define DSI_CMCR_DSW0TX_Msk (0x1U << DSI_CMCR_DSW0TX_Pos) 18828 #define DSI_CMCR_DSW0TX DSI_CMCR_DSW0TX_Msk 18829 #define DSI_CMCR_DSW1TX_Pos (17U) 18830 #define DSI_CMCR_DSW1TX_Msk (0x1U << DSI_CMCR_DSW1TX_Pos) 18831 #define DSI_CMCR_DSW1TX DSI_CMCR_DSW1TX_Msk 18832 #define DSI_CMCR_DSR0TX_Pos (18U) 18833 #define DSI_CMCR_DSR0TX_Msk (0x1U << DSI_CMCR_DSR0TX_Pos) 18834 #define DSI_CMCR_DSR0TX DSI_CMCR_DSR0TX_Msk 18835 #define DSI_CMCR_DLWTX_Pos (19U) 18836 #define DSI_CMCR_DLWTX_Msk (0x1U << DSI_CMCR_DLWTX_Pos) 18837 #define DSI_CMCR_DLWTX DSI_CMCR_DLWTX_Msk 18838 #define DSI_CMCR_MRDPS_Pos (24U) 18839 #define DSI_CMCR_MRDPS_Msk (0x1U << DSI_CMCR_MRDPS_Pos) 18840 #define DSI_CMCR_MRDPS DSI_CMCR_MRDPS_Msk 18843 #define DSI_GHCR_DT_Pos (0U) 18844 #define DSI_GHCR_DT_Msk (0x3FU << DSI_GHCR_DT_Pos) 18845 #define DSI_GHCR_DT DSI_GHCR_DT_Msk 18846 #define DSI_GHCR_DT0_Pos (0U) 18847 #define DSI_GHCR_DT0_Msk (0x1U << DSI_GHCR_DT0_Pos) 18848 #define DSI_GHCR_DT0 DSI_GHCR_DT0_Msk 18849 #define DSI_GHCR_DT1_Pos (1U) 18850 #define DSI_GHCR_DT1_Msk (0x1U << DSI_GHCR_DT1_Pos) 18851 #define DSI_GHCR_DT1 DSI_GHCR_DT1_Msk 18852 #define DSI_GHCR_DT2_Pos (2U) 18853 #define DSI_GHCR_DT2_Msk (0x1U << DSI_GHCR_DT2_Pos) 18854 #define DSI_GHCR_DT2 DSI_GHCR_DT2_Msk 18855 #define DSI_GHCR_DT3_Pos (3U) 18856 #define DSI_GHCR_DT3_Msk (0x1U << DSI_GHCR_DT3_Pos) 18857 #define DSI_GHCR_DT3 DSI_GHCR_DT3_Msk 18858 #define DSI_GHCR_DT4_Pos (4U) 18859 #define DSI_GHCR_DT4_Msk (0x1U << DSI_GHCR_DT4_Pos) 18860 #define DSI_GHCR_DT4 DSI_GHCR_DT4_Msk 18861 #define DSI_GHCR_DT5_Pos (5U) 18862 #define DSI_GHCR_DT5_Msk (0x1U << DSI_GHCR_DT5_Pos) 18863 #define DSI_GHCR_DT5 DSI_GHCR_DT5_Msk 18865 #define DSI_GHCR_VCID_Pos (6U) 18866 #define DSI_GHCR_VCID_Msk (0x3U << DSI_GHCR_VCID_Pos) 18867 #define DSI_GHCR_VCID DSI_GHCR_VCID_Msk 18868 #define DSI_GHCR_VCID0_Pos (6U) 18869 #define DSI_GHCR_VCID0_Msk (0x1U << DSI_GHCR_VCID0_Pos) 18870 #define DSI_GHCR_VCID0 DSI_GHCR_VCID0_Msk 18871 #define DSI_GHCR_VCID1_Pos (7U) 18872 #define DSI_GHCR_VCID1_Msk (0x1U << DSI_GHCR_VCID1_Pos) 18873 #define DSI_GHCR_VCID1 DSI_GHCR_VCID1_Msk 18875 #define DSI_GHCR_WCLSB_Pos (8U) 18876 #define DSI_GHCR_WCLSB_Msk (0xFFU << DSI_GHCR_WCLSB_Pos) 18877 #define DSI_GHCR_WCLSB DSI_GHCR_WCLSB_Msk 18878 #define DSI_GHCR_WCLSB0_Pos (8U) 18879 #define DSI_GHCR_WCLSB0_Msk (0x1U << DSI_GHCR_WCLSB0_Pos) 18880 #define DSI_GHCR_WCLSB0 DSI_GHCR_WCLSB0_Msk 18881 #define DSI_GHCR_WCLSB1_Pos (9U) 18882 #define DSI_GHCR_WCLSB1_Msk (0x1U << DSI_GHCR_WCLSB1_Pos) 18883 #define DSI_GHCR_WCLSB1 DSI_GHCR_WCLSB1_Msk 18884 #define DSI_GHCR_WCLSB2_Pos (10U) 18885 #define DSI_GHCR_WCLSB2_Msk (0x1U << DSI_GHCR_WCLSB2_Pos) 18886 #define DSI_GHCR_WCLSB2 DSI_GHCR_WCLSB2_Msk 18887 #define DSI_GHCR_WCLSB3_Pos (11U) 18888 #define DSI_GHCR_WCLSB3_Msk (0x1U << DSI_GHCR_WCLSB3_Pos) 18889 #define DSI_GHCR_WCLSB3 DSI_GHCR_WCLSB3_Msk 18890 #define DSI_GHCR_WCLSB4_Pos (12U) 18891 #define DSI_GHCR_WCLSB4_Msk (0x1U << DSI_GHCR_WCLSB4_Pos) 18892 #define DSI_GHCR_WCLSB4 DSI_GHCR_WCLSB4_Msk 18893 #define DSI_GHCR_WCLSB5_Pos (13U) 18894 #define DSI_GHCR_WCLSB5_Msk (0x1U << DSI_GHCR_WCLSB5_Pos) 18895 #define DSI_GHCR_WCLSB5 DSI_GHCR_WCLSB5_Msk 18896 #define DSI_GHCR_WCLSB6_Pos (14U) 18897 #define DSI_GHCR_WCLSB6_Msk (0x1U << DSI_GHCR_WCLSB6_Pos) 18898 #define DSI_GHCR_WCLSB6 DSI_GHCR_WCLSB6_Msk 18899 #define DSI_GHCR_WCLSB7_Pos (15U) 18900 #define DSI_GHCR_WCLSB7_Msk (0x1U << DSI_GHCR_WCLSB7_Pos) 18901 #define DSI_GHCR_WCLSB7 DSI_GHCR_WCLSB7_Msk 18903 #define DSI_GHCR_WCMSB_Pos (16U) 18904 #define DSI_GHCR_WCMSB_Msk (0xFFU << DSI_GHCR_WCMSB_Pos) 18905 #define DSI_GHCR_WCMSB DSI_GHCR_WCMSB_Msk 18906 #define DSI_GHCR_WCMSB0_Pos (16U) 18907 #define DSI_GHCR_WCMSB0_Msk (0x1U << DSI_GHCR_WCMSB0_Pos) 18908 #define DSI_GHCR_WCMSB0 DSI_GHCR_WCMSB0_Msk 18909 #define DSI_GHCR_WCMSB1_Pos (17U) 18910 #define DSI_GHCR_WCMSB1_Msk (0x1U << DSI_GHCR_WCMSB1_Pos) 18911 #define DSI_GHCR_WCMSB1 DSI_GHCR_WCMSB1_Msk 18912 #define DSI_GHCR_WCMSB2_Pos (18U) 18913 #define DSI_GHCR_WCMSB2_Msk (0x1U << DSI_GHCR_WCMSB2_Pos) 18914 #define DSI_GHCR_WCMSB2 DSI_GHCR_WCMSB2_Msk 18915 #define DSI_GHCR_WCMSB3_Pos (19U) 18916 #define DSI_GHCR_WCMSB3_Msk (0x1U << DSI_GHCR_WCMSB3_Pos) 18917 #define DSI_GHCR_WCMSB3 DSI_GHCR_WCMSB3_Msk 18918 #define DSI_GHCR_WCMSB4_Pos (20U) 18919 #define DSI_GHCR_WCMSB4_Msk (0x1U << DSI_GHCR_WCMSB4_Pos) 18920 #define DSI_GHCR_WCMSB4 DSI_GHCR_WCMSB4_Msk 18921 #define DSI_GHCR_WCMSB5_Pos (21U) 18922 #define DSI_GHCR_WCMSB5_Msk (0x1U << DSI_GHCR_WCMSB5_Pos) 18923 #define DSI_GHCR_WCMSB5 DSI_GHCR_WCMSB5_Msk 18924 #define DSI_GHCR_WCMSB6_Pos (22U) 18925 #define DSI_GHCR_WCMSB6_Msk (0x1U << DSI_GHCR_WCMSB6_Pos) 18926 #define DSI_GHCR_WCMSB6 DSI_GHCR_WCMSB6_Msk 18927 #define DSI_GHCR_WCMSB7_Pos (23U) 18928 #define DSI_GHCR_WCMSB7_Msk (0x1U << DSI_GHCR_WCMSB7_Pos) 18929 #define DSI_GHCR_WCMSB7 DSI_GHCR_WCMSB7_Msk 18932 #define DSI_GPDR_DATA1_Pos (0U) 18933 #define DSI_GPDR_DATA1_Msk (0xFFU << DSI_GPDR_DATA1_Pos) 18934 #define DSI_GPDR_DATA1 DSI_GPDR_DATA1_Msk 18935 #define DSI_GPDR_DATA1_0 (0x01U << DSI_GPDR_DATA1_Pos) 18936 #define DSI_GPDR_DATA1_1 (0x02U << DSI_GPDR_DATA1_Pos) 18937 #define DSI_GPDR_DATA1_2 (0x04U << DSI_GPDR_DATA1_Pos) 18938 #define DSI_GPDR_DATA1_3 (0x08U << DSI_GPDR_DATA1_Pos) 18939 #define DSI_GPDR_DATA1_4 (0x10U << DSI_GPDR_DATA1_Pos) 18940 #define DSI_GPDR_DATA1_5 (0x20U << DSI_GPDR_DATA1_Pos) 18941 #define DSI_GPDR_DATA1_6 (0x40U << DSI_GPDR_DATA1_Pos) 18942 #define DSI_GPDR_DATA1_7 (0x80U << DSI_GPDR_DATA1_Pos) 18944 #define DSI_GPDR_DATA2_Pos (8U) 18945 #define DSI_GPDR_DATA2_Msk (0xFFU << DSI_GPDR_DATA2_Pos) 18946 #define DSI_GPDR_DATA2 DSI_GPDR_DATA2_Msk 18947 #define DSI_GPDR_DATA2_0 (0x01U << DSI_GPDR_DATA2_Pos) 18948 #define DSI_GPDR_DATA2_1 (0x02U << DSI_GPDR_DATA2_Pos) 18949 #define DSI_GPDR_DATA2_2 (0x04U << DSI_GPDR_DATA2_Pos) 18950 #define DSI_GPDR_DATA2_3 (0x08U << DSI_GPDR_DATA2_Pos) 18951 #define DSI_GPDR_DATA2_4 (0x10U << DSI_GPDR_DATA2_Pos) 18952 #define DSI_GPDR_DATA2_5 (0x20U << DSI_GPDR_DATA2_Pos) 18953 #define DSI_GPDR_DATA2_6 (0x40U << DSI_GPDR_DATA2_Pos) 18954 #define DSI_GPDR_DATA2_7 (0x80U << DSI_GPDR_DATA2_Pos) 18956 #define DSI_GPDR_DATA3_Pos (16U) 18957 #define DSI_GPDR_DATA3_Msk (0xFFU << DSI_GPDR_DATA3_Pos) 18958 #define DSI_GPDR_DATA3 DSI_GPDR_DATA3_Msk 18959 #define DSI_GPDR_DATA3_0 (0x01U << DSI_GPDR_DATA3_Pos) 18960 #define DSI_GPDR_DATA3_1 (0x02U << DSI_GPDR_DATA3_Pos) 18961 #define DSI_GPDR_DATA3_2 (0x04U << DSI_GPDR_DATA3_Pos) 18962 #define DSI_GPDR_DATA3_3 (0x08U << DSI_GPDR_DATA3_Pos) 18963 #define DSI_GPDR_DATA3_4 (0x10U << DSI_GPDR_DATA3_Pos) 18964 #define DSI_GPDR_DATA3_5 (0x20U << DSI_GPDR_DATA3_Pos) 18965 #define DSI_GPDR_DATA3_6 (0x40U << DSI_GPDR_DATA3_Pos) 18966 #define DSI_GPDR_DATA3_7 (0x80U << DSI_GPDR_DATA3_Pos) 18968 #define DSI_GPDR_DATA4_Pos (24U) 18969 #define DSI_GPDR_DATA4_Msk (0xFFU << DSI_GPDR_DATA4_Pos) 18970 #define DSI_GPDR_DATA4 DSI_GPDR_DATA4_Msk 18971 #define DSI_GPDR_DATA4_0 (0x01U << DSI_GPDR_DATA4_Pos) 18972 #define DSI_GPDR_DATA4_1 (0x02U << DSI_GPDR_DATA4_Pos) 18973 #define DSI_GPDR_DATA4_2 (0x04U << DSI_GPDR_DATA4_Pos) 18974 #define DSI_GPDR_DATA4_3 (0x08U << DSI_GPDR_DATA4_Pos) 18975 #define DSI_GPDR_DATA4_4 (0x10U << DSI_GPDR_DATA4_Pos) 18976 #define DSI_GPDR_DATA4_5 (0x20U << DSI_GPDR_DATA4_Pos) 18977 #define DSI_GPDR_DATA4_6 (0x40U << DSI_GPDR_DATA4_Pos) 18978 #define DSI_GPDR_DATA4_7 (0x80U << DSI_GPDR_DATA4_Pos) 18981 #define DSI_GPSR_CMDFE_Pos (0U) 18982 #define DSI_GPSR_CMDFE_Msk (0x1U << DSI_GPSR_CMDFE_Pos) 18983 #define DSI_GPSR_CMDFE DSI_GPSR_CMDFE_Msk 18984 #define DSI_GPSR_CMDFF_Pos (1U) 18985 #define DSI_GPSR_CMDFF_Msk (0x1U << DSI_GPSR_CMDFF_Pos) 18986 #define DSI_GPSR_CMDFF DSI_GPSR_CMDFF_Msk 18987 #define DSI_GPSR_PWRFE_Pos (2U) 18988 #define DSI_GPSR_PWRFE_Msk (0x1U << DSI_GPSR_PWRFE_Pos) 18989 #define DSI_GPSR_PWRFE DSI_GPSR_PWRFE_Msk 18990 #define DSI_GPSR_PWRFF_Pos (3U) 18991 #define DSI_GPSR_PWRFF_Msk (0x1U << DSI_GPSR_PWRFF_Pos) 18992 #define DSI_GPSR_PWRFF DSI_GPSR_PWRFF_Msk 18993 #define DSI_GPSR_PRDFE_Pos (4U) 18994 #define DSI_GPSR_PRDFE_Msk (0x1U << DSI_GPSR_PRDFE_Pos) 18995 #define DSI_GPSR_PRDFE DSI_GPSR_PRDFE_Msk 18996 #define DSI_GPSR_PRDFF_Pos (5U) 18997 #define DSI_GPSR_PRDFF_Msk (0x1U << DSI_GPSR_PRDFF_Pos) 18998 #define DSI_GPSR_PRDFF DSI_GPSR_PRDFF_Msk 18999 #define DSI_GPSR_RCB_Pos (6U) 19000 #define DSI_GPSR_RCB_Msk (0x1U << DSI_GPSR_RCB_Pos) 19001 #define DSI_GPSR_RCB DSI_GPSR_RCB_Msk 19004 #define DSI_TCCR0_LPRX_TOCNT_Pos (0U) 19005 #define DSI_TCCR0_LPRX_TOCNT_Msk (0xFFFFU << DSI_TCCR0_LPRX_TOCNT_Pos) 19006 #define DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk 19007 #define DSI_TCCR0_LPRX_TOCNT0_Pos (0U) 19008 #define DSI_TCCR0_LPRX_TOCNT0_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT0_Pos) 19009 #define DSI_TCCR0_LPRX_TOCNT0 DSI_TCCR0_LPRX_TOCNT0_Msk 19010 #define DSI_TCCR0_LPRX_TOCNT1_Pos (1U) 19011 #define DSI_TCCR0_LPRX_TOCNT1_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT1_Pos) 19012 #define DSI_TCCR0_LPRX_TOCNT1 DSI_TCCR0_LPRX_TOCNT1_Msk 19013 #define DSI_TCCR0_LPRX_TOCNT2_Pos (2U) 19014 #define DSI_TCCR0_LPRX_TOCNT2_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT2_Pos) 19015 #define DSI_TCCR0_LPRX_TOCNT2 DSI_TCCR0_LPRX_TOCNT2_Msk 19016 #define DSI_TCCR0_LPRX_TOCNT3_Pos (3U) 19017 #define DSI_TCCR0_LPRX_TOCNT3_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT3_Pos) 19018 #define DSI_TCCR0_LPRX_TOCNT3 DSI_TCCR0_LPRX_TOCNT3_Msk 19019 #define DSI_TCCR0_LPRX_TOCNT4_Pos (4U) 19020 #define DSI_TCCR0_LPRX_TOCNT4_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT4_Pos) 19021 #define DSI_TCCR0_LPRX_TOCNT4 DSI_TCCR0_LPRX_TOCNT4_Msk 19022 #define DSI_TCCR0_LPRX_TOCNT5_Pos (5U) 19023 #define DSI_TCCR0_LPRX_TOCNT5_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT5_Pos) 19024 #define DSI_TCCR0_LPRX_TOCNT5 DSI_TCCR0_LPRX_TOCNT5_Msk 19025 #define DSI_TCCR0_LPRX_TOCNT6_Pos (6U) 19026 #define DSI_TCCR0_LPRX_TOCNT6_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT6_Pos) 19027 #define DSI_TCCR0_LPRX_TOCNT6 DSI_TCCR0_LPRX_TOCNT6_Msk 19028 #define DSI_TCCR0_LPRX_TOCNT7_Pos (7U) 19029 #define DSI_TCCR0_LPRX_TOCNT7_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT7_Pos) 19030 #define DSI_TCCR0_LPRX_TOCNT7 DSI_TCCR0_LPRX_TOCNT7_Msk 19031 #define DSI_TCCR0_LPRX_TOCNT8_Pos (8U) 19032 #define DSI_TCCR0_LPRX_TOCNT8_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT8_Pos) 19033 #define DSI_TCCR0_LPRX_TOCNT8 DSI_TCCR0_LPRX_TOCNT8_Msk 19034 #define DSI_TCCR0_LPRX_TOCNT9_Pos (9U) 19035 #define DSI_TCCR0_LPRX_TOCNT9_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT9_Pos) 19036 #define DSI_TCCR0_LPRX_TOCNT9 DSI_TCCR0_LPRX_TOCNT9_Msk 19037 #define DSI_TCCR0_LPRX_TOCNT10_Pos (10U) 19038 #define DSI_TCCR0_LPRX_TOCNT10_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT10_Pos) 19039 #define DSI_TCCR0_LPRX_TOCNT10 DSI_TCCR0_LPRX_TOCNT10_Msk 19040 #define DSI_TCCR0_LPRX_TOCNT11_Pos (11U) 19041 #define DSI_TCCR0_LPRX_TOCNT11_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT11_Pos) 19042 #define DSI_TCCR0_LPRX_TOCNT11 DSI_TCCR0_LPRX_TOCNT11_Msk 19043 #define DSI_TCCR0_LPRX_TOCNT12_Pos (12U) 19044 #define DSI_TCCR0_LPRX_TOCNT12_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT12_Pos) 19045 #define DSI_TCCR0_LPRX_TOCNT12 DSI_TCCR0_LPRX_TOCNT12_Msk 19046 #define DSI_TCCR0_LPRX_TOCNT13_Pos (13U) 19047 #define DSI_TCCR0_LPRX_TOCNT13_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT13_Pos) 19048 #define DSI_TCCR0_LPRX_TOCNT13 DSI_TCCR0_LPRX_TOCNT13_Msk 19049 #define DSI_TCCR0_LPRX_TOCNT14_Pos (14U) 19050 #define DSI_TCCR0_LPRX_TOCNT14_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT14_Pos) 19051 #define DSI_TCCR0_LPRX_TOCNT14 DSI_TCCR0_LPRX_TOCNT14_Msk 19052 #define DSI_TCCR0_LPRX_TOCNT15_Pos (15U) 19053 #define DSI_TCCR0_LPRX_TOCNT15_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT15_Pos) 19054 #define DSI_TCCR0_LPRX_TOCNT15 DSI_TCCR0_LPRX_TOCNT15_Msk 19056 #define DSI_TCCR0_HSTX_TOCNT_Pos (16U) 19057 #define DSI_TCCR0_HSTX_TOCNT_Msk (0xFFFFU << DSI_TCCR0_HSTX_TOCNT_Pos) 19058 #define DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk 19059 #define DSI_TCCR0_HSTX_TOCNT0_Pos (16U) 19060 #define DSI_TCCR0_HSTX_TOCNT0_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT0_Pos) 19061 #define DSI_TCCR0_HSTX_TOCNT0 DSI_TCCR0_HSTX_TOCNT0_Msk 19062 #define DSI_TCCR0_HSTX_TOCNT1_Pos (17U) 19063 #define DSI_TCCR0_HSTX_TOCNT1_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT1_Pos) 19064 #define DSI_TCCR0_HSTX_TOCNT1 DSI_TCCR0_HSTX_TOCNT1_Msk 19065 #define DSI_TCCR0_HSTX_TOCNT2_Pos (18U) 19066 #define DSI_TCCR0_HSTX_TOCNT2_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT2_Pos) 19067 #define DSI_TCCR0_HSTX_TOCNT2 DSI_TCCR0_HSTX_TOCNT2_Msk 19068 #define DSI_TCCR0_HSTX_TOCNT3_Pos (19U) 19069 #define DSI_TCCR0_HSTX_TOCNT3_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT3_Pos) 19070 #define DSI_TCCR0_HSTX_TOCNT3 DSI_TCCR0_HSTX_TOCNT3_Msk 19071 #define DSI_TCCR0_HSTX_TOCNT4_Pos (20U) 19072 #define DSI_TCCR0_HSTX_TOCNT4_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT4_Pos) 19073 #define DSI_TCCR0_HSTX_TOCNT4 DSI_TCCR0_HSTX_TOCNT4_Msk 19074 #define DSI_TCCR0_HSTX_TOCNT5_Pos (21U) 19075 #define DSI_TCCR0_HSTX_TOCNT5_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT5_Pos) 19076 #define DSI_TCCR0_HSTX_TOCNT5 DSI_TCCR0_HSTX_TOCNT5_Msk 19077 #define DSI_TCCR0_HSTX_TOCNT6_Pos (22U) 19078 #define DSI_TCCR0_HSTX_TOCNT6_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT6_Pos) 19079 #define DSI_TCCR0_HSTX_TOCNT6 DSI_TCCR0_HSTX_TOCNT6_Msk 19080 #define DSI_TCCR0_HSTX_TOCNT7_Pos (23U) 19081 #define DSI_TCCR0_HSTX_TOCNT7_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT7_Pos) 19082 #define DSI_TCCR0_HSTX_TOCNT7 DSI_TCCR0_HSTX_TOCNT7_Msk 19083 #define DSI_TCCR0_HSTX_TOCNT8_Pos (24U) 19084 #define DSI_TCCR0_HSTX_TOCNT8_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT8_Pos) 19085 #define DSI_TCCR0_HSTX_TOCNT8 DSI_TCCR0_HSTX_TOCNT8_Msk 19086 #define DSI_TCCR0_HSTX_TOCNT9_Pos (25U) 19087 #define DSI_TCCR0_HSTX_TOCNT9_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT9_Pos) 19088 #define DSI_TCCR0_HSTX_TOCNT9 DSI_TCCR0_HSTX_TOCNT9_Msk 19089 #define DSI_TCCR0_HSTX_TOCNT10_Pos (26U) 19090 #define DSI_TCCR0_HSTX_TOCNT10_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT10_Pos) 19091 #define DSI_TCCR0_HSTX_TOCNT10 DSI_TCCR0_HSTX_TOCNT10_Msk 19092 #define DSI_TCCR0_HSTX_TOCNT11_Pos (27U) 19093 #define DSI_TCCR0_HSTX_TOCNT11_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT11_Pos) 19094 #define DSI_TCCR0_HSTX_TOCNT11 DSI_TCCR0_HSTX_TOCNT11_Msk 19095 #define DSI_TCCR0_HSTX_TOCNT12_Pos (28U) 19096 #define DSI_TCCR0_HSTX_TOCNT12_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT12_Pos) 19097 #define DSI_TCCR0_HSTX_TOCNT12 DSI_TCCR0_HSTX_TOCNT12_Msk 19098 #define DSI_TCCR0_HSTX_TOCNT13_Pos (29U) 19099 #define DSI_TCCR0_HSTX_TOCNT13_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT13_Pos) 19100 #define DSI_TCCR0_HSTX_TOCNT13 DSI_TCCR0_HSTX_TOCNT13_Msk 19101 #define DSI_TCCR0_HSTX_TOCNT14_Pos (30U) 19102 #define DSI_TCCR0_HSTX_TOCNT14_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT14_Pos) 19103 #define DSI_TCCR0_HSTX_TOCNT14 DSI_TCCR0_HSTX_TOCNT14_Msk 19104 #define DSI_TCCR0_HSTX_TOCNT15_Pos (31U) 19105 #define DSI_TCCR0_HSTX_TOCNT15_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT15_Pos) 19106 #define DSI_TCCR0_HSTX_TOCNT15 DSI_TCCR0_HSTX_TOCNT15_Msk 19109 #define DSI_TCCR1_HSRD_TOCNT_Pos (0U) 19110 #define DSI_TCCR1_HSRD_TOCNT_Msk (0xFFFFU << DSI_TCCR1_HSRD_TOCNT_Pos) 19111 #define DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk 19112 #define DSI_TCCR1_HSRD_TOCNT0_Pos (0U) 19113 #define DSI_TCCR1_HSRD_TOCNT0_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT0_Pos) 19114 #define DSI_TCCR1_HSRD_TOCNT0 DSI_TCCR1_HSRD_TOCNT0_Msk 19115 #define DSI_TCCR1_HSRD_TOCNT1_Pos (1U) 19116 #define DSI_TCCR1_HSRD_TOCNT1_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT1_Pos) 19117 #define DSI_TCCR1_HSRD_TOCNT1 DSI_TCCR1_HSRD_TOCNT1_Msk 19118 #define DSI_TCCR1_HSRD_TOCNT2_Pos (2U) 19119 #define DSI_TCCR1_HSRD_TOCNT2_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT2_Pos) 19120 #define DSI_TCCR1_HSRD_TOCNT2 DSI_TCCR1_HSRD_TOCNT2_Msk 19121 #define DSI_TCCR1_HSRD_TOCNT3_Pos (3U) 19122 #define DSI_TCCR1_HSRD_TOCNT3_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT3_Pos) 19123 #define DSI_TCCR1_HSRD_TOCNT3 DSI_TCCR1_HSRD_TOCNT3_Msk 19124 #define DSI_TCCR1_HSRD_TOCNT4_Pos (4U) 19125 #define DSI_TCCR1_HSRD_TOCNT4_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT4_Pos) 19126 #define DSI_TCCR1_HSRD_TOCNT4 DSI_TCCR1_HSRD_TOCNT4_Msk 19127 #define DSI_TCCR1_HSRD_TOCNT5_Pos (5U) 19128 #define DSI_TCCR1_HSRD_TOCNT5_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT5_Pos) 19129 #define DSI_TCCR1_HSRD_TOCNT5 DSI_TCCR1_HSRD_TOCNT5_Msk 19130 #define DSI_TCCR1_HSRD_TOCNT6_Pos (6U) 19131 #define DSI_TCCR1_HSRD_TOCNT6_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT6_Pos) 19132 #define DSI_TCCR1_HSRD_TOCNT6 DSI_TCCR1_HSRD_TOCNT6_Msk 19133 #define DSI_TCCR1_HSRD_TOCNT7_Pos (7U) 19134 #define DSI_TCCR1_HSRD_TOCNT7_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT7_Pos) 19135 #define DSI_TCCR1_HSRD_TOCNT7 DSI_TCCR1_HSRD_TOCNT7_Msk 19136 #define DSI_TCCR1_HSRD_TOCNT8_Pos (8U) 19137 #define DSI_TCCR1_HSRD_TOCNT8_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT8_Pos) 19138 #define DSI_TCCR1_HSRD_TOCNT8 DSI_TCCR1_HSRD_TOCNT8_Msk 19139 #define DSI_TCCR1_HSRD_TOCNT9_Pos (9U) 19140 #define DSI_TCCR1_HSRD_TOCNT9_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT9_Pos) 19141 #define DSI_TCCR1_HSRD_TOCNT9 DSI_TCCR1_HSRD_TOCNT9_Msk 19142 #define DSI_TCCR1_HSRD_TOCNT10_Pos (10U) 19143 #define DSI_TCCR1_HSRD_TOCNT10_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT10_Pos) 19144 #define DSI_TCCR1_HSRD_TOCNT10 DSI_TCCR1_HSRD_TOCNT10_Msk 19145 #define DSI_TCCR1_HSRD_TOCNT11_Pos (11U) 19146 #define DSI_TCCR1_HSRD_TOCNT11_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT11_Pos) 19147 #define DSI_TCCR1_HSRD_TOCNT11 DSI_TCCR1_HSRD_TOCNT11_Msk 19148 #define DSI_TCCR1_HSRD_TOCNT12_Pos (12U) 19149 #define DSI_TCCR1_HSRD_TOCNT12_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT12_Pos) 19150 #define DSI_TCCR1_HSRD_TOCNT12 DSI_TCCR1_HSRD_TOCNT12_Msk 19151 #define DSI_TCCR1_HSRD_TOCNT13_Pos (13U) 19152 #define DSI_TCCR1_HSRD_TOCNT13_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT13_Pos) 19153 #define DSI_TCCR1_HSRD_TOCNT13 DSI_TCCR1_HSRD_TOCNT13_Msk 19154 #define DSI_TCCR1_HSRD_TOCNT14_Pos (14U) 19155 #define DSI_TCCR1_HSRD_TOCNT14_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT14_Pos) 19156 #define DSI_TCCR1_HSRD_TOCNT14 DSI_TCCR1_HSRD_TOCNT14_Msk 19157 #define DSI_TCCR1_HSRD_TOCNT15_Pos (15U) 19158 #define DSI_TCCR1_HSRD_TOCNT15_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT15_Pos) 19159 #define DSI_TCCR1_HSRD_TOCNT15 DSI_TCCR1_HSRD_TOCNT15_Msk 19162 #define DSI_TCCR2_LPRD_TOCNT_Pos (0U) 19163 #define DSI_TCCR2_LPRD_TOCNT_Msk (0xFFFFU << DSI_TCCR2_LPRD_TOCNT_Pos) 19164 #define DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk 19165 #define DSI_TCCR2_LPRD_TOCNT0_Pos (0U) 19166 #define DSI_TCCR2_LPRD_TOCNT0_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT0_Pos) 19167 #define DSI_TCCR2_LPRD_TOCNT0 DSI_TCCR2_LPRD_TOCNT0_Msk 19168 #define DSI_TCCR2_LPRD_TOCNT1_Pos (1U) 19169 #define DSI_TCCR2_LPRD_TOCNT1_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT1_Pos) 19170 #define DSI_TCCR2_LPRD_TOCNT1 DSI_TCCR2_LPRD_TOCNT1_Msk 19171 #define DSI_TCCR2_LPRD_TOCNT2_Pos (2U) 19172 #define DSI_TCCR2_LPRD_TOCNT2_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT2_Pos) 19173 #define DSI_TCCR2_LPRD_TOCNT2 DSI_TCCR2_LPRD_TOCNT2_Msk 19174 #define DSI_TCCR2_LPRD_TOCNT3_Pos (3U) 19175 #define DSI_TCCR2_LPRD_TOCNT3_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT3_Pos) 19176 #define DSI_TCCR2_LPRD_TOCNT3 DSI_TCCR2_LPRD_TOCNT3_Msk 19177 #define DSI_TCCR2_LPRD_TOCNT4_Pos (4U) 19178 #define DSI_TCCR2_LPRD_TOCNT4_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT4_Pos) 19179 #define DSI_TCCR2_LPRD_TOCNT4 DSI_TCCR2_LPRD_TOCNT4_Msk 19180 #define DSI_TCCR2_LPRD_TOCNT5_Pos (5U) 19181 #define DSI_TCCR2_LPRD_TOCNT5_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT5_Pos) 19182 #define DSI_TCCR2_LPRD_TOCNT5 DSI_TCCR2_LPRD_TOCNT5_Msk 19183 #define DSI_TCCR2_LPRD_TOCNT6_Pos (6U) 19184 #define DSI_TCCR2_LPRD_TOCNT6_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT6_Pos) 19185 #define DSI_TCCR2_LPRD_TOCNT6 DSI_TCCR2_LPRD_TOCNT6_Msk 19186 #define DSI_TCCR2_LPRD_TOCNT7_Pos (7U) 19187 #define DSI_TCCR2_LPRD_TOCNT7_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT7_Pos) 19188 #define DSI_TCCR2_LPRD_TOCNT7 DSI_TCCR2_LPRD_TOCNT7_Msk 19189 #define DSI_TCCR2_LPRD_TOCNT8_Pos (8U) 19190 #define DSI_TCCR2_LPRD_TOCNT8_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT8_Pos) 19191 #define DSI_TCCR2_LPRD_TOCNT8 DSI_TCCR2_LPRD_TOCNT8_Msk 19192 #define DSI_TCCR2_LPRD_TOCNT9_Pos (9U) 19193 #define DSI_TCCR2_LPRD_TOCNT9_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT9_Pos) 19194 #define DSI_TCCR2_LPRD_TOCNT9 DSI_TCCR2_LPRD_TOCNT9_Msk 19195 #define DSI_TCCR2_LPRD_TOCNT10_Pos (10U) 19196 #define DSI_TCCR2_LPRD_TOCNT10_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT10_Pos) 19197 #define DSI_TCCR2_LPRD_TOCNT10 DSI_TCCR2_LPRD_TOCNT10_Msk 19198 #define DSI_TCCR2_LPRD_TOCNT11_Pos (11U) 19199 #define DSI_TCCR2_LPRD_TOCNT11_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT11_Pos) 19200 #define DSI_TCCR2_LPRD_TOCNT11 DSI_TCCR2_LPRD_TOCNT11_Msk 19201 #define DSI_TCCR2_LPRD_TOCNT12_Pos (12U) 19202 #define DSI_TCCR2_LPRD_TOCNT12_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT12_Pos) 19203 #define DSI_TCCR2_LPRD_TOCNT12 DSI_TCCR2_LPRD_TOCNT12_Msk 19204 #define DSI_TCCR2_LPRD_TOCNT13_Pos (13U) 19205 #define DSI_TCCR2_LPRD_TOCNT13_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT13_Pos) 19206 #define DSI_TCCR2_LPRD_TOCNT13 DSI_TCCR2_LPRD_TOCNT13_Msk 19207 #define DSI_TCCR2_LPRD_TOCNT14_Pos (14U) 19208 #define DSI_TCCR2_LPRD_TOCNT14_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT14_Pos) 19209 #define DSI_TCCR2_LPRD_TOCNT14 DSI_TCCR2_LPRD_TOCNT14_Msk 19210 #define DSI_TCCR2_LPRD_TOCNT15_Pos (15U) 19211 #define DSI_TCCR2_LPRD_TOCNT15_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT15_Pos) 19212 #define DSI_TCCR2_LPRD_TOCNT15 DSI_TCCR2_LPRD_TOCNT15_Msk 19215 #define DSI_TCCR3_HSWR_TOCNT_Pos (0U) 19216 #define DSI_TCCR3_HSWR_TOCNT_Msk (0xFFFFU << DSI_TCCR3_HSWR_TOCNT_Pos) 19217 #define DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk 19218 #define DSI_TCCR3_HSWR_TOCNT0_Pos (0U) 19219 #define DSI_TCCR3_HSWR_TOCNT0_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT0_Pos) 19220 #define DSI_TCCR3_HSWR_TOCNT0 DSI_TCCR3_HSWR_TOCNT0_Msk 19221 #define DSI_TCCR3_HSWR_TOCNT1_Pos (1U) 19222 #define DSI_TCCR3_HSWR_TOCNT1_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT1_Pos) 19223 #define DSI_TCCR3_HSWR_TOCNT1 DSI_TCCR3_HSWR_TOCNT1_Msk 19224 #define DSI_TCCR3_HSWR_TOCNT2_Pos (2U) 19225 #define DSI_TCCR3_HSWR_TOCNT2_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT2_Pos) 19226 #define DSI_TCCR3_HSWR_TOCNT2 DSI_TCCR3_HSWR_TOCNT2_Msk 19227 #define DSI_TCCR3_HSWR_TOCNT3_Pos (3U) 19228 #define DSI_TCCR3_HSWR_TOCNT3_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT3_Pos) 19229 #define DSI_TCCR3_HSWR_TOCNT3 DSI_TCCR3_HSWR_TOCNT3_Msk 19230 #define DSI_TCCR3_HSWR_TOCNT4_Pos (4U) 19231 #define DSI_TCCR3_HSWR_TOCNT4_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT4_Pos) 19232 #define DSI_TCCR3_HSWR_TOCNT4 DSI_TCCR3_HSWR_TOCNT4_Msk 19233 #define DSI_TCCR3_HSWR_TOCNT5_Pos (5U) 19234 #define DSI_TCCR3_HSWR_TOCNT5_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT5_Pos) 19235 #define DSI_TCCR3_HSWR_TOCNT5 DSI_TCCR3_HSWR_TOCNT5_Msk 19236 #define DSI_TCCR3_HSWR_TOCNT6_Pos (6U) 19237 #define DSI_TCCR3_HSWR_TOCNT6_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT6_Pos) 19238 #define DSI_TCCR3_HSWR_TOCNT6 DSI_TCCR3_HSWR_TOCNT6_Msk 19239 #define DSI_TCCR3_HSWR_TOCNT7_Pos (7U) 19240 #define DSI_TCCR3_HSWR_TOCNT7_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT7_Pos) 19241 #define DSI_TCCR3_HSWR_TOCNT7 DSI_TCCR3_HSWR_TOCNT7_Msk 19242 #define DSI_TCCR3_HSWR_TOCNT8_Pos (8U) 19243 #define DSI_TCCR3_HSWR_TOCNT8_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT8_Pos) 19244 #define DSI_TCCR3_HSWR_TOCNT8 DSI_TCCR3_HSWR_TOCNT8_Msk 19245 #define DSI_TCCR3_HSWR_TOCNT9_Pos (9U) 19246 #define DSI_TCCR3_HSWR_TOCNT9_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT9_Pos) 19247 #define DSI_TCCR3_HSWR_TOCNT9 DSI_TCCR3_HSWR_TOCNT9_Msk 19248 #define DSI_TCCR3_HSWR_TOCNT10_Pos (10U) 19249 #define DSI_TCCR3_HSWR_TOCNT10_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT10_Pos) 19250 #define DSI_TCCR3_HSWR_TOCNT10 DSI_TCCR3_HSWR_TOCNT10_Msk 19251 #define DSI_TCCR3_HSWR_TOCNT11_Pos (11U) 19252 #define DSI_TCCR3_HSWR_TOCNT11_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT11_Pos) 19253 #define DSI_TCCR3_HSWR_TOCNT11 DSI_TCCR3_HSWR_TOCNT11_Msk 19254 #define DSI_TCCR3_HSWR_TOCNT12_Pos (12U) 19255 #define DSI_TCCR3_HSWR_TOCNT12_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT12_Pos) 19256 #define DSI_TCCR3_HSWR_TOCNT12 DSI_TCCR3_HSWR_TOCNT12_Msk 19257 #define DSI_TCCR3_HSWR_TOCNT13_Pos (13U) 19258 #define DSI_TCCR3_HSWR_TOCNT13_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT13_Pos) 19259 #define DSI_TCCR3_HSWR_TOCNT13 DSI_TCCR3_HSWR_TOCNT13_Msk 19260 #define DSI_TCCR3_HSWR_TOCNT14_Pos (14U) 19261 #define DSI_TCCR3_HSWR_TOCNT14_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT14_Pos) 19262 #define DSI_TCCR3_HSWR_TOCNT14 DSI_TCCR3_HSWR_TOCNT14_Msk 19263 #define DSI_TCCR3_HSWR_TOCNT15_Pos (15U) 19264 #define DSI_TCCR3_HSWR_TOCNT15_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT15_Pos) 19265 #define DSI_TCCR3_HSWR_TOCNT15 DSI_TCCR3_HSWR_TOCNT15_Msk 19267 #define DSI_TCCR3_PM_Pos (24U) 19268 #define DSI_TCCR3_PM_Msk (0x1U << DSI_TCCR3_PM_Pos) 19269 #define DSI_TCCR3_PM DSI_TCCR3_PM_Msk 19272 #define DSI_TCCR4_LPWR_TOCNT_Pos (0U) 19273 #define DSI_TCCR4_LPWR_TOCNT_Msk (0xFFFFU << DSI_TCCR4_LPWR_TOCNT_Pos) 19274 #define DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk 19275 #define DSI_TCCR4_LPWR_TOCNT0_Pos (0U) 19276 #define DSI_TCCR4_LPWR_TOCNT0_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT0_Pos) 19277 #define DSI_TCCR4_LPWR_TOCNT0 DSI_TCCR4_LPWR_TOCNT0_Msk 19278 #define DSI_TCCR4_LPWR_TOCNT1_Pos (1U) 19279 #define DSI_TCCR4_LPWR_TOCNT1_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT1_Pos) 19280 #define DSI_TCCR4_LPWR_TOCNT1 DSI_TCCR4_LPWR_TOCNT1_Msk 19281 #define DSI_TCCR4_LPWR_TOCNT2_Pos (2U) 19282 #define DSI_TCCR4_LPWR_TOCNT2_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT2_Pos) 19283 #define DSI_TCCR4_LPWR_TOCNT2 DSI_TCCR4_LPWR_TOCNT2_Msk 19284 #define DSI_TCCR4_LPWR_TOCNT3_Pos (3U) 19285 #define DSI_TCCR4_LPWR_TOCNT3_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT3_Pos) 19286 #define DSI_TCCR4_LPWR_TOCNT3 DSI_TCCR4_LPWR_TOCNT3_Msk 19287 #define DSI_TCCR4_LPWR_TOCNT4_Pos (4U) 19288 #define DSI_TCCR4_LPWR_TOCNT4_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT4_Pos) 19289 #define DSI_TCCR4_LPWR_TOCNT4 DSI_TCCR4_LPWR_TOCNT4_Msk 19290 #define DSI_TCCR4_LPWR_TOCNT5_Pos (5U) 19291 #define DSI_TCCR4_LPWR_TOCNT5_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT5_Pos) 19292 #define DSI_TCCR4_LPWR_TOCNT5 DSI_TCCR4_LPWR_TOCNT5_Msk 19293 #define DSI_TCCR4_LPWR_TOCNT6_Pos (6U) 19294 #define DSI_TCCR4_LPWR_TOCNT6_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT6_Pos) 19295 #define DSI_TCCR4_LPWR_TOCNT6 DSI_TCCR4_LPWR_TOCNT6_Msk 19296 #define DSI_TCCR4_LPWR_TOCNT7_Pos (7U) 19297 #define DSI_TCCR4_LPWR_TOCNT7_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT7_Pos) 19298 #define DSI_TCCR4_LPWR_TOCNT7 DSI_TCCR4_LPWR_TOCNT7_Msk 19299 #define DSI_TCCR4_LPWR_TOCNT8_Pos (8U) 19300 #define DSI_TCCR4_LPWR_TOCNT8_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT8_Pos) 19301 #define DSI_TCCR4_LPWR_TOCNT8 DSI_TCCR4_LPWR_TOCNT8_Msk 19302 #define DSI_TCCR4_LPWR_TOCNT9_Pos (9U) 19303 #define DSI_TCCR4_LPWR_TOCNT9_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT9_Pos) 19304 #define DSI_TCCR4_LPWR_TOCNT9 DSI_TCCR4_LPWR_TOCNT9_Msk 19305 #define DSI_TCCR4_LPWR_TOCNT10_Pos (10U) 19306 #define DSI_TCCR4_LPWR_TOCNT10_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT10_Pos) 19307 #define DSI_TCCR4_LPWR_TOCNT10 DSI_TCCR4_LPWR_TOCNT10_Msk 19308 #define DSI_TCCR4_LPWR_TOCNT11_Pos (11U) 19309 #define DSI_TCCR4_LPWR_TOCNT11_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT11_Pos) 19310 #define DSI_TCCR4_LPWR_TOCNT11 DSI_TCCR4_LPWR_TOCNT11_Msk 19311 #define DSI_TCCR4_LPWR_TOCNT12_Pos (12U) 19312 #define DSI_TCCR4_LPWR_TOCNT12_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT12_Pos) 19313 #define DSI_TCCR4_LPWR_TOCNT12 DSI_TCCR4_LPWR_TOCNT12_Msk 19314 #define DSI_TCCR4_LPWR_TOCNT13_Pos (13U) 19315 #define DSI_TCCR4_LPWR_TOCNT13_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT13_Pos) 19316 #define DSI_TCCR4_LPWR_TOCNT13 DSI_TCCR4_LPWR_TOCNT13_Msk 19317 #define DSI_TCCR4_LPWR_TOCNT14_Pos (14U) 19318 #define DSI_TCCR4_LPWR_TOCNT14_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT14_Pos) 19319 #define DSI_TCCR4_LPWR_TOCNT14 DSI_TCCR4_LPWR_TOCNT14_Msk 19320 #define DSI_TCCR4_LPWR_TOCNT15_Pos (15U) 19321 #define DSI_TCCR4_LPWR_TOCNT15_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT15_Pos) 19322 #define DSI_TCCR4_LPWR_TOCNT15 DSI_TCCR4_LPWR_TOCNT15_Msk 19325 #define DSI_TCCR5_BTA_TOCNT_Pos (0U) 19326 #define DSI_TCCR5_BTA_TOCNT_Msk (0xFFFFU << DSI_TCCR5_BTA_TOCNT_Pos) 19327 #define DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk 19328 #define DSI_TCCR5_BTA_TOCNT0_Pos (0U) 19329 #define DSI_TCCR5_BTA_TOCNT0_Msk (0x1U << DSI_TCCR5_BTA_TOCNT0_Pos) 19330 #define DSI_TCCR5_BTA_TOCNT0 DSI_TCCR5_BTA_TOCNT0_Msk 19331 #define DSI_TCCR5_BTA_TOCNT1_Pos (1U) 19332 #define DSI_TCCR5_BTA_TOCNT1_Msk (0x1U << DSI_TCCR5_BTA_TOCNT1_Pos) 19333 #define DSI_TCCR5_BTA_TOCNT1 DSI_TCCR5_BTA_TOCNT1_Msk 19334 #define DSI_TCCR5_BTA_TOCNT2_Pos (2U) 19335 #define DSI_TCCR5_BTA_TOCNT2_Msk (0x1U << DSI_TCCR5_BTA_TOCNT2_Pos) 19336 #define DSI_TCCR5_BTA_TOCNT2 DSI_TCCR5_BTA_TOCNT2_Msk 19337 #define DSI_TCCR5_BTA_TOCNT3_Pos (3U) 19338 #define DSI_TCCR5_BTA_TOCNT3_Msk (0x1U << DSI_TCCR5_BTA_TOCNT3_Pos) 19339 #define DSI_TCCR5_BTA_TOCNT3 DSI_TCCR5_BTA_TOCNT3_Msk 19340 #define DSI_TCCR5_BTA_TOCNT4_Pos (4U) 19341 #define DSI_TCCR5_BTA_TOCNT4_Msk (0x1U << DSI_TCCR5_BTA_TOCNT4_Pos) 19342 #define DSI_TCCR5_BTA_TOCNT4 DSI_TCCR5_BTA_TOCNT4_Msk 19343 #define DSI_TCCR5_BTA_TOCNT5_Pos (5U) 19344 #define DSI_TCCR5_BTA_TOCNT5_Msk (0x1U << DSI_TCCR5_BTA_TOCNT5_Pos) 19345 #define DSI_TCCR5_BTA_TOCNT5 DSI_TCCR5_BTA_TOCNT5_Msk 19346 #define DSI_TCCR5_BTA_TOCNT6_Pos (6U) 19347 #define DSI_TCCR5_BTA_TOCNT6_Msk (0x1U << DSI_TCCR5_BTA_TOCNT6_Pos) 19348 #define DSI_TCCR5_BTA_TOCNT6 DSI_TCCR5_BTA_TOCNT6_Msk 19349 #define DSI_TCCR5_BTA_TOCNT7_Pos (7U) 19350 #define DSI_TCCR5_BTA_TOCNT7_Msk (0x1U << DSI_TCCR5_BTA_TOCNT7_Pos) 19351 #define DSI_TCCR5_BTA_TOCNT7 DSI_TCCR5_BTA_TOCNT7_Msk 19352 #define DSI_TCCR5_BTA_TOCNT8_Pos (8U) 19353 #define DSI_TCCR5_BTA_TOCNT8_Msk (0x1U << DSI_TCCR5_BTA_TOCNT8_Pos) 19354 #define DSI_TCCR5_BTA_TOCNT8 DSI_TCCR5_BTA_TOCNT8_Msk 19355 #define DSI_TCCR5_BTA_TOCNT9_Pos (9U) 19356 #define DSI_TCCR5_BTA_TOCNT9_Msk (0x1U << DSI_TCCR5_BTA_TOCNT9_Pos) 19357 #define DSI_TCCR5_BTA_TOCNT9 DSI_TCCR5_BTA_TOCNT9_Msk 19358 #define DSI_TCCR5_BTA_TOCNT10_Pos (10U) 19359 #define DSI_TCCR5_BTA_TOCNT10_Msk (0x1U << DSI_TCCR5_BTA_TOCNT10_Pos) 19360 #define DSI_TCCR5_BTA_TOCNT10 DSI_TCCR5_BTA_TOCNT10_Msk 19361 #define DSI_TCCR5_BTA_TOCNT11_Pos (11U) 19362 #define DSI_TCCR5_BTA_TOCNT11_Msk (0x1U << DSI_TCCR5_BTA_TOCNT11_Pos) 19363 #define DSI_TCCR5_BTA_TOCNT11 DSI_TCCR5_BTA_TOCNT11_Msk 19364 #define DSI_TCCR5_BTA_TOCNT12_Pos (12U) 19365 #define DSI_TCCR5_BTA_TOCNT12_Msk (0x1U << DSI_TCCR5_BTA_TOCNT12_Pos) 19366 #define DSI_TCCR5_BTA_TOCNT12 DSI_TCCR5_BTA_TOCNT12_Msk 19367 #define DSI_TCCR5_BTA_TOCNT13_Pos (13U) 19368 #define DSI_TCCR5_BTA_TOCNT13_Msk (0x1U << DSI_TCCR5_BTA_TOCNT13_Pos) 19369 #define DSI_TCCR5_BTA_TOCNT13 DSI_TCCR5_BTA_TOCNT13_Msk 19370 #define DSI_TCCR5_BTA_TOCNT14_Pos (14U) 19371 #define DSI_TCCR5_BTA_TOCNT14_Msk (0x1U << DSI_TCCR5_BTA_TOCNT14_Pos) 19372 #define DSI_TCCR5_BTA_TOCNT14 DSI_TCCR5_BTA_TOCNT14_Msk 19373 #define DSI_TCCR5_BTA_TOCNT15_Pos (15U) 19374 #define DSI_TCCR5_BTA_TOCNT15_Msk (0x1U << DSI_TCCR5_BTA_TOCNT15_Pos) 19375 #define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk 19378 #define DSI_TDCR_3DM 0x00000003U 19379 #define DSI_TDCR_3DM0 0x00000001U 19380 #define DSI_TDCR_3DM1 0x00000002U 19382 #define DSI_TDCR_3DF 0x0000000CU 19383 #define DSI_TDCR_3DF0 0x00000004U 19384 #define DSI_TDCR_3DF1 0x00000008U 19386 #define DSI_TDCR_SVS_Pos (4U) 19387 #define DSI_TDCR_SVS_Msk (0x1U << DSI_TDCR_SVS_Pos) 19388 #define DSI_TDCR_SVS DSI_TDCR_SVS_Msk 19389 #define DSI_TDCR_RF_Pos (5U) 19390 #define DSI_TDCR_RF_Msk (0x1U << DSI_TDCR_RF_Pos) 19391 #define DSI_TDCR_RF DSI_TDCR_RF_Msk 19392 #define DSI_TDCR_S3DC_Pos (16U) 19393 #define DSI_TDCR_S3DC_Msk (0x1U << DSI_TDCR_S3DC_Pos) 19394 #define DSI_TDCR_S3DC DSI_TDCR_S3DC_Msk 19397 #define DSI_CLCR_DPCC_Pos (0U) 19398 #define DSI_CLCR_DPCC_Msk (0x1U << DSI_CLCR_DPCC_Pos) 19399 #define DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk 19400 #define DSI_CLCR_ACR_Pos (1U) 19401 #define DSI_CLCR_ACR_Msk (0x1U << DSI_CLCR_ACR_Pos) 19402 #define DSI_CLCR_ACR DSI_CLCR_ACR_Msk 19405 #define DSI_CLTCR_LP2HS_TIME_Pos (0U) 19406 #define DSI_CLTCR_LP2HS_TIME_Msk (0x3FFU << DSI_CLTCR_LP2HS_TIME_Pos) 19407 #define DSI_CLTCR_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk 19408 #define DSI_CLTCR_LP2HS_TIME0_Pos (0U) 19409 #define DSI_CLTCR_LP2HS_TIME0_Msk (0x1U << DSI_CLTCR_LP2HS_TIME0_Pos) 19410 #define DSI_CLTCR_LP2HS_TIME0 DSI_CLTCR_LP2HS_TIME0_Msk 19411 #define DSI_CLTCR_LP2HS_TIME1_Pos (1U) 19412 #define DSI_CLTCR_LP2HS_TIME1_Msk (0x1U << DSI_CLTCR_LP2HS_TIME1_Pos) 19413 #define DSI_CLTCR_LP2HS_TIME1 DSI_CLTCR_LP2HS_TIME1_Msk 19414 #define DSI_CLTCR_LP2HS_TIME2_Pos (2U) 19415 #define DSI_CLTCR_LP2HS_TIME2_Msk (0x1U << DSI_CLTCR_LP2HS_TIME2_Pos) 19416 #define DSI_CLTCR_LP2HS_TIME2 DSI_CLTCR_LP2HS_TIME2_Msk 19417 #define DSI_CLTCR_LP2HS_TIME3_Pos (3U) 19418 #define DSI_CLTCR_LP2HS_TIME3_Msk (0x1U << DSI_CLTCR_LP2HS_TIME3_Pos) 19419 #define DSI_CLTCR_LP2HS_TIME3 DSI_CLTCR_LP2HS_TIME3_Msk 19420 #define DSI_CLTCR_LP2HS_TIME4_Pos (4U) 19421 #define DSI_CLTCR_LP2HS_TIME4_Msk (0x1U << DSI_CLTCR_LP2HS_TIME4_Pos) 19422 #define DSI_CLTCR_LP2HS_TIME4 DSI_CLTCR_LP2HS_TIME4_Msk 19423 #define DSI_CLTCR_LP2HS_TIME5_Pos (5U) 19424 #define DSI_CLTCR_LP2HS_TIME5_Msk (0x1U << DSI_CLTCR_LP2HS_TIME5_Pos) 19425 #define DSI_CLTCR_LP2HS_TIME5 DSI_CLTCR_LP2HS_TIME5_Msk 19426 #define DSI_CLTCR_LP2HS_TIME6_Pos (6U) 19427 #define DSI_CLTCR_LP2HS_TIME6_Msk (0x1U << DSI_CLTCR_LP2HS_TIME6_Pos) 19428 #define DSI_CLTCR_LP2HS_TIME6 DSI_CLTCR_LP2HS_TIME6_Msk 19429 #define DSI_CLTCR_LP2HS_TIME7_Pos (7U) 19430 #define DSI_CLTCR_LP2HS_TIME7_Msk (0x1U << DSI_CLTCR_LP2HS_TIME7_Pos) 19431 #define DSI_CLTCR_LP2HS_TIME7 DSI_CLTCR_LP2HS_TIME7_Msk 19432 #define DSI_CLTCR_LP2HS_TIME8_Pos (8U) 19433 #define DSI_CLTCR_LP2HS_TIME8_Msk (0x1U << DSI_CLTCR_LP2HS_TIME8_Pos) 19434 #define DSI_CLTCR_LP2HS_TIME8 DSI_CLTCR_LP2HS_TIME8_Msk 19435 #define DSI_CLTCR_LP2HS_TIME9_Pos (9U) 19436 #define DSI_CLTCR_LP2HS_TIME9_Msk (0x1U << DSI_CLTCR_LP2HS_TIME9_Pos) 19437 #define DSI_CLTCR_LP2HS_TIME9 DSI_CLTCR_LP2HS_TIME9_Msk 19439 #define DSI_CLTCR_HS2LP_TIME_Pos (16U) 19440 #define DSI_CLTCR_HS2LP_TIME_Msk (0x3FFU << DSI_CLTCR_HS2LP_TIME_Pos) 19441 #define DSI_CLTCR_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk 19442 #define DSI_CLTCR_HS2LP_TIME0_Pos (16U) 19443 #define DSI_CLTCR_HS2LP_TIME0_Msk (0x1U << DSI_CLTCR_HS2LP_TIME0_Pos) 19444 #define DSI_CLTCR_HS2LP_TIME0 DSI_CLTCR_HS2LP_TIME0_Msk 19445 #define DSI_CLTCR_HS2LP_TIME1_Pos (17U) 19446 #define DSI_CLTCR_HS2LP_TIME1_Msk (0x1U << DSI_CLTCR_HS2LP_TIME1_Pos) 19447 #define DSI_CLTCR_HS2LP_TIME1 DSI_CLTCR_HS2LP_TIME1_Msk 19448 #define DSI_CLTCR_HS2LP_TIME2_Pos (18U) 19449 #define DSI_CLTCR_HS2LP_TIME2_Msk (0x1U << DSI_CLTCR_HS2LP_TIME2_Pos) 19450 #define DSI_CLTCR_HS2LP_TIME2 DSI_CLTCR_HS2LP_TIME2_Msk 19451 #define DSI_CLTCR_HS2LP_TIME3_Pos (19U) 19452 #define DSI_CLTCR_HS2LP_TIME3_Msk (0x1U << DSI_CLTCR_HS2LP_TIME3_Pos) 19453 #define DSI_CLTCR_HS2LP_TIME3 DSI_CLTCR_HS2LP_TIME3_Msk 19454 #define DSI_CLTCR_HS2LP_TIME4_Pos (20U) 19455 #define DSI_CLTCR_HS2LP_TIME4_Msk (0x1U << DSI_CLTCR_HS2LP_TIME4_Pos) 19456 #define DSI_CLTCR_HS2LP_TIME4 DSI_CLTCR_HS2LP_TIME4_Msk 19457 #define DSI_CLTCR_HS2LP_TIME5_Pos (21U) 19458 #define DSI_CLTCR_HS2LP_TIME5_Msk (0x1U << DSI_CLTCR_HS2LP_TIME5_Pos) 19459 #define DSI_CLTCR_HS2LP_TIME5 DSI_CLTCR_HS2LP_TIME5_Msk 19460 #define DSI_CLTCR_HS2LP_TIME6_Pos (22U) 19461 #define DSI_CLTCR_HS2LP_TIME6_Msk (0x1U << DSI_CLTCR_HS2LP_TIME6_Pos) 19462 #define DSI_CLTCR_HS2LP_TIME6 DSI_CLTCR_HS2LP_TIME6_Msk 19463 #define DSI_CLTCR_HS2LP_TIME7_Pos (23U) 19464 #define DSI_CLTCR_HS2LP_TIME7_Msk (0x1U << DSI_CLTCR_HS2LP_TIME7_Pos) 19465 #define DSI_CLTCR_HS2LP_TIME7 DSI_CLTCR_HS2LP_TIME7_Msk 19466 #define DSI_CLTCR_HS2LP_TIME8_Pos (24U) 19467 #define DSI_CLTCR_HS2LP_TIME8_Msk (0x1U << DSI_CLTCR_HS2LP_TIME8_Pos) 19468 #define DSI_CLTCR_HS2LP_TIME8 DSI_CLTCR_HS2LP_TIME8_Msk 19469 #define DSI_CLTCR_HS2LP_TIME9_Pos (25U) 19470 #define DSI_CLTCR_HS2LP_TIME9_Msk (0x1U << DSI_CLTCR_HS2LP_TIME9_Pos) 19471 #define DSI_CLTCR_HS2LP_TIME9 DSI_CLTCR_HS2LP_TIME9_Msk 19474 #define DSI_DLTCR_MRD_TIME_Pos (0U) 19475 #define DSI_DLTCR_MRD_TIME_Msk (0x7FFFU << DSI_DLTCR_MRD_TIME_Pos) 19476 #define DSI_DLTCR_MRD_TIME DSI_DLTCR_MRD_TIME_Msk 19477 #define DSI_DLTCR_MRD_TIME0_Pos (0U) 19478 #define DSI_DLTCR_MRD_TIME0_Msk (0x1U << DSI_DLTCR_MRD_TIME0_Pos) 19479 #define DSI_DLTCR_MRD_TIME0 DSI_DLTCR_MRD_TIME0_Msk 19480 #define DSI_DLTCR_MRD_TIME1_Pos (1U) 19481 #define DSI_DLTCR_MRD_TIME1_Msk (0x1U << DSI_DLTCR_MRD_TIME1_Pos) 19482 #define DSI_DLTCR_MRD_TIME1 DSI_DLTCR_MRD_TIME1_Msk 19483 #define DSI_DLTCR_MRD_TIME2_Pos (2U) 19484 #define DSI_DLTCR_MRD_TIME2_Msk (0x1U << DSI_DLTCR_MRD_TIME2_Pos) 19485 #define DSI_DLTCR_MRD_TIME2 DSI_DLTCR_MRD_TIME2_Msk 19486 #define DSI_DLTCR_MRD_TIME3_Pos (3U) 19487 #define DSI_DLTCR_MRD_TIME3_Msk (0x1U << DSI_DLTCR_MRD_TIME3_Pos) 19488 #define DSI_DLTCR_MRD_TIME3 DSI_DLTCR_MRD_TIME3_Msk 19489 #define DSI_DLTCR_MRD_TIME4_Pos (4U) 19490 #define DSI_DLTCR_MRD_TIME4_Msk (0x1U << DSI_DLTCR_MRD_TIME4_Pos) 19491 #define DSI_DLTCR_MRD_TIME4 DSI_DLTCR_MRD_TIME4_Msk 19492 #define DSI_DLTCR_MRD_TIME5_Pos (5U) 19493 #define DSI_DLTCR_MRD_TIME5_Msk (0x1U << DSI_DLTCR_MRD_TIME5_Pos) 19494 #define DSI_DLTCR_MRD_TIME5 DSI_DLTCR_MRD_TIME5_Msk 19495 #define DSI_DLTCR_MRD_TIME6_Pos (6U) 19496 #define DSI_DLTCR_MRD_TIME6_Msk (0x1U << DSI_DLTCR_MRD_TIME6_Pos) 19497 #define DSI_DLTCR_MRD_TIME6 DSI_DLTCR_MRD_TIME6_Msk 19498 #define DSI_DLTCR_MRD_TIME7_Pos (7U) 19499 #define DSI_DLTCR_MRD_TIME7_Msk (0x1U << DSI_DLTCR_MRD_TIME7_Pos) 19500 #define DSI_DLTCR_MRD_TIME7 DSI_DLTCR_MRD_TIME7_Msk 19501 #define DSI_DLTCR_MRD_TIME8_Pos (8U) 19502 #define DSI_DLTCR_MRD_TIME8_Msk (0x1U << DSI_DLTCR_MRD_TIME8_Pos) 19503 #define DSI_DLTCR_MRD_TIME8 DSI_DLTCR_MRD_TIME8_Msk 19504 #define DSI_DLTCR_MRD_TIME9_Pos (9U) 19505 #define DSI_DLTCR_MRD_TIME9_Msk (0x1U << DSI_DLTCR_MRD_TIME9_Pos) 19506 #define DSI_DLTCR_MRD_TIME9 DSI_DLTCR_MRD_TIME9_Msk 19507 #define DSI_DLTCR_MRD_TIME10_Pos (10U) 19508 #define DSI_DLTCR_MRD_TIME10_Msk (0x1U << DSI_DLTCR_MRD_TIME10_Pos) 19509 #define DSI_DLTCR_MRD_TIME10 DSI_DLTCR_MRD_TIME10_Msk 19510 #define DSI_DLTCR_MRD_TIME11_Pos (11U) 19511 #define DSI_DLTCR_MRD_TIME11_Msk (0x1U << DSI_DLTCR_MRD_TIME11_Pos) 19512 #define DSI_DLTCR_MRD_TIME11 DSI_DLTCR_MRD_TIME11_Msk 19513 #define DSI_DLTCR_MRD_TIME12_Pos (12U) 19514 #define DSI_DLTCR_MRD_TIME12_Msk (0x1U << DSI_DLTCR_MRD_TIME12_Pos) 19515 #define DSI_DLTCR_MRD_TIME12 DSI_DLTCR_MRD_TIME12_Msk 19516 #define DSI_DLTCR_MRD_TIME13_Pos (13U) 19517 #define DSI_DLTCR_MRD_TIME13_Msk (0x1U << DSI_DLTCR_MRD_TIME13_Pos) 19518 #define DSI_DLTCR_MRD_TIME13 DSI_DLTCR_MRD_TIME13_Msk 19519 #define DSI_DLTCR_MRD_TIME14_Pos (14U) 19520 #define DSI_DLTCR_MRD_TIME14_Msk (0x1U << DSI_DLTCR_MRD_TIME14_Pos) 19521 #define DSI_DLTCR_MRD_TIME14 DSI_DLTCR_MRD_TIME14_Msk 19523 #define DSI_DLTCR_LP2HS_TIME_Pos (16U) 19524 #define DSI_DLTCR_LP2HS_TIME_Msk (0xFFU << DSI_DLTCR_LP2HS_TIME_Pos) 19525 #define DSI_DLTCR_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk 19526 #define DSI_DLTCR_LP2HS_TIME0_Pos (16U) 19527 #define DSI_DLTCR_LP2HS_TIME0_Msk (0x1U << DSI_DLTCR_LP2HS_TIME0_Pos) 19528 #define DSI_DLTCR_LP2HS_TIME0 DSI_DLTCR_LP2HS_TIME0_Msk 19529 #define DSI_DLTCR_LP2HS_TIME1_Pos (17U) 19530 #define DSI_DLTCR_LP2HS_TIME1_Msk (0x1U << DSI_DLTCR_LP2HS_TIME1_Pos) 19531 #define DSI_DLTCR_LP2HS_TIME1 DSI_DLTCR_LP2HS_TIME1_Msk 19532 #define DSI_DLTCR_LP2HS_TIME2_Pos (18U) 19533 #define DSI_DLTCR_LP2HS_TIME2_Msk (0x1U << DSI_DLTCR_LP2HS_TIME2_Pos) 19534 #define DSI_DLTCR_LP2HS_TIME2 DSI_DLTCR_LP2HS_TIME2_Msk 19535 #define DSI_DLTCR_LP2HS_TIME3_Pos (19U) 19536 #define DSI_DLTCR_LP2HS_TIME3_Msk (0x1U << DSI_DLTCR_LP2HS_TIME3_Pos) 19537 #define DSI_DLTCR_LP2HS_TIME3 DSI_DLTCR_LP2HS_TIME3_Msk 19538 #define DSI_DLTCR_LP2HS_TIME4_Pos (20U) 19539 #define DSI_DLTCR_LP2HS_TIME4_Msk (0x1U << DSI_DLTCR_LP2HS_TIME4_Pos) 19540 #define DSI_DLTCR_LP2HS_TIME4 DSI_DLTCR_LP2HS_TIME4_Msk 19541 #define DSI_DLTCR_LP2HS_TIME5_Pos (21U) 19542 #define DSI_DLTCR_LP2HS_TIME5_Msk (0x1U << DSI_DLTCR_LP2HS_TIME5_Pos) 19543 #define DSI_DLTCR_LP2HS_TIME5 DSI_DLTCR_LP2HS_TIME5_Msk 19544 #define DSI_DLTCR_LP2HS_TIME6_Pos (22U) 19545 #define DSI_DLTCR_LP2HS_TIME6_Msk (0x1U << DSI_DLTCR_LP2HS_TIME6_Pos) 19546 #define DSI_DLTCR_LP2HS_TIME6 DSI_DLTCR_LP2HS_TIME6_Msk 19547 #define DSI_DLTCR_LP2HS_TIME7_Pos (23U) 19548 #define DSI_DLTCR_LP2HS_TIME7_Msk (0x1U << DSI_DLTCR_LP2HS_TIME7_Pos) 19549 #define DSI_DLTCR_LP2HS_TIME7 DSI_DLTCR_LP2HS_TIME7_Msk 19551 #define DSI_DLTCR_HS2LP_TIME_Pos (24U) 19552 #define DSI_DLTCR_HS2LP_TIME_Msk (0xFFU << DSI_DLTCR_HS2LP_TIME_Pos) 19553 #define DSI_DLTCR_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk 19554 #define DSI_DLTCR_HS2LP_TIME0_Pos (24U) 19555 #define DSI_DLTCR_HS2LP_TIME0_Msk (0x1U << DSI_DLTCR_HS2LP_TIME0_Pos) 19556 #define DSI_DLTCR_HS2LP_TIME0 DSI_DLTCR_HS2LP_TIME0_Msk 19557 #define DSI_DLTCR_HS2LP_TIME1_Pos (25U) 19558 #define DSI_DLTCR_HS2LP_TIME1_Msk (0x1U << DSI_DLTCR_HS2LP_TIME1_Pos) 19559 #define DSI_DLTCR_HS2LP_TIME1 DSI_DLTCR_HS2LP_TIME1_Msk 19560 #define DSI_DLTCR_HS2LP_TIME2_Pos (26U) 19561 #define DSI_DLTCR_HS2LP_TIME2_Msk (0x1U << DSI_DLTCR_HS2LP_TIME2_Pos) 19562 #define DSI_DLTCR_HS2LP_TIME2 DSI_DLTCR_HS2LP_TIME2_Msk 19563 #define DSI_DLTCR_HS2LP_TIME3_Pos (27U) 19564 #define DSI_DLTCR_HS2LP_TIME3_Msk (0x1U << DSI_DLTCR_HS2LP_TIME3_Pos) 19565 #define DSI_DLTCR_HS2LP_TIME3 DSI_DLTCR_HS2LP_TIME3_Msk 19566 #define DSI_DLTCR_HS2LP_TIME4_Pos (28U) 19567 #define DSI_DLTCR_HS2LP_TIME4_Msk (0x1U << DSI_DLTCR_HS2LP_TIME4_Pos) 19568 #define DSI_DLTCR_HS2LP_TIME4 DSI_DLTCR_HS2LP_TIME4_Msk 19569 #define DSI_DLTCR_HS2LP_TIME5_Pos (29U) 19570 #define DSI_DLTCR_HS2LP_TIME5_Msk (0x1U << DSI_DLTCR_HS2LP_TIME5_Pos) 19571 #define DSI_DLTCR_HS2LP_TIME5 DSI_DLTCR_HS2LP_TIME5_Msk 19572 #define DSI_DLTCR_HS2LP_TIME6_Pos (30U) 19573 #define DSI_DLTCR_HS2LP_TIME6_Msk (0x1U << DSI_DLTCR_HS2LP_TIME6_Pos) 19574 #define DSI_DLTCR_HS2LP_TIME6 DSI_DLTCR_HS2LP_TIME6_Msk 19575 #define DSI_DLTCR_HS2LP_TIME7_Pos (31U) 19576 #define DSI_DLTCR_HS2LP_TIME7_Msk (0x1U << DSI_DLTCR_HS2LP_TIME7_Pos) 19577 #define DSI_DLTCR_HS2LP_TIME7 DSI_DLTCR_HS2LP_TIME7_Msk 19580 #define DSI_PCTLR_DEN_Pos (1U) 19581 #define DSI_PCTLR_DEN_Msk (0x1U << DSI_PCTLR_DEN_Pos) 19582 #define DSI_PCTLR_DEN DSI_PCTLR_DEN_Msk 19583 #define DSI_PCTLR_CKE_Pos (2U) 19584 #define DSI_PCTLR_CKE_Msk (0x1U << DSI_PCTLR_CKE_Pos) 19585 #define DSI_PCTLR_CKE DSI_PCTLR_CKE_Msk 19588 #define DSI_PCONFR_NL_Pos (0U) 19589 #define DSI_PCONFR_NL_Msk (0x3U << DSI_PCONFR_NL_Pos) 19590 #define DSI_PCONFR_NL DSI_PCONFR_NL_Msk 19591 #define DSI_PCONFR_NL0_Pos (0U) 19592 #define DSI_PCONFR_NL0_Msk (0x1U << DSI_PCONFR_NL0_Pos) 19593 #define DSI_PCONFR_NL0 DSI_PCONFR_NL0_Msk 19594 #define DSI_PCONFR_NL1_Pos (1U) 19595 #define DSI_PCONFR_NL1_Msk (0x1U << DSI_PCONFR_NL1_Pos) 19596 #define DSI_PCONFR_NL1 DSI_PCONFR_NL1_Msk 19598 #define DSI_PCONFR_SW_TIME_Pos (8U) 19599 #define DSI_PCONFR_SW_TIME_Msk (0xFFU << DSI_PCONFR_SW_TIME_Pos) 19600 #define DSI_PCONFR_SW_TIME DSI_PCONFR_SW_TIME_Msk 19601 #define DSI_PCONFR_SW_TIME0_Pos (8U) 19602 #define DSI_PCONFR_SW_TIME0_Msk (0x1U << DSI_PCONFR_SW_TIME0_Pos) 19603 #define DSI_PCONFR_SW_TIME0 DSI_PCONFR_SW_TIME0_Msk 19604 #define DSI_PCONFR_SW_TIME1_Pos (9U) 19605 #define DSI_PCONFR_SW_TIME1_Msk (0x1U << DSI_PCONFR_SW_TIME1_Pos) 19606 #define DSI_PCONFR_SW_TIME1 DSI_PCONFR_SW_TIME1_Msk 19607 #define DSI_PCONFR_SW_TIME2_Pos (10U) 19608 #define DSI_PCONFR_SW_TIME2_Msk (0x1U << DSI_PCONFR_SW_TIME2_Pos) 19609 #define DSI_PCONFR_SW_TIME2 DSI_PCONFR_SW_TIME2_Msk 19610 #define DSI_PCONFR_SW_TIME3_Pos (11U) 19611 #define DSI_PCONFR_SW_TIME3_Msk (0x1U << DSI_PCONFR_SW_TIME3_Pos) 19612 #define DSI_PCONFR_SW_TIME3 DSI_PCONFR_SW_TIME3_Msk 19613 #define DSI_PCONFR_SW_TIME4_Pos (12U) 19614 #define DSI_PCONFR_SW_TIME4_Msk (0x1U << DSI_PCONFR_SW_TIME4_Pos) 19615 #define DSI_PCONFR_SW_TIME4 DSI_PCONFR_SW_TIME4_Msk 19616 #define DSI_PCONFR_SW_TIME5_Pos (13U) 19617 #define DSI_PCONFR_SW_TIME5_Msk (0x1U << DSI_PCONFR_SW_TIME5_Pos) 19618 #define DSI_PCONFR_SW_TIME5 DSI_PCONFR_SW_TIME5_Msk 19619 #define DSI_PCONFR_SW_TIME6_Pos (14U) 19620 #define DSI_PCONFR_SW_TIME6_Msk (0x1U << DSI_PCONFR_SW_TIME6_Pos) 19621 #define DSI_PCONFR_SW_TIME6 DSI_PCONFR_SW_TIME6_Msk 19622 #define DSI_PCONFR_SW_TIME7_Pos (15U) 19623 #define DSI_PCONFR_SW_TIME7_Msk (0x1U << DSI_PCONFR_SW_TIME7_Pos) 19624 #define DSI_PCONFR_SW_TIME7 DSI_PCONFR_SW_TIME7_Msk 19627 #define DSI_PUCR_URCL_Pos (0U) 19628 #define DSI_PUCR_URCL_Msk (0x1U << DSI_PUCR_URCL_Pos) 19629 #define DSI_PUCR_URCL DSI_PUCR_URCL_Msk 19630 #define DSI_PUCR_UECL_Pos (1U) 19631 #define DSI_PUCR_UECL_Msk (0x1U << DSI_PUCR_UECL_Pos) 19632 #define DSI_PUCR_UECL DSI_PUCR_UECL_Msk 19633 #define DSI_PUCR_URDL_Pos (2U) 19634 #define DSI_PUCR_URDL_Msk (0x1U << DSI_PUCR_URDL_Pos) 19635 #define DSI_PUCR_URDL DSI_PUCR_URDL_Msk 19636 #define DSI_PUCR_UEDL_Pos (3U) 19637 #define DSI_PUCR_UEDL_Msk (0x1U << DSI_PUCR_UEDL_Pos) 19638 #define DSI_PUCR_UEDL DSI_PUCR_UEDL_Msk 19641 #define DSI_PTTCR_TX_TRIG_Pos (0U) 19642 #define DSI_PTTCR_TX_TRIG_Msk (0xFU << DSI_PTTCR_TX_TRIG_Pos) 19643 #define DSI_PTTCR_TX_TRIG DSI_PTTCR_TX_TRIG_Msk 19644 #define DSI_PTTCR_TX_TRIG0_Pos (0U) 19645 #define DSI_PTTCR_TX_TRIG0_Msk (0x1U << DSI_PTTCR_TX_TRIG0_Pos) 19646 #define DSI_PTTCR_TX_TRIG0 DSI_PTTCR_TX_TRIG0_Msk 19647 #define DSI_PTTCR_TX_TRIG1_Pos (1U) 19648 #define DSI_PTTCR_TX_TRIG1_Msk (0x1U << DSI_PTTCR_TX_TRIG1_Pos) 19649 #define DSI_PTTCR_TX_TRIG1 DSI_PTTCR_TX_TRIG1_Msk 19650 #define DSI_PTTCR_TX_TRIG2_Pos (2U) 19651 #define DSI_PTTCR_TX_TRIG2_Msk (0x1U << DSI_PTTCR_TX_TRIG2_Pos) 19652 #define DSI_PTTCR_TX_TRIG2 DSI_PTTCR_TX_TRIG2_Msk 19653 #define DSI_PTTCR_TX_TRIG3_Pos (3U) 19654 #define DSI_PTTCR_TX_TRIG3_Msk (0x1U << DSI_PTTCR_TX_TRIG3_Pos) 19655 #define DSI_PTTCR_TX_TRIG3 DSI_PTTCR_TX_TRIG3_Msk 19658 #define DSI_PSR_PD_Pos (1U) 19659 #define DSI_PSR_PD_Msk (0x1U << DSI_PSR_PD_Pos) 19660 #define DSI_PSR_PD DSI_PSR_PD_Msk 19661 #define DSI_PSR_PSSC_Pos (2U) 19662 #define DSI_PSR_PSSC_Msk (0x1U << DSI_PSR_PSSC_Pos) 19663 #define DSI_PSR_PSSC DSI_PSR_PSSC_Msk 19664 #define DSI_PSR_UANC_Pos (3U) 19665 #define DSI_PSR_UANC_Msk (0x1U << DSI_PSR_UANC_Pos) 19666 #define DSI_PSR_UANC DSI_PSR_UANC_Msk 19667 #define DSI_PSR_PSS0_Pos (4U) 19668 #define DSI_PSR_PSS0_Msk (0x1U << DSI_PSR_PSS0_Pos) 19669 #define DSI_PSR_PSS0 DSI_PSR_PSS0_Msk 19670 #define DSI_PSR_UAN0_Pos (5U) 19671 #define DSI_PSR_UAN0_Msk (0x1U << DSI_PSR_UAN0_Pos) 19672 #define DSI_PSR_UAN0 DSI_PSR_UAN0_Msk 19673 #define DSI_PSR_RUE0_Pos (6U) 19674 #define DSI_PSR_RUE0_Msk (0x1U << DSI_PSR_RUE0_Pos) 19675 #define DSI_PSR_RUE0 DSI_PSR_RUE0_Msk 19676 #define DSI_PSR_PSS1_Pos (7U) 19677 #define DSI_PSR_PSS1_Msk (0x1U << DSI_PSR_PSS1_Pos) 19678 #define DSI_PSR_PSS1 DSI_PSR_PSS1_Msk 19679 #define DSI_PSR_UAN1_Pos (8U) 19680 #define DSI_PSR_UAN1_Msk (0x1U << DSI_PSR_UAN1_Pos) 19681 #define DSI_PSR_UAN1 DSI_PSR_UAN1_Msk 19684 #define DSI_ISR0_AE0_Pos (0U) 19685 #define DSI_ISR0_AE0_Msk (0x1U << DSI_ISR0_AE0_Pos) 19686 #define DSI_ISR0_AE0 DSI_ISR0_AE0_Msk 19687 #define DSI_ISR0_AE1_Pos (1U) 19688 #define DSI_ISR0_AE1_Msk (0x1U << DSI_ISR0_AE1_Pos) 19689 #define DSI_ISR0_AE1 DSI_ISR0_AE1_Msk 19690 #define DSI_ISR0_AE2_Pos (2U) 19691 #define DSI_ISR0_AE2_Msk (0x1U << DSI_ISR0_AE2_Pos) 19692 #define DSI_ISR0_AE2 DSI_ISR0_AE2_Msk 19693 #define DSI_ISR0_AE3_Pos (3U) 19694 #define DSI_ISR0_AE3_Msk (0x1U << DSI_ISR0_AE3_Pos) 19695 #define DSI_ISR0_AE3 DSI_ISR0_AE3_Msk 19696 #define DSI_ISR0_AE4_Pos (4U) 19697 #define DSI_ISR0_AE4_Msk (0x1U << DSI_ISR0_AE4_Pos) 19698 #define DSI_ISR0_AE4 DSI_ISR0_AE4_Msk 19699 #define DSI_ISR0_AE5_Pos (5U) 19700 #define DSI_ISR0_AE5_Msk (0x1U << DSI_ISR0_AE5_Pos) 19701 #define DSI_ISR0_AE5 DSI_ISR0_AE5_Msk 19702 #define DSI_ISR0_AE6_Pos (6U) 19703 #define DSI_ISR0_AE6_Msk (0x1U << DSI_ISR0_AE6_Pos) 19704 #define DSI_ISR0_AE6 DSI_ISR0_AE6_Msk 19705 #define DSI_ISR0_AE7_Pos (7U) 19706 #define DSI_ISR0_AE7_Msk (0x1U << DSI_ISR0_AE7_Pos) 19707 #define DSI_ISR0_AE7 DSI_ISR0_AE7_Msk 19708 #define DSI_ISR0_AE8_Pos (8U) 19709 #define DSI_ISR0_AE8_Msk (0x1U << DSI_ISR0_AE8_Pos) 19710 #define DSI_ISR0_AE8 DSI_ISR0_AE8_Msk 19711 #define DSI_ISR0_AE9_Pos (9U) 19712 #define DSI_ISR0_AE9_Msk (0x1U << DSI_ISR0_AE9_Pos) 19713 #define DSI_ISR0_AE9 DSI_ISR0_AE9_Msk 19714 #define DSI_ISR0_AE10_Pos (10U) 19715 #define DSI_ISR0_AE10_Msk (0x1U << DSI_ISR0_AE10_Pos) 19716 #define DSI_ISR0_AE10 DSI_ISR0_AE10_Msk 19717 #define DSI_ISR0_AE11_Pos (11U) 19718 #define DSI_ISR0_AE11_Msk (0x1U << DSI_ISR0_AE11_Pos) 19719 #define DSI_ISR0_AE11 DSI_ISR0_AE11_Msk 19720 #define DSI_ISR0_AE12_Pos (12U) 19721 #define DSI_ISR0_AE12_Msk (0x1U << DSI_ISR0_AE12_Pos) 19722 #define DSI_ISR0_AE12 DSI_ISR0_AE12_Msk 19723 #define DSI_ISR0_AE13_Pos (13U) 19724 #define DSI_ISR0_AE13_Msk (0x1U << DSI_ISR0_AE13_Pos) 19725 #define DSI_ISR0_AE13 DSI_ISR0_AE13_Msk 19726 #define DSI_ISR0_AE14_Pos (14U) 19727 #define DSI_ISR0_AE14_Msk (0x1U << DSI_ISR0_AE14_Pos) 19728 #define DSI_ISR0_AE14 DSI_ISR0_AE14_Msk 19729 #define DSI_ISR0_AE15_Pos (15U) 19730 #define DSI_ISR0_AE15_Msk (0x1U << DSI_ISR0_AE15_Pos) 19731 #define DSI_ISR0_AE15 DSI_ISR0_AE15_Msk 19732 #define DSI_ISR0_PE0_Pos (16U) 19733 #define DSI_ISR0_PE0_Msk (0x1U << DSI_ISR0_PE0_Pos) 19734 #define DSI_ISR0_PE0 DSI_ISR0_PE0_Msk 19735 #define DSI_ISR0_PE1_Pos (17U) 19736 #define DSI_ISR0_PE1_Msk (0x1U << DSI_ISR0_PE1_Pos) 19737 #define DSI_ISR0_PE1 DSI_ISR0_PE1_Msk 19738 #define DSI_ISR0_PE2_Pos (18U) 19739 #define DSI_ISR0_PE2_Msk (0x1U << DSI_ISR0_PE2_Pos) 19740 #define DSI_ISR0_PE2 DSI_ISR0_PE2_Msk 19741 #define DSI_ISR0_PE3_Pos (19U) 19742 #define DSI_ISR0_PE3_Msk (0x1U << DSI_ISR0_PE3_Pos) 19743 #define DSI_ISR0_PE3 DSI_ISR0_PE3_Msk 19744 #define DSI_ISR0_PE4_Pos (20U) 19745 #define DSI_ISR0_PE4_Msk (0x1U << DSI_ISR0_PE4_Pos) 19746 #define DSI_ISR0_PE4 DSI_ISR0_PE4_Msk 19749 #define DSI_ISR1_TOHSTX_Pos (0U) 19750 #define DSI_ISR1_TOHSTX_Msk (0x1U << DSI_ISR1_TOHSTX_Pos) 19751 #define DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk 19752 #define DSI_ISR1_TOLPRX_Pos (1U) 19753 #define DSI_ISR1_TOLPRX_Msk (0x1U << DSI_ISR1_TOLPRX_Pos) 19754 #define DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk 19755 #define DSI_ISR1_ECCSE_Pos (2U) 19756 #define DSI_ISR1_ECCSE_Msk (0x1U << DSI_ISR1_ECCSE_Pos) 19757 #define DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk 19758 #define DSI_ISR1_ECCME_Pos (3U) 19759 #define DSI_ISR1_ECCME_Msk (0x1U << DSI_ISR1_ECCME_Pos) 19760 #define DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk 19761 #define DSI_ISR1_CRCE_Pos (4U) 19762 #define DSI_ISR1_CRCE_Msk (0x1U << DSI_ISR1_CRCE_Pos) 19763 #define DSI_ISR1_CRCE DSI_ISR1_CRCE_Msk 19764 #define DSI_ISR1_PSE_Pos (5U) 19765 #define DSI_ISR1_PSE_Msk (0x1U << DSI_ISR1_PSE_Pos) 19766 #define DSI_ISR1_PSE DSI_ISR1_PSE_Msk 19767 #define DSI_ISR1_EOTPE_Pos (6U) 19768 #define DSI_ISR1_EOTPE_Msk (0x1U << DSI_ISR1_EOTPE_Pos) 19769 #define DSI_ISR1_EOTPE DSI_ISR1_EOTPE_Msk 19770 #define DSI_ISR1_LPWRE_Pos (7U) 19771 #define DSI_ISR1_LPWRE_Msk (0x1U << DSI_ISR1_LPWRE_Pos) 19772 #define DSI_ISR1_LPWRE DSI_ISR1_LPWRE_Msk 19773 #define DSI_ISR1_GCWRE_Pos (8U) 19774 #define DSI_ISR1_GCWRE_Msk (0x1U << DSI_ISR1_GCWRE_Pos) 19775 #define DSI_ISR1_GCWRE DSI_ISR1_GCWRE_Msk 19776 #define DSI_ISR1_GPWRE_Pos (9U) 19777 #define DSI_ISR1_GPWRE_Msk (0x1U << DSI_ISR1_GPWRE_Pos) 19778 #define DSI_ISR1_GPWRE DSI_ISR1_GPWRE_Msk 19779 #define DSI_ISR1_GPTXE_Pos (10U) 19780 #define DSI_ISR1_GPTXE_Msk (0x1U << DSI_ISR1_GPTXE_Pos) 19781 #define DSI_ISR1_GPTXE DSI_ISR1_GPTXE_Msk 19782 #define DSI_ISR1_GPRDE_Pos (11U) 19783 #define DSI_ISR1_GPRDE_Msk (0x1U << DSI_ISR1_GPRDE_Pos) 19784 #define DSI_ISR1_GPRDE DSI_ISR1_GPRDE_Msk 19785 #define DSI_ISR1_GPRXE_Pos (12U) 19786 #define DSI_ISR1_GPRXE_Msk (0x1U << DSI_ISR1_GPRXE_Pos) 19787 #define DSI_ISR1_GPRXE DSI_ISR1_GPRXE_Msk 19790 #define DSI_IER0_AE0IE_Pos (0U) 19791 #define DSI_IER0_AE0IE_Msk (0x1U << DSI_IER0_AE0IE_Pos) 19792 #define DSI_IER0_AE0IE DSI_IER0_AE0IE_Msk 19793 #define DSI_IER0_AE1IE_Pos (1U) 19794 #define DSI_IER0_AE1IE_Msk (0x1U << DSI_IER0_AE1IE_Pos) 19795 #define DSI_IER0_AE1IE DSI_IER0_AE1IE_Msk 19796 #define DSI_IER0_AE2IE_Pos (2U) 19797 #define DSI_IER0_AE2IE_Msk (0x1U << DSI_IER0_AE2IE_Pos) 19798 #define DSI_IER0_AE2IE DSI_IER0_AE2IE_Msk 19799 #define DSI_IER0_AE3IE_Pos (3U) 19800 #define DSI_IER0_AE3IE_Msk (0x1U << DSI_IER0_AE3IE_Pos) 19801 #define DSI_IER0_AE3IE DSI_IER0_AE3IE_Msk 19802 #define DSI_IER0_AE4IE_Pos (4U) 19803 #define DSI_IER0_AE4IE_Msk (0x1U << DSI_IER0_AE4IE_Pos) 19804 #define DSI_IER0_AE4IE DSI_IER0_AE4IE_Msk 19805 #define DSI_IER0_AE5IE_Pos (5U) 19806 #define DSI_IER0_AE5IE_Msk (0x1U << DSI_IER0_AE5IE_Pos) 19807 #define DSI_IER0_AE5IE DSI_IER0_AE5IE_Msk 19808 #define DSI_IER0_AE6IE_Pos (6U) 19809 #define DSI_IER0_AE6IE_Msk (0x1U << DSI_IER0_AE6IE_Pos) 19810 #define DSI_IER0_AE6IE DSI_IER0_AE6IE_Msk 19811 #define DSI_IER0_AE7IE_Pos (7U) 19812 #define DSI_IER0_AE7IE_Msk (0x1U << DSI_IER0_AE7IE_Pos) 19813 #define DSI_IER0_AE7IE DSI_IER0_AE7IE_Msk 19814 #define DSI_IER0_AE8IE_Pos (8U) 19815 #define DSI_IER0_AE8IE_Msk (0x1U << DSI_IER0_AE8IE_Pos) 19816 #define DSI_IER0_AE8IE DSI_IER0_AE8IE_Msk 19817 #define DSI_IER0_AE9IE_Pos (9U) 19818 #define DSI_IER0_AE9IE_Msk (0x1U << DSI_IER0_AE9IE_Pos) 19819 #define DSI_IER0_AE9IE DSI_IER0_AE9IE_Msk 19820 #define DSI_IER0_AE10IE_Pos (10U) 19821 #define DSI_IER0_AE10IE_Msk (0x1U << DSI_IER0_AE10IE_Pos) 19822 #define DSI_IER0_AE10IE DSI_IER0_AE10IE_Msk 19823 #define DSI_IER0_AE11IE_Pos (11U) 19824 #define DSI_IER0_AE11IE_Msk (0x1U << DSI_IER0_AE11IE_Pos) 19825 #define DSI_IER0_AE11IE DSI_IER0_AE11IE_Msk 19826 #define DSI_IER0_AE12IE_Pos (12U) 19827 #define DSI_IER0_AE12IE_Msk (0x1U << DSI_IER0_AE12IE_Pos) 19828 #define DSI_IER0_AE12IE DSI_IER0_AE12IE_Msk 19829 #define DSI_IER0_AE13IE_Pos (13U) 19830 #define DSI_IER0_AE13IE_Msk (0x1U << DSI_IER0_AE13IE_Pos) 19831 #define DSI_IER0_AE13IE DSI_IER0_AE13IE_Msk 19832 #define DSI_IER0_AE14IE_Pos (14U) 19833 #define DSI_IER0_AE14IE_Msk (0x1U << DSI_IER0_AE14IE_Pos) 19834 #define DSI_IER0_AE14IE DSI_IER0_AE14IE_Msk 19835 #define DSI_IER0_AE15IE_Pos (15U) 19836 #define DSI_IER0_AE15IE_Msk (0x1U << DSI_IER0_AE15IE_Pos) 19837 #define DSI_IER0_AE15IE DSI_IER0_AE15IE_Msk 19838 #define DSI_IER0_PE0IE_Pos (16U) 19839 #define DSI_IER0_PE0IE_Msk (0x1U << DSI_IER0_PE0IE_Pos) 19840 #define DSI_IER0_PE0IE DSI_IER0_PE0IE_Msk 19841 #define DSI_IER0_PE1IE_Pos (17U) 19842 #define DSI_IER0_PE1IE_Msk (0x1U << DSI_IER0_PE1IE_Pos) 19843 #define DSI_IER0_PE1IE DSI_IER0_PE1IE_Msk 19844 #define DSI_IER0_PE2IE_Pos (18U) 19845 #define DSI_IER0_PE2IE_Msk (0x1U << DSI_IER0_PE2IE_Pos) 19846 #define DSI_IER0_PE2IE DSI_IER0_PE2IE_Msk 19847 #define DSI_IER0_PE3IE_Pos (19U) 19848 #define DSI_IER0_PE3IE_Msk (0x1U << DSI_IER0_PE3IE_Pos) 19849 #define DSI_IER0_PE3IE DSI_IER0_PE3IE_Msk 19850 #define DSI_IER0_PE4IE_Pos (20U) 19851 #define DSI_IER0_PE4IE_Msk (0x1U << DSI_IER0_PE4IE_Pos) 19852 #define DSI_IER0_PE4IE DSI_IER0_PE4IE_Msk 19855 #define DSI_IER1_TOHSTXIE_Pos (0U) 19856 #define DSI_IER1_TOHSTXIE_Msk (0x1U << DSI_IER1_TOHSTXIE_Pos) 19857 #define DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk 19858 #define DSI_IER1_TOLPRXIE_Pos (1U) 19859 #define DSI_IER1_TOLPRXIE_Msk (0x1U << DSI_IER1_TOLPRXIE_Pos) 19860 #define DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk 19861 #define DSI_IER1_ECCSEIE_Pos (2U) 19862 #define DSI_IER1_ECCSEIE_Msk (0x1U << DSI_IER1_ECCSEIE_Pos) 19863 #define DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk 19864 #define DSI_IER1_ECCMEIE_Pos (3U) 19865 #define DSI_IER1_ECCMEIE_Msk (0x1U << DSI_IER1_ECCMEIE_Pos) 19866 #define DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk 19867 #define DSI_IER1_CRCEIE_Pos (4U) 19868 #define DSI_IER1_CRCEIE_Msk (0x1U << DSI_IER1_CRCEIE_Pos) 19869 #define DSI_IER1_CRCEIE DSI_IER1_CRCEIE_Msk 19870 #define DSI_IER1_PSEIE_Pos (5U) 19871 #define DSI_IER1_PSEIE_Msk (0x1U << DSI_IER1_PSEIE_Pos) 19872 #define DSI_IER1_PSEIE DSI_IER1_PSEIE_Msk 19873 #define DSI_IER1_EOTPEIE_Pos (6U) 19874 #define DSI_IER1_EOTPEIE_Msk (0x1U << DSI_IER1_EOTPEIE_Pos) 19875 #define DSI_IER1_EOTPEIE DSI_IER1_EOTPEIE_Msk 19876 #define DSI_IER1_LPWREIE_Pos (7U) 19877 #define DSI_IER1_LPWREIE_Msk (0x1U << DSI_IER1_LPWREIE_Pos) 19878 #define DSI_IER1_LPWREIE DSI_IER1_LPWREIE_Msk 19879 #define DSI_IER1_GCWREIE_Pos (8U) 19880 #define DSI_IER1_GCWREIE_Msk (0x1U << DSI_IER1_GCWREIE_Pos) 19881 #define DSI_IER1_GCWREIE DSI_IER1_GCWREIE_Msk 19882 #define DSI_IER1_GPWREIE_Pos (9U) 19883 #define DSI_IER1_GPWREIE_Msk (0x1U << DSI_IER1_GPWREIE_Pos) 19884 #define DSI_IER1_GPWREIE DSI_IER1_GPWREIE_Msk 19885 #define DSI_IER1_GPTXEIE_Pos (10U) 19886 #define DSI_IER1_GPTXEIE_Msk (0x1U << DSI_IER1_GPTXEIE_Pos) 19887 #define DSI_IER1_GPTXEIE DSI_IER1_GPTXEIE_Msk 19888 #define DSI_IER1_GPRDEIE_Pos (11U) 19889 #define DSI_IER1_GPRDEIE_Msk (0x1U << DSI_IER1_GPRDEIE_Pos) 19890 #define DSI_IER1_GPRDEIE DSI_IER1_GPRDEIE_Msk 19891 #define DSI_IER1_GPRXEIE_Pos (12U) 19892 #define DSI_IER1_GPRXEIE_Msk (0x1U << DSI_IER1_GPRXEIE_Pos) 19893 #define DSI_IER1_GPRXEIE DSI_IER1_GPRXEIE_Msk 19896 #define DSI_FIR0_FAE0_Pos (0U) 19897 #define DSI_FIR0_FAE0_Msk (0x1U << DSI_FIR0_FAE0_Pos) 19898 #define DSI_FIR0_FAE0 DSI_FIR0_FAE0_Msk 19899 #define DSI_FIR0_FAE1_Pos (1U) 19900 #define DSI_FIR0_FAE1_Msk (0x1U << DSI_FIR0_FAE1_Pos) 19901 #define DSI_FIR0_FAE1 DSI_FIR0_FAE1_Msk 19902 #define DSI_FIR0_FAE2_Pos (2U) 19903 #define DSI_FIR0_FAE2_Msk (0x1U << DSI_FIR0_FAE2_Pos) 19904 #define DSI_FIR0_FAE2 DSI_FIR0_FAE2_Msk 19905 #define DSI_FIR0_FAE3_Pos (3U) 19906 #define DSI_FIR0_FAE3_Msk (0x1U << DSI_FIR0_FAE3_Pos) 19907 #define DSI_FIR0_FAE3 DSI_FIR0_FAE3_Msk 19908 #define DSI_FIR0_FAE4_Pos (4U) 19909 #define DSI_FIR0_FAE4_Msk (0x1U << DSI_FIR0_FAE4_Pos) 19910 #define DSI_FIR0_FAE4 DSI_FIR0_FAE4_Msk 19911 #define DSI_FIR0_FAE5_Pos (5U) 19912 #define DSI_FIR0_FAE5_Msk (0x1U << DSI_FIR0_FAE5_Pos) 19913 #define DSI_FIR0_FAE5 DSI_FIR0_FAE5_Msk 19914 #define DSI_FIR0_FAE6_Pos (6U) 19915 #define DSI_FIR0_FAE6_Msk (0x1U << DSI_FIR0_FAE6_Pos) 19916 #define DSI_FIR0_FAE6 DSI_FIR0_FAE6_Msk 19917 #define DSI_FIR0_FAE7_Pos (7U) 19918 #define DSI_FIR0_FAE7_Msk (0x1U << DSI_FIR0_FAE7_Pos) 19919 #define DSI_FIR0_FAE7 DSI_FIR0_FAE7_Msk 19920 #define DSI_FIR0_FAE8_Pos (8U) 19921 #define DSI_FIR0_FAE8_Msk (0x1U << DSI_FIR0_FAE8_Pos) 19922 #define DSI_FIR0_FAE8 DSI_FIR0_FAE8_Msk 19923 #define DSI_FIR0_FAE9_Pos (9U) 19924 #define DSI_FIR0_FAE9_Msk (0x1U << DSI_FIR0_FAE9_Pos) 19925 #define DSI_FIR0_FAE9 DSI_FIR0_FAE9_Msk 19926 #define DSI_FIR0_FAE10_Pos (10U) 19927 #define DSI_FIR0_FAE10_Msk (0x1U << DSI_FIR0_FAE10_Pos) 19928 #define DSI_FIR0_FAE10 DSI_FIR0_FAE10_Msk 19929 #define DSI_FIR0_FAE11_Pos (11U) 19930 #define DSI_FIR0_FAE11_Msk (0x1U << DSI_FIR0_FAE11_Pos) 19931 #define DSI_FIR0_FAE11 DSI_FIR0_FAE11_Msk 19932 #define DSI_FIR0_FAE12_Pos (12U) 19933 #define DSI_FIR0_FAE12_Msk (0x1U << DSI_FIR0_FAE12_Pos) 19934 #define DSI_FIR0_FAE12 DSI_FIR0_FAE12_Msk 19935 #define DSI_FIR0_FAE13_Pos (13U) 19936 #define DSI_FIR0_FAE13_Msk (0x1U << DSI_FIR0_FAE13_Pos) 19937 #define DSI_FIR0_FAE13 DSI_FIR0_FAE13_Msk 19938 #define DSI_FIR0_FAE14_Pos (14U) 19939 #define DSI_FIR0_FAE14_Msk (0x1U << DSI_FIR0_FAE14_Pos) 19940 #define DSI_FIR0_FAE14 DSI_FIR0_FAE14_Msk 19941 #define DSI_FIR0_FAE15_Pos (15U) 19942 #define DSI_FIR0_FAE15_Msk (0x1U << DSI_FIR0_FAE15_Pos) 19943 #define DSI_FIR0_FAE15 DSI_FIR0_FAE15_Msk 19944 #define DSI_FIR0_FPE0_Pos (16U) 19945 #define DSI_FIR0_FPE0_Msk (0x1U << DSI_FIR0_FPE0_Pos) 19946 #define DSI_FIR0_FPE0 DSI_FIR0_FPE0_Msk 19947 #define DSI_FIR0_FPE1_Pos (17U) 19948 #define DSI_FIR0_FPE1_Msk (0x1U << DSI_FIR0_FPE1_Pos) 19949 #define DSI_FIR0_FPE1 DSI_FIR0_FPE1_Msk 19950 #define DSI_FIR0_FPE2_Pos (18U) 19951 #define DSI_FIR0_FPE2_Msk (0x1U << DSI_FIR0_FPE2_Pos) 19952 #define DSI_FIR0_FPE2 DSI_FIR0_FPE2_Msk 19953 #define DSI_FIR0_FPE3_Pos (19U) 19954 #define DSI_FIR0_FPE3_Msk (0x1U << DSI_FIR0_FPE3_Pos) 19955 #define DSI_FIR0_FPE3 DSI_FIR0_FPE3_Msk 19956 #define DSI_FIR0_FPE4_Pos (20U) 19957 #define DSI_FIR0_FPE4_Msk (0x1U << DSI_FIR0_FPE4_Pos) 19958 #define DSI_FIR0_FPE4 DSI_FIR0_FPE4_Msk 19961 #define DSI_FIR1_FTOHSTX_Pos (0U) 19962 #define DSI_FIR1_FTOHSTX_Msk (0x1U << DSI_FIR1_FTOHSTX_Pos) 19963 #define DSI_FIR1_FTOHSTX DSI_FIR1_FTOHSTX_Msk 19964 #define DSI_FIR1_FTOLPRX_Pos (1U) 19965 #define DSI_FIR1_FTOLPRX_Msk (0x1U << DSI_FIR1_FTOLPRX_Pos) 19966 #define DSI_FIR1_FTOLPRX DSI_FIR1_FTOLPRX_Msk 19967 #define DSI_FIR1_FECCSE_Pos (2U) 19968 #define DSI_FIR1_FECCSE_Msk (0x1U << DSI_FIR1_FECCSE_Pos) 19969 #define DSI_FIR1_FECCSE DSI_FIR1_FECCSE_Msk 19970 #define DSI_FIR1_FECCME_Pos (3U) 19971 #define DSI_FIR1_FECCME_Msk (0x1U << DSI_FIR1_FECCME_Pos) 19972 #define DSI_FIR1_FECCME DSI_FIR1_FECCME_Msk 19973 #define DSI_FIR1_FCRCE_Pos (4U) 19974 #define DSI_FIR1_FCRCE_Msk (0x1U << DSI_FIR1_FCRCE_Pos) 19975 #define DSI_FIR1_FCRCE DSI_FIR1_FCRCE_Msk 19976 #define DSI_FIR1_FPSE_Pos (5U) 19977 #define DSI_FIR1_FPSE_Msk (0x1U << DSI_FIR1_FPSE_Pos) 19978 #define DSI_FIR1_FPSE DSI_FIR1_FPSE_Msk 19979 #define DSI_FIR1_FEOTPE_Pos (6U) 19980 #define DSI_FIR1_FEOTPE_Msk (0x1U << DSI_FIR1_FEOTPE_Pos) 19981 #define DSI_FIR1_FEOTPE DSI_FIR1_FEOTPE_Msk 19982 #define DSI_FIR1_FLPWRE_Pos (7U) 19983 #define DSI_FIR1_FLPWRE_Msk (0x1U << DSI_FIR1_FLPWRE_Pos) 19984 #define DSI_FIR1_FLPWRE DSI_FIR1_FLPWRE_Msk 19985 #define DSI_FIR1_FGCWRE_Pos (8U) 19986 #define DSI_FIR1_FGCWRE_Msk (0x1U << DSI_FIR1_FGCWRE_Pos) 19987 #define DSI_FIR1_FGCWRE DSI_FIR1_FGCWRE_Msk 19988 #define DSI_FIR1_FGPWRE_Pos (9U) 19989 #define DSI_FIR1_FGPWRE_Msk (0x1U << DSI_FIR1_FGPWRE_Pos) 19990 #define DSI_FIR1_FGPWRE DSI_FIR1_FGPWRE_Msk 19991 #define DSI_FIR1_FGPTXE_Pos (10U) 19992 #define DSI_FIR1_FGPTXE_Msk (0x1U << DSI_FIR1_FGPTXE_Pos) 19993 #define DSI_FIR1_FGPTXE DSI_FIR1_FGPTXE_Msk 19994 #define DSI_FIR1_FGPRDE_Pos (11U) 19995 #define DSI_FIR1_FGPRDE_Msk (0x1U << DSI_FIR1_FGPRDE_Pos) 19996 #define DSI_FIR1_FGPRDE DSI_FIR1_FGPRDE_Msk 19997 #define DSI_FIR1_FGPRXE_Pos (12U) 19998 #define DSI_FIR1_FGPRXE_Msk (0x1U << DSI_FIR1_FGPRXE_Pos) 19999 #define DSI_FIR1_FGPRXE DSI_FIR1_FGPRXE_Msk 20002 #define DSI_VSCR_EN_Pos (0U) 20003 #define DSI_VSCR_EN_Msk (0x1U << DSI_VSCR_EN_Pos) 20004 #define DSI_VSCR_EN DSI_VSCR_EN_Msk 20005 #define DSI_VSCR_UR_Pos (8U) 20006 #define DSI_VSCR_UR_Msk (0x1U << DSI_VSCR_UR_Pos) 20007 #define DSI_VSCR_UR DSI_VSCR_UR_Msk 20010 #define DSI_LCVCIDR_VCID_Pos (0U) 20011 #define DSI_LCVCIDR_VCID_Msk (0x3U << DSI_LCVCIDR_VCID_Pos) 20012 #define DSI_LCVCIDR_VCID DSI_LCVCIDR_VCID_Msk 20013 #define DSI_LCVCIDR_VCID0_Pos (0U) 20014 #define DSI_LCVCIDR_VCID0_Msk (0x1U << DSI_LCVCIDR_VCID0_Pos) 20015 #define DSI_LCVCIDR_VCID0 DSI_LCVCIDR_VCID0_Msk 20016 #define DSI_LCVCIDR_VCID1_Pos (1U) 20017 #define DSI_LCVCIDR_VCID1_Msk (0x1U << DSI_LCVCIDR_VCID1_Pos) 20018 #define DSI_LCVCIDR_VCID1 DSI_LCVCIDR_VCID1_Msk 20021 #define DSI_LCCCR_COLC_Pos (0U) 20022 #define DSI_LCCCR_COLC_Msk (0xFU << DSI_LCCCR_COLC_Pos) 20023 #define DSI_LCCCR_COLC DSI_LCCCR_COLC_Msk 20024 #define DSI_LCCCR_COLC0_Pos (0U) 20025 #define DSI_LCCCR_COLC0_Msk (0x1U << DSI_LCCCR_COLC0_Pos) 20026 #define DSI_LCCCR_COLC0 DSI_LCCCR_COLC0_Msk 20027 #define DSI_LCCCR_COLC1_Pos (1U) 20028 #define DSI_LCCCR_COLC1_Msk (0x1U << DSI_LCCCR_COLC1_Pos) 20029 #define DSI_LCCCR_COLC1 DSI_LCCCR_COLC1_Msk 20030 #define DSI_LCCCR_COLC2_Pos (2U) 20031 #define DSI_LCCCR_COLC2_Msk (0x1U << DSI_LCCCR_COLC2_Pos) 20032 #define DSI_LCCCR_COLC2 DSI_LCCCR_COLC2_Msk 20033 #define DSI_LCCCR_COLC3_Pos (3U) 20034 #define DSI_LCCCR_COLC3_Msk (0x1U << DSI_LCCCR_COLC3_Pos) 20035 #define DSI_LCCCR_COLC3 DSI_LCCCR_COLC3_Msk 20037 #define DSI_LCCCR_LPE_Pos (8U) 20038 #define DSI_LCCCR_LPE_Msk (0x1U << DSI_LCCCR_LPE_Pos) 20039 #define DSI_LCCCR_LPE DSI_LCCCR_LPE_Msk 20042 #define DSI_LPMCCR_VLPSIZE_Pos (0U) 20043 #define DSI_LPMCCR_VLPSIZE_Msk (0xFFU << DSI_LPMCCR_VLPSIZE_Pos) 20044 #define DSI_LPMCCR_VLPSIZE DSI_LPMCCR_VLPSIZE_Msk 20045 #define DSI_LPMCCR_VLPSIZE0_Pos (0U) 20046 #define DSI_LPMCCR_VLPSIZE0_Msk (0x1U << DSI_LPMCCR_VLPSIZE0_Pos) 20047 #define DSI_LPMCCR_VLPSIZE0 DSI_LPMCCR_VLPSIZE0_Msk 20048 #define DSI_LPMCCR_VLPSIZE1_Pos (1U) 20049 #define DSI_LPMCCR_VLPSIZE1_Msk (0x1U << DSI_LPMCCR_VLPSIZE1_Pos) 20050 #define DSI_LPMCCR_VLPSIZE1 DSI_LPMCCR_VLPSIZE1_Msk 20051 #define DSI_LPMCCR_VLPSIZE2_Pos (2U) 20052 #define DSI_LPMCCR_VLPSIZE2_Msk (0x1U << DSI_LPMCCR_VLPSIZE2_Pos) 20053 #define DSI_LPMCCR_VLPSIZE2 DSI_LPMCCR_VLPSIZE2_Msk 20054 #define DSI_LPMCCR_VLPSIZE3_Pos (3U) 20055 #define DSI_LPMCCR_VLPSIZE3_Msk (0x1U << DSI_LPMCCR_VLPSIZE3_Pos) 20056 #define DSI_LPMCCR_VLPSIZE3 DSI_LPMCCR_VLPSIZE3_Msk 20057 #define DSI_LPMCCR_VLPSIZE4_Pos (4U) 20058 #define DSI_LPMCCR_VLPSIZE4_Msk (0x1U << DSI_LPMCCR_VLPSIZE4_Pos) 20059 #define DSI_LPMCCR_VLPSIZE4 DSI_LPMCCR_VLPSIZE4_Msk 20060 #define DSI_LPMCCR_VLPSIZE5_Pos (5U) 20061 #define DSI_LPMCCR_VLPSIZE5_Msk (0x1U << DSI_LPMCCR_VLPSIZE5_Pos) 20062 #define DSI_LPMCCR_VLPSIZE5 DSI_LPMCCR_VLPSIZE5_Msk 20063 #define DSI_LPMCCR_VLPSIZE6_Pos (6U) 20064 #define DSI_LPMCCR_VLPSIZE6_Msk (0x1U << DSI_LPMCCR_VLPSIZE6_Pos) 20065 #define DSI_LPMCCR_VLPSIZE6 DSI_LPMCCR_VLPSIZE6_Msk 20066 #define DSI_LPMCCR_VLPSIZE7_Pos (7U) 20067 #define DSI_LPMCCR_VLPSIZE7_Msk (0x1U << DSI_LPMCCR_VLPSIZE7_Pos) 20068 #define DSI_LPMCCR_VLPSIZE7 DSI_LPMCCR_VLPSIZE7_Msk 20070 #define DSI_LPMCCR_LPSIZE_Pos (16U) 20071 #define DSI_LPMCCR_LPSIZE_Msk (0xFFU << DSI_LPMCCR_LPSIZE_Pos) 20072 #define DSI_LPMCCR_LPSIZE DSI_LPMCCR_LPSIZE_Msk 20073 #define DSI_LPMCCR_LPSIZE0_Pos (16U) 20074 #define DSI_LPMCCR_LPSIZE0_Msk (0x1U << DSI_LPMCCR_LPSIZE0_Pos) 20075 #define DSI_LPMCCR_LPSIZE0 DSI_LPMCCR_LPSIZE0_Msk 20076 #define DSI_LPMCCR_LPSIZE1_Pos (17U) 20077 #define DSI_LPMCCR_LPSIZE1_Msk (0x1U << DSI_LPMCCR_LPSIZE1_Pos) 20078 #define DSI_LPMCCR_LPSIZE1 DSI_LPMCCR_LPSIZE1_Msk 20079 #define DSI_LPMCCR_LPSIZE2_Pos (18U) 20080 #define DSI_LPMCCR_LPSIZE2_Msk (0x1U << DSI_LPMCCR_LPSIZE2_Pos) 20081 #define DSI_LPMCCR_LPSIZE2 DSI_LPMCCR_LPSIZE2_Msk 20082 #define DSI_LPMCCR_LPSIZE3_Pos (19U) 20083 #define DSI_LPMCCR_LPSIZE3_Msk (0x1U << DSI_LPMCCR_LPSIZE3_Pos) 20084 #define DSI_LPMCCR_LPSIZE3 DSI_LPMCCR_LPSIZE3_Msk 20085 #define DSI_LPMCCR_LPSIZE4_Pos (20U) 20086 #define DSI_LPMCCR_LPSIZE4_Msk (0x1U << DSI_LPMCCR_LPSIZE4_Pos) 20087 #define DSI_LPMCCR_LPSIZE4 DSI_LPMCCR_LPSIZE4_Msk 20088 #define DSI_LPMCCR_LPSIZE5_Pos (21U) 20089 #define DSI_LPMCCR_LPSIZE5_Msk (0x1U << DSI_LPMCCR_LPSIZE5_Pos) 20090 #define DSI_LPMCCR_LPSIZE5 DSI_LPMCCR_LPSIZE5_Msk 20091 #define DSI_LPMCCR_LPSIZE6_Pos (22U) 20092 #define DSI_LPMCCR_LPSIZE6_Msk (0x1U << DSI_LPMCCR_LPSIZE6_Pos) 20093 #define DSI_LPMCCR_LPSIZE6 DSI_LPMCCR_LPSIZE6_Msk 20094 #define DSI_LPMCCR_LPSIZE7_Pos (23U) 20095 #define DSI_LPMCCR_LPSIZE7_Msk (0x1U << DSI_LPMCCR_LPSIZE7_Pos) 20096 #define DSI_LPMCCR_LPSIZE7 DSI_LPMCCR_LPSIZE7_Msk 20099 #define DSI_VMCCR_VMT_Pos (0U) 20100 #define DSI_VMCCR_VMT_Msk (0x3U << DSI_VMCCR_VMT_Pos) 20101 #define DSI_VMCCR_VMT DSI_VMCCR_VMT_Msk 20102 #define DSI_VMCCR_VMT0_Pos (0U) 20103 #define DSI_VMCCR_VMT0_Msk (0x1U << DSI_VMCCR_VMT0_Pos) 20104 #define DSI_VMCCR_VMT0 DSI_VMCCR_VMT0_Msk 20105 #define DSI_VMCCR_VMT1_Pos (1U) 20106 #define DSI_VMCCR_VMT1_Msk (0x1U << DSI_VMCCR_VMT1_Pos) 20107 #define DSI_VMCCR_VMT1 DSI_VMCCR_VMT1_Msk 20109 #define DSI_VMCCR_LPVSAE_Pos (8U) 20110 #define DSI_VMCCR_LPVSAE_Msk (0x1U << DSI_VMCCR_LPVSAE_Pos) 20111 #define DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk 20112 #define DSI_VMCCR_LPVBPE_Pos (9U) 20113 #define DSI_VMCCR_LPVBPE_Msk (0x1U << DSI_VMCCR_LPVBPE_Pos) 20114 #define DSI_VMCCR_LPVBPE DSI_VMCCR_LPVBPE_Msk 20115 #define DSI_VMCCR_LPVFPE_Pos (10U) 20116 #define DSI_VMCCR_LPVFPE_Msk (0x1U << DSI_VMCCR_LPVFPE_Pos) 20117 #define DSI_VMCCR_LPVFPE DSI_VMCCR_LPVFPE_Msk 20118 #define DSI_VMCCR_LPVAE_Pos (11U) 20119 #define DSI_VMCCR_LPVAE_Msk (0x1U << DSI_VMCCR_LPVAE_Pos) 20120 #define DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk 20121 #define DSI_VMCCR_LPHBPE_Pos (12U) 20122 #define DSI_VMCCR_LPHBPE_Msk (0x1U << DSI_VMCCR_LPHBPE_Pos) 20123 #define DSI_VMCCR_LPHBPE DSI_VMCCR_LPHBPE_Msk 20124 #define DSI_VMCCR_LPHFE_Pos (13U) 20125 #define DSI_VMCCR_LPHFE_Msk (0x1U << DSI_VMCCR_LPHFE_Pos) 20126 #define DSI_VMCCR_LPHFE DSI_VMCCR_LPHFE_Msk 20127 #define DSI_VMCCR_FBTAAE_Pos (14U) 20128 #define DSI_VMCCR_FBTAAE_Msk (0x1U << DSI_VMCCR_FBTAAE_Pos) 20129 #define DSI_VMCCR_FBTAAE DSI_VMCCR_FBTAAE_Msk 20130 #define DSI_VMCCR_LPCE_Pos (15U) 20131 #define DSI_VMCCR_LPCE_Msk (0x1U << DSI_VMCCR_LPCE_Pos) 20132 #define DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk 20135 #define DSI_VPCCR_VPSIZE_Pos (0U) 20136 #define DSI_VPCCR_VPSIZE_Msk (0x3FFFU << DSI_VPCCR_VPSIZE_Pos) 20137 #define DSI_VPCCR_VPSIZE DSI_VPCCR_VPSIZE_Msk 20138 #define DSI_VPCCR_VPSIZE0_Pos (0U) 20139 #define DSI_VPCCR_VPSIZE0_Msk (0x1U << DSI_VPCCR_VPSIZE0_Pos) 20140 #define DSI_VPCCR_VPSIZE0 DSI_VPCCR_VPSIZE0_Msk 20141 #define DSI_VPCCR_VPSIZE1_Pos (1U) 20142 #define DSI_VPCCR_VPSIZE1_Msk (0x1U << DSI_VPCCR_VPSIZE1_Pos) 20143 #define DSI_VPCCR_VPSIZE1 DSI_VPCCR_VPSIZE1_Msk 20144 #define DSI_VPCCR_VPSIZE2_Pos (2U) 20145 #define DSI_VPCCR_VPSIZE2_Msk (0x1U << DSI_VPCCR_VPSIZE2_Pos) 20146 #define DSI_VPCCR_VPSIZE2 DSI_VPCCR_VPSIZE2_Msk 20147 #define DSI_VPCCR_VPSIZE3_Pos (3U) 20148 #define DSI_VPCCR_VPSIZE3_Msk (0x1U << DSI_VPCCR_VPSIZE3_Pos) 20149 #define DSI_VPCCR_VPSIZE3 DSI_VPCCR_VPSIZE3_Msk 20150 #define DSI_VPCCR_VPSIZE4_Pos (4U) 20151 #define DSI_VPCCR_VPSIZE4_Msk (0x1U << DSI_VPCCR_VPSIZE4_Pos) 20152 #define DSI_VPCCR_VPSIZE4 DSI_VPCCR_VPSIZE4_Msk 20153 #define DSI_VPCCR_VPSIZE5_Pos (5U) 20154 #define DSI_VPCCR_VPSIZE5_Msk (0x1U << DSI_VPCCR_VPSIZE5_Pos) 20155 #define DSI_VPCCR_VPSIZE5 DSI_VPCCR_VPSIZE5_Msk 20156 #define DSI_VPCCR_VPSIZE6_Pos (6U) 20157 #define DSI_VPCCR_VPSIZE6_Msk (0x1U << DSI_VPCCR_VPSIZE6_Pos) 20158 #define DSI_VPCCR_VPSIZE6 DSI_VPCCR_VPSIZE6_Msk 20159 #define DSI_VPCCR_VPSIZE7_Pos (7U) 20160 #define DSI_VPCCR_VPSIZE7_Msk (0x1U << DSI_VPCCR_VPSIZE7_Pos) 20161 #define DSI_VPCCR_VPSIZE7 DSI_VPCCR_VPSIZE7_Msk 20162 #define DSI_VPCCR_VPSIZE8_Pos (8U) 20163 #define DSI_VPCCR_VPSIZE8_Msk (0x1U << DSI_VPCCR_VPSIZE8_Pos) 20164 #define DSI_VPCCR_VPSIZE8 DSI_VPCCR_VPSIZE8_Msk 20165 #define DSI_VPCCR_VPSIZE9_Pos (9U) 20166 #define DSI_VPCCR_VPSIZE9_Msk (0x1U << DSI_VPCCR_VPSIZE9_Pos) 20167 #define DSI_VPCCR_VPSIZE9 DSI_VPCCR_VPSIZE9_Msk 20168 #define DSI_VPCCR_VPSIZE10_Pos (10U) 20169 #define DSI_VPCCR_VPSIZE10_Msk (0x1U << DSI_VPCCR_VPSIZE10_Pos) 20170 #define DSI_VPCCR_VPSIZE10 DSI_VPCCR_VPSIZE10_Msk 20171 #define DSI_VPCCR_VPSIZE11_Pos (11U) 20172 #define DSI_VPCCR_VPSIZE11_Msk (0x1U << DSI_VPCCR_VPSIZE11_Pos) 20173 #define DSI_VPCCR_VPSIZE11 DSI_VPCCR_VPSIZE11_Msk 20174 #define DSI_VPCCR_VPSIZE12_Pos (12U) 20175 #define DSI_VPCCR_VPSIZE12_Msk (0x1U << DSI_VPCCR_VPSIZE12_Pos) 20176 #define DSI_VPCCR_VPSIZE12 DSI_VPCCR_VPSIZE12_Msk 20177 #define DSI_VPCCR_VPSIZE13_Pos (13U) 20178 #define DSI_VPCCR_VPSIZE13_Msk (0x1U << DSI_VPCCR_VPSIZE13_Pos) 20179 #define DSI_VPCCR_VPSIZE13 DSI_VPCCR_VPSIZE13_Msk 20182 #define DSI_VCCCR_NUMC_Pos (0U) 20183 #define DSI_VCCCR_NUMC_Msk (0x1FFFU << DSI_VCCCR_NUMC_Pos) 20184 #define DSI_VCCCR_NUMC DSI_VCCCR_NUMC_Msk 20185 #define DSI_VCCCR_NUMC0_Pos (0U) 20186 #define DSI_VCCCR_NUMC0_Msk (0x1U << DSI_VCCCR_NUMC0_Pos) 20187 #define DSI_VCCCR_NUMC0 DSI_VCCCR_NUMC0_Msk 20188 #define DSI_VCCCR_NUMC1_Pos (1U) 20189 #define DSI_VCCCR_NUMC1_Msk (0x1U << DSI_VCCCR_NUMC1_Pos) 20190 #define DSI_VCCCR_NUMC1 DSI_VCCCR_NUMC1_Msk 20191 #define DSI_VCCCR_NUMC2_Pos (2U) 20192 #define DSI_VCCCR_NUMC2_Msk (0x1U << DSI_VCCCR_NUMC2_Pos) 20193 #define DSI_VCCCR_NUMC2 DSI_VCCCR_NUMC2_Msk 20194 #define DSI_VCCCR_NUMC3_Pos (3U) 20195 #define DSI_VCCCR_NUMC3_Msk (0x1U << DSI_VCCCR_NUMC3_Pos) 20196 #define DSI_VCCCR_NUMC3 DSI_VCCCR_NUMC3_Msk 20197 #define DSI_VCCCR_NUMC4_Pos (4U) 20198 #define DSI_VCCCR_NUMC4_Msk (0x1U << DSI_VCCCR_NUMC4_Pos) 20199 #define DSI_VCCCR_NUMC4 DSI_VCCCR_NUMC4_Msk 20200 #define DSI_VCCCR_NUMC5_Pos (5U) 20201 #define DSI_VCCCR_NUMC5_Msk (0x1U << DSI_VCCCR_NUMC5_Pos) 20202 #define DSI_VCCCR_NUMC5 DSI_VCCCR_NUMC5_Msk 20203 #define DSI_VCCCR_NUMC6_Pos (6U) 20204 #define DSI_VCCCR_NUMC6_Msk (0x1U << DSI_VCCCR_NUMC6_Pos) 20205 #define DSI_VCCCR_NUMC6 DSI_VCCCR_NUMC6_Msk 20206 #define DSI_VCCCR_NUMC7_Pos (7U) 20207 #define DSI_VCCCR_NUMC7_Msk (0x1U << DSI_VCCCR_NUMC7_Pos) 20208 #define DSI_VCCCR_NUMC7 DSI_VCCCR_NUMC7_Msk 20209 #define DSI_VCCCR_NUMC8_Pos (8U) 20210 #define DSI_VCCCR_NUMC8_Msk (0x1U << DSI_VCCCR_NUMC8_Pos) 20211 #define DSI_VCCCR_NUMC8 DSI_VCCCR_NUMC8_Msk 20212 #define DSI_VCCCR_NUMC9_Pos (9U) 20213 #define DSI_VCCCR_NUMC9_Msk (0x1U << DSI_VCCCR_NUMC9_Pos) 20214 #define DSI_VCCCR_NUMC9 DSI_VCCCR_NUMC9_Msk 20215 #define DSI_VCCCR_NUMC10_Pos (10U) 20216 #define DSI_VCCCR_NUMC10_Msk (0x1U << DSI_VCCCR_NUMC10_Pos) 20217 #define DSI_VCCCR_NUMC10 DSI_VCCCR_NUMC10_Msk 20218 #define DSI_VCCCR_NUMC11_Pos (11U) 20219 #define DSI_VCCCR_NUMC11_Msk (0x1U << DSI_VCCCR_NUMC11_Pos) 20220 #define DSI_VCCCR_NUMC11 DSI_VCCCR_NUMC11_Msk 20221 #define DSI_VCCCR_NUMC12_Pos (12U) 20222 #define DSI_VCCCR_NUMC12_Msk (0x1U << DSI_VCCCR_NUMC12_Pos) 20223 #define DSI_VCCCR_NUMC12 DSI_VCCCR_NUMC12_Msk 20226 #define DSI_VNPCCR_NPSIZE_Pos (0U) 20227 #define DSI_VNPCCR_NPSIZE_Msk (0x1FFFU << DSI_VNPCCR_NPSIZE_Pos) 20228 #define DSI_VNPCCR_NPSIZE DSI_VNPCCR_NPSIZE_Msk 20229 #define DSI_VNPCCR_NPSIZE0_Pos (0U) 20230 #define DSI_VNPCCR_NPSIZE0_Msk (0x1U << DSI_VNPCCR_NPSIZE0_Pos) 20231 #define DSI_VNPCCR_NPSIZE0 DSI_VNPCCR_NPSIZE0_Msk 20232 #define DSI_VNPCCR_NPSIZE1_Pos (1U) 20233 #define DSI_VNPCCR_NPSIZE1_Msk (0x1U << DSI_VNPCCR_NPSIZE1_Pos) 20234 #define DSI_VNPCCR_NPSIZE1 DSI_VNPCCR_NPSIZE1_Msk 20235 #define DSI_VNPCCR_NPSIZE2_Pos (2U) 20236 #define DSI_VNPCCR_NPSIZE2_Msk (0x1U << DSI_VNPCCR_NPSIZE2_Pos) 20237 #define DSI_VNPCCR_NPSIZE2 DSI_VNPCCR_NPSIZE2_Msk 20238 #define DSI_VNPCCR_NPSIZE3_Pos (3U) 20239 #define DSI_VNPCCR_NPSIZE3_Msk (0x1U << DSI_VNPCCR_NPSIZE3_Pos) 20240 #define DSI_VNPCCR_NPSIZE3 DSI_VNPCCR_NPSIZE3_Msk 20241 #define DSI_VNPCCR_NPSIZE4_Pos (4U) 20242 #define DSI_VNPCCR_NPSIZE4_Msk (0x1U << DSI_VNPCCR_NPSIZE4_Pos) 20243 #define DSI_VNPCCR_NPSIZE4 DSI_VNPCCR_NPSIZE4_Msk 20244 #define DSI_VNPCCR_NPSIZE5_Pos (5U) 20245 #define DSI_VNPCCR_NPSIZE5_Msk (0x1U << DSI_VNPCCR_NPSIZE5_Pos) 20246 #define DSI_VNPCCR_NPSIZE5 DSI_VNPCCR_NPSIZE5_Msk 20247 #define DSI_VNPCCR_NPSIZE6_Pos (6U) 20248 #define DSI_VNPCCR_NPSIZE6_Msk (0x1U << DSI_VNPCCR_NPSIZE6_Pos) 20249 #define DSI_VNPCCR_NPSIZE6 DSI_VNPCCR_NPSIZE6_Msk 20250 #define DSI_VNPCCR_NPSIZE7_Pos (7U) 20251 #define DSI_VNPCCR_NPSIZE7_Msk (0x1U << DSI_VNPCCR_NPSIZE7_Pos) 20252 #define DSI_VNPCCR_NPSIZE7 DSI_VNPCCR_NPSIZE7_Msk 20253 #define DSI_VNPCCR_NPSIZE8_Pos (8U) 20254 #define DSI_VNPCCR_NPSIZE8_Msk (0x1U << DSI_VNPCCR_NPSIZE8_Pos) 20255 #define DSI_VNPCCR_NPSIZE8 DSI_VNPCCR_NPSIZE8_Msk 20256 #define DSI_VNPCCR_NPSIZE9_Pos (9U) 20257 #define DSI_VNPCCR_NPSIZE9_Msk (0x1U << DSI_VNPCCR_NPSIZE9_Pos) 20258 #define DSI_VNPCCR_NPSIZE9 DSI_VNPCCR_NPSIZE9_Msk 20259 #define DSI_VNPCCR_NPSIZE10_Pos (10U) 20260 #define DSI_VNPCCR_NPSIZE10_Msk (0x1U << DSI_VNPCCR_NPSIZE10_Pos) 20261 #define DSI_VNPCCR_NPSIZE10 DSI_VNPCCR_NPSIZE10_Msk 20262 #define DSI_VNPCCR_NPSIZE11_Pos (11U) 20263 #define DSI_VNPCCR_NPSIZE11_Msk (0x1U << DSI_VNPCCR_NPSIZE11_Pos) 20264 #define DSI_VNPCCR_NPSIZE11 DSI_VNPCCR_NPSIZE11_Msk 20265 #define DSI_VNPCCR_NPSIZE12_Pos (12U) 20266 #define DSI_VNPCCR_NPSIZE12_Msk (0x1U << DSI_VNPCCR_NPSIZE12_Pos) 20267 #define DSI_VNPCCR_NPSIZE12 DSI_VNPCCR_NPSIZE12_Msk 20270 #define DSI_VHSACCR_HSA_Pos (0U) 20271 #define DSI_VHSACCR_HSA_Msk (0xFFFU << DSI_VHSACCR_HSA_Pos) 20272 #define DSI_VHSACCR_HSA DSI_VHSACCR_HSA_Msk 20273 #define DSI_VHSACCR_HSA0_Pos (0U) 20274 #define DSI_VHSACCR_HSA0_Msk (0x1U << DSI_VHSACCR_HSA0_Pos) 20275 #define DSI_VHSACCR_HSA0 DSI_VHSACCR_HSA0_Msk 20276 #define DSI_VHSACCR_HSA1_Pos (1U) 20277 #define DSI_VHSACCR_HSA1_Msk (0x1U << DSI_VHSACCR_HSA1_Pos) 20278 #define DSI_VHSACCR_HSA1 DSI_VHSACCR_HSA1_Msk 20279 #define DSI_VHSACCR_HSA2_Pos (2U) 20280 #define DSI_VHSACCR_HSA2_Msk (0x1U << DSI_VHSACCR_HSA2_Pos) 20281 #define DSI_VHSACCR_HSA2 DSI_VHSACCR_HSA2_Msk 20282 #define DSI_VHSACCR_HSA3_Pos (3U) 20283 #define DSI_VHSACCR_HSA3_Msk (0x1U << DSI_VHSACCR_HSA3_Pos) 20284 #define DSI_VHSACCR_HSA3 DSI_VHSACCR_HSA3_Msk 20285 #define DSI_VHSACCR_HSA4_Pos (4U) 20286 #define DSI_VHSACCR_HSA4_Msk (0x1U << DSI_VHSACCR_HSA4_Pos) 20287 #define DSI_VHSACCR_HSA4 DSI_VHSACCR_HSA4_Msk 20288 #define DSI_VHSACCR_HSA5_Pos (5U) 20289 #define DSI_VHSACCR_HSA5_Msk (0x1U << DSI_VHSACCR_HSA5_Pos) 20290 #define DSI_VHSACCR_HSA5 DSI_VHSACCR_HSA5_Msk 20291 #define DSI_VHSACCR_HSA6_Pos (6U) 20292 #define DSI_VHSACCR_HSA6_Msk (0x1U << DSI_VHSACCR_HSA6_Pos) 20293 #define DSI_VHSACCR_HSA6 DSI_VHSACCR_HSA6_Msk 20294 #define DSI_VHSACCR_HSA7_Pos (7U) 20295 #define DSI_VHSACCR_HSA7_Msk (0x1U << DSI_VHSACCR_HSA7_Pos) 20296 #define DSI_VHSACCR_HSA7 DSI_VHSACCR_HSA7_Msk 20297 #define DSI_VHSACCR_HSA8_Pos (8U) 20298 #define DSI_VHSACCR_HSA8_Msk (0x1U << DSI_VHSACCR_HSA8_Pos) 20299 #define DSI_VHSACCR_HSA8 DSI_VHSACCR_HSA8_Msk 20300 #define DSI_VHSACCR_HSA9_Pos (9U) 20301 #define DSI_VHSACCR_HSA9_Msk (0x1U << DSI_VHSACCR_HSA9_Pos) 20302 #define DSI_VHSACCR_HSA9 DSI_VHSACCR_HSA9_Msk 20303 #define DSI_VHSACCR_HSA10_Pos (10U) 20304 #define DSI_VHSACCR_HSA10_Msk (0x1U << DSI_VHSACCR_HSA10_Pos) 20305 #define DSI_VHSACCR_HSA10 DSI_VHSACCR_HSA10_Msk 20306 #define DSI_VHSACCR_HSA11_Pos (11U) 20307 #define DSI_VHSACCR_HSA11_Msk (0x1U << DSI_VHSACCR_HSA11_Pos) 20308 #define DSI_VHSACCR_HSA11 DSI_VHSACCR_HSA11_Msk 20311 #define DSI_VHBPCCR_HBP_Pos (0U) 20312 #define DSI_VHBPCCR_HBP_Msk (0xFFFU << DSI_VHBPCCR_HBP_Pos) 20313 #define DSI_VHBPCCR_HBP DSI_VHBPCCR_HBP_Msk 20314 #define DSI_VHBPCCR_HBP0_Pos (0U) 20315 #define DSI_VHBPCCR_HBP0_Msk (0x1U << DSI_VHBPCCR_HBP0_Pos) 20316 #define DSI_VHBPCCR_HBP0 DSI_VHBPCCR_HBP0_Msk 20317 #define DSI_VHBPCCR_HBP1_Pos (1U) 20318 #define DSI_VHBPCCR_HBP1_Msk (0x1U << DSI_VHBPCCR_HBP1_Pos) 20319 #define DSI_VHBPCCR_HBP1 DSI_VHBPCCR_HBP1_Msk 20320 #define DSI_VHBPCCR_HBP2_Pos (2U) 20321 #define DSI_VHBPCCR_HBP2_Msk (0x1U << DSI_VHBPCCR_HBP2_Pos) 20322 #define DSI_VHBPCCR_HBP2 DSI_VHBPCCR_HBP2_Msk 20323 #define DSI_VHBPCCR_HBP3_Pos (3U) 20324 #define DSI_VHBPCCR_HBP3_Msk (0x1U << DSI_VHBPCCR_HBP3_Pos) 20325 #define DSI_VHBPCCR_HBP3 DSI_VHBPCCR_HBP3_Msk 20326 #define DSI_VHBPCCR_HBP4_Pos (4U) 20327 #define DSI_VHBPCCR_HBP4_Msk (0x1U << DSI_VHBPCCR_HBP4_Pos) 20328 #define DSI_VHBPCCR_HBP4 DSI_VHBPCCR_HBP4_Msk 20329 #define DSI_VHBPCCR_HBP5_Pos (5U) 20330 #define DSI_VHBPCCR_HBP5_Msk (0x1U << DSI_VHBPCCR_HBP5_Pos) 20331 #define DSI_VHBPCCR_HBP5 DSI_VHBPCCR_HBP5_Msk 20332 #define DSI_VHBPCCR_HBP6_Pos (6U) 20333 #define DSI_VHBPCCR_HBP6_Msk (0x1U << DSI_VHBPCCR_HBP6_Pos) 20334 #define DSI_VHBPCCR_HBP6 DSI_VHBPCCR_HBP6_Msk 20335 #define DSI_VHBPCCR_HBP7_Pos (7U) 20336 #define DSI_VHBPCCR_HBP7_Msk (0x1U << DSI_VHBPCCR_HBP7_Pos) 20337 #define DSI_VHBPCCR_HBP7 DSI_VHBPCCR_HBP7_Msk 20338 #define DSI_VHBPCCR_HBP8_Pos (8U) 20339 #define DSI_VHBPCCR_HBP8_Msk (0x1U << DSI_VHBPCCR_HBP8_Pos) 20340 #define DSI_VHBPCCR_HBP8 DSI_VHBPCCR_HBP8_Msk 20341 #define DSI_VHBPCCR_HBP9_Pos (9U) 20342 #define DSI_VHBPCCR_HBP9_Msk (0x1U << DSI_VHBPCCR_HBP9_Pos) 20343 #define DSI_VHBPCCR_HBP9 DSI_VHBPCCR_HBP9_Msk 20344 #define DSI_VHBPCCR_HBP10_Pos (10U) 20345 #define DSI_VHBPCCR_HBP10_Msk (0x1U << DSI_VHBPCCR_HBP10_Pos) 20346 #define DSI_VHBPCCR_HBP10 DSI_VHBPCCR_HBP10_Msk 20347 #define DSI_VHBPCCR_HBP11_Pos (11U) 20348 #define DSI_VHBPCCR_HBP11_Msk (0x1U << DSI_VHBPCCR_HBP11_Pos) 20349 #define DSI_VHBPCCR_HBP11 DSI_VHBPCCR_HBP11_Msk 20352 #define DSI_VLCCR_HLINE_Pos (0U) 20353 #define DSI_VLCCR_HLINE_Msk (0x7FFFU << DSI_VLCCR_HLINE_Pos) 20354 #define DSI_VLCCR_HLINE DSI_VLCCR_HLINE_Msk 20355 #define DSI_VLCCR_HLINE0_Pos (0U) 20356 #define DSI_VLCCR_HLINE0_Msk (0x1U << DSI_VLCCR_HLINE0_Pos) 20357 #define DSI_VLCCR_HLINE0 DSI_VLCCR_HLINE0_Msk 20358 #define DSI_VLCCR_HLINE1_Pos (1U) 20359 #define DSI_VLCCR_HLINE1_Msk (0x1U << DSI_VLCCR_HLINE1_Pos) 20360 #define DSI_VLCCR_HLINE1 DSI_VLCCR_HLINE1_Msk 20361 #define DSI_VLCCR_HLINE2_Pos (2U) 20362 #define DSI_VLCCR_HLINE2_Msk (0x1U << DSI_VLCCR_HLINE2_Pos) 20363 #define DSI_VLCCR_HLINE2 DSI_VLCCR_HLINE2_Msk 20364 #define DSI_VLCCR_HLINE3_Pos (3U) 20365 #define DSI_VLCCR_HLINE3_Msk (0x1U << DSI_VLCCR_HLINE3_Pos) 20366 #define DSI_VLCCR_HLINE3 DSI_VLCCR_HLINE3_Msk 20367 #define DSI_VLCCR_HLINE4_Pos (4U) 20368 #define DSI_VLCCR_HLINE4_Msk (0x1U << DSI_VLCCR_HLINE4_Pos) 20369 #define DSI_VLCCR_HLINE4 DSI_VLCCR_HLINE4_Msk 20370 #define DSI_VLCCR_HLINE5_Pos (5U) 20371 #define DSI_VLCCR_HLINE5_Msk (0x1U << DSI_VLCCR_HLINE5_Pos) 20372 #define DSI_VLCCR_HLINE5 DSI_VLCCR_HLINE5_Msk 20373 #define DSI_VLCCR_HLINE6_Pos (6U) 20374 #define DSI_VLCCR_HLINE6_Msk (0x1U << DSI_VLCCR_HLINE6_Pos) 20375 #define DSI_VLCCR_HLINE6 DSI_VLCCR_HLINE6_Msk 20376 #define DSI_VLCCR_HLINE7_Pos (7U) 20377 #define DSI_VLCCR_HLINE7_Msk (0x1U << DSI_VLCCR_HLINE7_Pos) 20378 #define DSI_VLCCR_HLINE7 DSI_VLCCR_HLINE7_Msk 20379 #define DSI_VLCCR_HLINE8_Pos (8U) 20380 #define DSI_VLCCR_HLINE8_Msk (0x1U << DSI_VLCCR_HLINE8_Pos) 20381 #define DSI_VLCCR_HLINE8 DSI_VLCCR_HLINE8_Msk 20382 #define DSI_VLCCR_HLINE9_Pos (9U) 20383 #define DSI_VLCCR_HLINE9_Msk (0x1U << DSI_VLCCR_HLINE9_Pos) 20384 #define DSI_VLCCR_HLINE9 DSI_VLCCR_HLINE9_Msk 20385 #define DSI_VLCCR_HLINE10_Pos (10U) 20386 #define DSI_VLCCR_HLINE10_Msk (0x1U << DSI_VLCCR_HLINE10_Pos) 20387 #define DSI_VLCCR_HLINE10 DSI_VLCCR_HLINE10_Msk 20388 #define DSI_VLCCR_HLINE11_Pos (11U) 20389 #define DSI_VLCCR_HLINE11_Msk (0x1U << DSI_VLCCR_HLINE11_Pos) 20390 #define DSI_VLCCR_HLINE11 DSI_VLCCR_HLINE11_Msk 20391 #define DSI_VLCCR_HLINE12_Pos (12U) 20392 #define DSI_VLCCR_HLINE12_Msk (0x1U << DSI_VLCCR_HLINE12_Pos) 20393 #define DSI_VLCCR_HLINE12 DSI_VLCCR_HLINE12_Msk 20394 #define DSI_VLCCR_HLINE13_Pos (13U) 20395 #define DSI_VLCCR_HLINE13_Msk (0x1U << DSI_VLCCR_HLINE13_Pos) 20396 #define DSI_VLCCR_HLINE13 DSI_VLCCR_HLINE13_Msk 20397 #define DSI_VLCCR_HLINE14_Pos (14U) 20398 #define DSI_VLCCR_HLINE14_Msk (0x1U << DSI_VLCCR_HLINE14_Pos) 20399 #define DSI_VLCCR_HLINE14 DSI_VLCCR_HLINE14_Msk 20402 #define DSI_VVSACCR_VSA_Pos (0U) 20403 #define DSI_VVSACCR_VSA_Msk (0x3FFU << DSI_VVSACCR_VSA_Pos) 20404 #define DSI_VVSACCR_VSA DSI_VVSACCR_VSA_Msk 20405 #define DSI_VVSACCR_VSA0_Pos (0U) 20406 #define DSI_VVSACCR_VSA0_Msk (0x1U << DSI_VVSACCR_VSA0_Pos) 20407 #define DSI_VVSACCR_VSA0 DSI_VVSACCR_VSA0_Msk 20408 #define DSI_VVSACCR_VSA1_Pos (1U) 20409 #define DSI_VVSACCR_VSA1_Msk (0x1U << DSI_VVSACCR_VSA1_Pos) 20410 #define DSI_VVSACCR_VSA1 DSI_VVSACCR_VSA1_Msk 20411 #define DSI_VVSACCR_VSA2_Pos (2U) 20412 #define DSI_VVSACCR_VSA2_Msk (0x1U << DSI_VVSACCR_VSA2_Pos) 20413 #define DSI_VVSACCR_VSA2 DSI_VVSACCR_VSA2_Msk 20414 #define DSI_VVSACCR_VSA3_Pos (3U) 20415 #define DSI_VVSACCR_VSA3_Msk (0x1U << DSI_VVSACCR_VSA3_Pos) 20416 #define DSI_VVSACCR_VSA3 DSI_VVSACCR_VSA3_Msk 20417 #define DSI_VVSACCR_VSA4_Pos (4U) 20418 #define DSI_VVSACCR_VSA4_Msk (0x1U << DSI_VVSACCR_VSA4_Pos) 20419 #define DSI_VVSACCR_VSA4 DSI_VVSACCR_VSA4_Msk 20420 #define DSI_VVSACCR_VSA5_Pos (5U) 20421 #define DSI_VVSACCR_VSA5_Msk (0x1U << DSI_VVSACCR_VSA5_Pos) 20422 #define DSI_VVSACCR_VSA5 DSI_VVSACCR_VSA5_Msk 20423 #define DSI_VVSACCR_VSA6_Pos (6U) 20424 #define DSI_VVSACCR_VSA6_Msk (0x1U << DSI_VVSACCR_VSA6_Pos) 20425 #define DSI_VVSACCR_VSA6 DSI_VVSACCR_VSA6_Msk 20426 #define DSI_VVSACCR_VSA7_Pos (7U) 20427 #define DSI_VVSACCR_VSA7_Msk (0x1U << DSI_VVSACCR_VSA7_Pos) 20428 #define DSI_VVSACCR_VSA7 DSI_VVSACCR_VSA7_Msk 20429 #define DSI_VVSACCR_VSA8_Pos (8U) 20430 #define DSI_VVSACCR_VSA8_Msk (0x1U << DSI_VVSACCR_VSA8_Pos) 20431 #define DSI_VVSACCR_VSA8 DSI_VVSACCR_VSA8_Msk 20432 #define DSI_VVSACCR_VSA9_Pos (9U) 20433 #define DSI_VVSACCR_VSA9_Msk (0x1U << DSI_VVSACCR_VSA9_Pos) 20434 #define DSI_VVSACCR_VSA9 DSI_VVSACCR_VSA9_Msk 20437 #define DSI_VVBPCCR_VBP_Pos (0U) 20438 #define DSI_VVBPCCR_VBP_Msk (0x3FFU << DSI_VVBPCCR_VBP_Pos) 20439 #define DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk 20440 #define DSI_VVBPCCR_VBP0_Pos (0U) 20441 #define DSI_VVBPCCR_VBP0_Msk (0x1U << DSI_VVBPCCR_VBP0_Pos) 20442 #define DSI_VVBPCCR_VBP0 DSI_VVBPCCR_VBP0_Msk 20443 #define DSI_VVBPCCR_VBP1_Pos (1U) 20444 #define DSI_VVBPCCR_VBP1_Msk (0x1U << DSI_VVBPCCR_VBP1_Pos) 20445 #define DSI_VVBPCCR_VBP1 DSI_VVBPCCR_VBP1_Msk 20446 #define DSI_VVBPCCR_VBP2_Pos (2U) 20447 #define DSI_VVBPCCR_VBP2_Msk (0x1U << DSI_VVBPCCR_VBP2_Pos) 20448 #define DSI_VVBPCCR_VBP2 DSI_VVBPCCR_VBP2_Msk 20449 #define DSI_VVBPCCR_VBP3_Pos (3U) 20450 #define DSI_VVBPCCR_VBP3_Msk (0x1U << DSI_VVBPCCR_VBP3_Pos) 20451 #define DSI_VVBPCCR_VBP3 DSI_VVBPCCR_VBP3_Msk 20452 #define DSI_VVBPCCR_VBP4_Pos (4U) 20453 #define DSI_VVBPCCR_VBP4_Msk (0x1U << DSI_VVBPCCR_VBP4_Pos) 20454 #define DSI_VVBPCCR_VBP4 DSI_VVBPCCR_VBP4_Msk 20455 #define DSI_VVBPCCR_VBP5_Pos (5U) 20456 #define DSI_VVBPCCR_VBP5_Msk (0x1U << DSI_VVBPCCR_VBP5_Pos) 20457 #define DSI_VVBPCCR_VBP5 DSI_VVBPCCR_VBP5_Msk 20458 #define DSI_VVBPCCR_VBP6_Pos (6U) 20459 #define DSI_VVBPCCR_VBP6_Msk (0x1U << DSI_VVBPCCR_VBP6_Pos) 20460 #define DSI_VVBPCCR_VBP6 DSI_VVBPCCR_VBP6_Msk 20461 #define DSI_VVBPCCR_VBP7_Pos (7U) 20462 #define DSI_VVBPCCR_VBP7_Msk (0x1U << DSI_VVBPCCR_VBP7_Pos) 20463 #define DSI_VVBPCCR_VBP7 DSI_VVBPCCR_VBP7_Msk 20464 #define DSI_VVBPCCR_VBP8_Pos (8U) 20465 #define DSI_VVBPCCR_VBP8_Msk (0x1U << DSI_VVBPCCR_VBP8_Pos) 20466 #define DSI_VVBPCCR_VBP8 DSI_VVBPCCR_VBP8_Msk 20467 #define DSI_VVBPCCR_VBP9_Pos (9U) 20468 #define DSI_VVBPCCR_VBP9_Msk (0x1U << DSI_VVBPCCR_VBP9_Pos) 20469 #define DSI_VVBPCCR_VBP9 DSI_VVBPCCR_VBP9_Msk 20472 #define DSI_VVFPCCR_VFP_Pos (0U) 20473 #define DSI_VVFPCCR_VFP_Msk (0x3FFU << DSI_VVFPCCR_VFP_Pos) 20474 #define DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk 20475 #define DSI_VVFPCCR_VFP0_Pos (0U) 20476 #define DSI_VVFPCCR_VFP0_Msk (0x1U << DSI_VVFPCCR_VFP0_Pos) 20477 #define DSI_VVFPCCR_VFP0 DSI_VVFPCCR_VFP0_Msk 20478 #define DSI_VVFPCCR_VFP1_Pos (1U) 20479 #define DSI_VVFPCCR_VFP1_Msk (0x1U << DSI_VVFPCCR_VFP1_Pos) 20480 #define DSI_VVFPCCR_VFP1 DSI_VVFPCCR_VFP1_Msk 20481 #define DSI_VVFPCCR_VFP2_Pos (2U) 20482 #define DSI_VVFPCCR_VFP2_Msk (0x1U << DSI_VVFPCCR_VFP2_Pos) 20483 #define DSI_VVFPCCR_VFP2 DSI_VVFPCCR_VFP2_Msk 20484 #define DSI_VVFPCCR_VFP3_Pos (3U) 20485 #define DSI_VVFPCCR_VFP3_Msk (0x1U << DSI_VVFPCCR_VFP3_Pos) 20486 #define DSI_VVFPCCR_VFP3 DSI_VVFPCCR_VFP3_Msk 20487 #define DSI_VVFPCCR_VFP4_Pos (4U) 20488 #define DSI_VVFPCCR_VFP4_Msk (0x1U << DSI_VVFPCCR_VFP4_Pos) 20489 #define DSI_VVFPCCR_VFP4 DSI_VVFPCCR_VFP4_Msk 20490 #define DSI_VVFPCCR_VFP5_Pos (5U) 20491 #define DSI_VVFPCCR_VFP5_Msk (0x1U << DSI_VVFPCCR_VFP5_Pos) 20492 #define DSI_VVFPCCR_VFP5 DSI_VVFPCCR_VFP5_Msk 20493 #define DSI_VVFPCCR_VFP6_Pos (6U) 20494 #define DSI_VVFPCCR_VFP6_Msk (0x1U << DSI_VVFPCCR_VFP6_Pos) 20495 #define DSI_VVFPCCR_VFP6 DSI_VVFPCCR_VFP6_Msk 20496 #define DSI_VVFPCCR_VFP7_Pos (7U) 20497 #define DSI_VVFPCCR_VFP7_Msk (0x1U << DSI_VVFPCCR_VFP7_Pos) 20498 #define DSI_VVFPCCR_VFP7 DSI_VVFPCCR_VFP7_Msk 20499 #define DSI_VVFPCCR_VFP8_Pos (8U) 20500 #define DSI_VVFPCCR_VFP8_Msk (0x1U << DSI_VVFPCCR_VFP8_Pos) 20501 #define DSI_VVFPCCR_VFP8 DSI_VVFPCCR_VFP8_Msk 20502 #define DSI_VVFPCCR_VFP9_Pos (9U) 20503 #define DSI_VVFPCCR_VFP9_Msk (0x1U << DSI_VVFPCCR_VFP9_Pos) 20504 #define DSI_VVFPCCR_VFP9 DSI_VVFPCCR_VFP9_Msk 20507 #define DSI_VVACCR_VA_Pos (0U) 20508 #define DSI_VVACCR_VA_Msk (0x3FFFU << DSI_VVACCR_VA_Pos) 20509 #define DSI_VVACCR_VA DSI_VVACCR_VA_Msk 20510 #define DSI_VVACCR_VA0_Pos (0U) 20511 #define DSI_VVACCR_VA0_Msk (0x1U << DSI_VVACCR_VA0_Pos) 20512 #define DSI_VVACCR_VA0 DSI_VVACCR_VA0_Msk 20513 #define DSI_VVACCR_VA1_Pos (1U) 20514 #define DSI_VVACCR_VA1_Msk (0x1U << DSI_VVACCR_VA1_Pos) 20515 #define DSI_VVACCR_VA1 DSI_VVACCR_VA1_Msk 20516 #define DSI_VVACCR_VA2_Pos (2U) 20517 #define DSI_VVACCR_VA2_Msk (0x1U << DSI_VVACCR_VA2_Pos) 20518 #define DSI_VVACCR_VA2 DSI_VVACCR_VA2_Msk 20519 #define DSI_VVACCR_VA3_Pos (3U) 20520 #define DSI_VVACCR_VA3_Msk (0x1U << DSI_VVACCR_VA3_Pos) 20521 #define DSI_VVACCR_VA3 DSI_VVACCR_VA3_Msk 20522 #define DSI_VVACCR_VA4_Pos (4U) 20523 #define DSI_VVACCR_VA4_Msk (0x1U << DSI_VVACCR_VA4_Pos) 20524 #define DSI_VVACCR_VA4 DSI_VVACCR_VA4_Msk 20525 #define DSI_VVACCR_VA5_Pos (5U) 20526 #define DSI_VVACCR_VA5_Msk (0x1U << DSI_VVACCR_VA5_Pos) 20527 #define DSI_VVACCR_VA5 DSI_VVACCR_VA5_Msk 20528 #define DSI_VVACCR_VA6_Pos (6U) 20529 #define DSI_VVACCR_VA6_Msk (0x1U << DSI_VVACCR_VA6_Pos) 20530 #define DSI_VVACCR_VA6 DSI_VVACCR_VA6_Msk 20531 #define DSI_VVACCR_VA7_Pos (7U) 20532 #define DSI_VVACCR_VA7_Msk (0x1U << DSI_VVACCR_VA7_Pos) 20533 #define DSI_VVACCR_VA7 DSI_VVACCR_VA7_Msk 20534 #define DSI_VVACCR_VA8_Pos (8U) 20535 #define DSI_VVACCR_VA8_Msk (0x1U << DSI_VVACCR_VA8_Pos) 20536 #define DSI_VVACCR_VA8 DSI_VVACCR_VA8_Msk 20537 #define DSI_VVACCR_VA9_Pos (9U) 20538 #define DSI_VVACCR_VA9_Msk (0x1U << DSI_VVACCR_VA9_Pos) 20539 #define DSI_VVACCR_VA9 DSI_VVACCR_VA9_Msk 20540 #define DSI_VVACCR_VA10_Pos (10U) 20541 #define DSI_VVACCR_VA10_Msk (0x1U << DSI_VVACCR_VA10_Pos) 20542 #define DSI_VVACCR_VA10 DSI_VVACCR_VA10_Msk 20543 #define DSI_VVACCR_VA11_Pos (11U) 20544 #define DSI_VVACCR_VA11_Msk (0x1U << DSI_VVACCR_VA11_Pos) 20545 #define DSI_VVACCR_VA11 DSI_VVACCR_VA11_Msk 20546 #define DSI_VVACCR_VA12_Pos (12U) 20547 #define DSI_VVACCR_VA12_Msk (0x1U << DSI_VVACCR_VA12_Pos) 20548 #define DSI_VVACCR_VA12 DSI_VVACCR_VA12_Msk 20549 #define DSI_VVACCR_VA13_Pos (13U) 20550 #define DSI_VVACCR_VA13_Msk (0x1U << DSI_VVACCR_VA13_Pos) 20551 #define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk 20554 #define DSI_TDCCR_3DM 0x00000003U 20555 #define DSI_TDCCR_3DM0 0x00000001U 20556 #define DSI_TDCCR_3DM1 0x00000002U 20558 #define DSI_TDCCR_3DF 0x0000000CU 20559 #define DSI_TDCCR_3DF0 0x00000004U 20560 #define DSI_TDCCR_3DF1 0x00000008U 20562 #define DSI_TDCCR_SVS_Pos (4U) 20563 #define DSI_TDCCR_SVS_Msk (0x1U << DSI_TDCCR_SVS_Pos) 20564 #define DSI_TDCCR_SVS DSI_TDCCR_SVS_Msk 20565 #define DSI_TDCCR_RF_Pos (5U) 20566 #define DSI_TDCCR_RF_Msk (0x1U << DSI_TDCCR_RF_Pos) 20567 #define DSI_TDCCR_RF DSI_TDCCR_RF_Msk 20568 #define DSI_TDCCR_S3DC_Pos (16U) 20569 #define DSI_TDCCR_S3DC_Msk (0x1U << DSI_TDCCR_S3DC_Pos) 20570 #define DSI_TDCCR_S3DC DSI_TDCCR_S3DC_Msk 20573 #define DSI_WCFGR_DSIM_Pos (0U) 20574 #define DSI_WCFGR_DSIM_Msk (0x1U << DSI_WCFGR_DSIM_Pos) 20575 #define DSI_WCFGR_DSIM DSI_WCFGR_DSIM_Msk 20576 #define DSI_WCFGR_COLMUX_Pos (1U) 20577 #define DSI_WCFGR_COLMUX_Msk (0x7U << DSI_WCFGR_COLMUX_Pos) 20578 #define DSI_WCFGR_COLMUX DSI_WCFGR_COLMUX_Msk 20579 #define DSI_WCFGR_COLMUX0_Pos (1U) 20580 #define DSI_WCFGR_COLMUX0_Msk (0x1U << DSI_WCFGR_COLMUX0_Pos) 20581 #define DSI_WCFGR_COLMUX0 DSI_WCFGR_COLMUX0_Msk 20582 #define DSI_WCFGR_COLMUX1_Pos (2U) 20583 #define DSI_WCFGR_COLMUX1_Msk (0x1U << DSI_WCFGR_COLMUX1_Pos) 20584 #define DSI_WCFGR_COLMUX1 DSI_WCFGR_COLMUX1_Msk 20585 #define DSI_WCFGR_COLMUX2_Pos (3U) 20586 #define DSI_WCFGR_COLMUX2_Msk (0x1U << DSI_WCFGR_COLMUX2_Pos) 20587 #define DSI_WCFGR_COLMUX2 DSI_WCFGR_COLMUX2_Msk 20589 #define DSI_WCFGR_TESRC_Pos (4U) 20590 #define DSI_WCFGR_TESRC_Msk (0x1U << DSI_WCFGR_TESRC_Pos) 20591 #define DSI_WCFGR_TESRC DSI_WCFGR_TESRC_Msk 20592 #define DSI_WCFGR_TEPOL_Pos (5U) 20593 #define DSI_WCFGR_TEPOL_Msk (0x1U << DSI_WCFGR_TEPOL_Pos) 20594 #define DSI_WCFGR_TEPOL DSI_WCFGR_TEPOL_Msk 20595 #define DSI_WCFGR_AR_Pos (6U) 20596 #define DSI_WCFGR_AR_Msk (0x1U << DSI_WCFGR_AR_Pos) 20597 #define DSI_WCFGR_AR DSI_WCFGR_AR_Msk 20598 #define DSI_WCFGR_VSPOL_Pos (7U) 20599 #define DSI_WCFGR_VSPOL_Msk (0x1U << DSI_WCFGR_VSPOL_Pos) 20600 #define DSI_WCFGR_VSPOL DSI_WCFGR_VSPOL_Msk 20603 #define DSI_WCR_COLM_Pos (0U) 20604 #define DSI_WCR_COLM_Msk (0x1U << DSI_WCR_COLM_Pos) 20605 #define DSI_WCR_COLM DSI_WCR_COLM_Msk 20606 #define DSI_WCR_SHTDN_Pos (1U) 20607 #define DSI_WCR_SHTDN_Msk (0x1U << DSI_WCR_SHTDN_Pos) 20608 #define DSI_WCR_SHTDN DSI_WCR_SHTDN_Msk 20609 #define DSI_WCR_LTDCEN_Pos (2U) 20610 #define DSI_WCR_LTDCEN_Msk (0x1U << DSI_WCR_LTDCEN_Pos) 20611 #define DSI_WCR_LTDCEN DSI_WCR_LTDCEN_Msk 20612 #define DSI_WCR_DSIEN_Pos (3U) 20613 #define DSI_WCR_DSIEN_Msk (0x1U << DSI_WCR_DSIEN_Pos) 20614 #define DSI_WCR_DSIEN DSI_WCR_DSIEN_Msk 20617 #define DSI_WIER_TEIE_Pos (0U) 20618 #define DSI_WIER_TEIE_Msk (0x1U << DSI_WIER_TEIE_Pos) 20619 #define DSI_WIER_TEIE DSI_WIER_TEIE_Msk 20620 #define DSI_WIER_ERIE_Pos (1U) 20621 #define DSI_WIER_ERIE_Msk (0x1U << DSI_WIER_ERIE_Pos) 20622 #define DSI_WIER_ERIE DSI_WIER_ERIE_Msk 20623 #define DSI_WIER_PLLLIE_Pos (9U) 20624 #define DSI_WIER_PLLLIE_Msk (0x1U << DSI_WIER_PLLLIE_Pos) 20625 #define DSI_WIER_PLLLIE DSI_WIER_PLLLIE_Msk 20626 #define DSI_WIER_PLLUIE_Pos (10U) 20627 #define DSI_WIER_PLLUIE_Msk (0x1U << DSI_WIER_PLLUIE_Pos) 20628 #define DSI_WIER_PLLUIE DSI_WIER_PLLUIE_Msk 20629 #define DSI_WIER_RRIE_Pos (13U) 20630 #define DSI_WIER_RRIE_Msk (0x1U << DSI_WIER_RRIE_Pos) 20631 #define DSI_WIER_RRIE DSI_WIER_RRIE_Msk 20634 #define DSI_WISR_TEIF_Pos (0U) 20635 #define DSI_WISR_TEIF_Msk (0x1U << DSI_WISR_TEIF_Pos) 20636 #define DSI_WISR_TEIF DSI_WISR_TEIF_Msk 20637 #define DSI_WISR_ERIF_Pos (1U) 20638 #define DSI_WISR_ERIF_Msk (0x1U << DSI_WISR_ERIF_Pos) 20639 #define DSI_WISR_ERIF DSI_WISR_ERIF_Msk 20640 #define DSI_WISR_BUSY_Pos (2U) 20641 #define DSI_WISR_BUSY_Msk (0x1U << DSI_WISR_BUSY_Pos) 20642 #define DSI_WISR_BUSY DSI_WISR_BUSY_Msk 20643 #define DSI_WISR_PLLLS_Pos (8U) 20644 #define DSI_WISR_PLLLS_Msk (0x1U << DSI_WISR_PLLLS_Pos) 20645 #define DSI_WISR_PLLLS DSI_WISR_PLLLS_Msk 20646 #define DSI_WISR_PLLLIF_Pos (9U) 20647 #define DSI_WISR_PLLLIF_Msk (0x1U << DSI_WISR_PLLLIF_Pos) 20648 #define DSI_WISR_PLLLIF DSI_WISR_PLLLIF_Msk 20649 #define DSI_WISR_PLLUIF_Pos (10U) 20650 #define DSI_WISR_PLLUIF_Msk (0x1U << DSI_WISR_PLLUIF_Pos) 20651 #define DSI_WISR_PLLUIF DSI_WISR_PLLUIF_Msk 20652 #define DSI_WISR_RRS_Pos (12U) 20653 #define DSI_WISR_RRS_Msk (0x1U << DSI_WISR_RRS_Pos) 20654 #define DSI_WISR_RRS DSI_WISR_RRS_Msk 20655 #define DSI_WISR_RRIF_Pos (13U) 20656 #define DSI_WISR_RRIF_Msk (0x1U << DSI_WISR_RRIF_Pos) 20657 #define DSI_WISR_RRIF DSI_WISR_RRIF_Msk 20660 #define DSI_WIFCR_CTEIF_Pos (0U) 20661 #define DSI_WIFCR_CTEIF_Msk (0x1U << DSI_WIFCR_CTEIF_Pos) 20662 #define DSI_WIFCR_CTEIF DSI_WIFCR_CTEIF_Msk 20663 #define DSI_WIFCR_CERIF_Pos (1U) 20664 #define DSI_WIFCR_CERIF_Msk (0x1U << DSI_WIFCR_CERIF_Pos) 20665 #define DSI_WIFCR_CERIF DSI_WIFCR_CERIF_Msk 20666 #define DSI_WIFCR_CPLLLIF_Pos (9U) 20667 #define DSI_WIFCR_CPLLLIF_Msk (0x1U << DSI_WIFCR_CPLLLIF_Pos) 20668 #define DSI_WIFCR_CPLLLIF DSI_WIFCR_CPLLLIF_Msk 20669 #define DSI_WIFCR_CPLLUIF_Pos (10U) 20670 #define DSI_WIFCR_CPLLUIF_Msk (0x1U << DSI_WIFCR_CPLLUIF_Pos) 20671 #define DSI_WIFCR_CPLLUIF DSI_WIFCR_CPLLUIF_Msk 20672 #define DSI_WIFCR_CRRIF_Pos (13U) 20673 #define DSI_WIFCR_CRRIF_Msk (0x1U << DSI_WIFCR_CRRIF_Pos) 20674 #define DSI_WIFCR_CRRIF DSI_WIFCR_CRRIF_Msk 20677 #define DSI_WPCR0_UIX4_Pos (0U) 20678 #define DSI_WPCR0_UIX4_Msk (0x3FU << DSI_WPCR0_UIX4_Pos) 20679 #define DSI_WPCR0_UIX4 DSI_WPCR0_UIX4_Msk 20680 #define DSI_WPCR0_UIX4_0 (0x01U << DSI_WPCR0_UIX4_Pos) 20681 #define DSI_WPCR0_UIX4_1 (0x02U << DSI_WPCR0_UIX4_Pos) 20682 #define DSI_WPCR0_UIX4_2 (0x04U << DSI_WPCR0_UIX4_Pos) 20683 #define DSI_WPCR0_UIX4_3 (0x08U << DSI_WPCR0_UIX4_Pos) 20684 #define DSI_WPCR0_UIX4_4 (0x10U << DSI_WPCR0_UIX4_Pos) 20685 #define DSI_WPCR0_UIX4_5 (0x20U << DSI_WPCR0_UIX4_Pos) 20687 #define DSI_WPCR0_SWCL_Pos (6U) 20688 #define DSI_WPCR0_SWCL_Msk (0x1U << DSI_WPCR0_SWCL_Pos) 20689 #define DSI_WPCR0_SWCL DSI_WPCR0_SWCL_Msk 20690 #define DSI_WPCR0_SWDL0_Pos (7U) 20691 #define DSI_WPCR0_SWDL0_Msk (0x1U << DSI_WPCR0_SWDL0_Pos) 20692 #define DSI_WPCR0_SWDL0 DSI_WPCR0_SWDL0_Msk 20693 #define DSI_WPCR0_SWDL1_Pos (8U) 20694 #define DSI_WPCR0_SWDL1_Msk (0x1U << DSI_WPCR0_SWDL1_Pos) 20695 #define DSI_WPCR0_SWDL1 DSI_WPCR0_SWDL1_Msk 20696 #define DSI_WPCR0_HSICL_Pos (9U) 20697 #define DSI_WPCR0_HSICL_Msk (0x1U << DSI_WPCR0_HSICL_Pos) 20698 #define DSI_WPCR0_HSICL DSI_WPCR0_HSICL_Msk 20699 #define DSI_WPCR0_HSIDL0_Pos (10U) 20700 #define DSI_WPCR0_HSIDL0_Msk (0x1U << DSI_WPCR0_HSIDL0_Pos) 20701 #define DSI_WPCR0_HSIDL0 DSI_WPCR0_HSIDL0_Msk 20702 #define DSI_WPCR0_HSIDL1_Pos (11U) 20703 #define DSI_WPCR0_HSIDL1_Msk (0x1U << DSI_WPCR0_HSIDL1_Pos) 20704 #define DSI_WPCR0_HSIDL1 DSI_WPCR0_HSIDL1_Msk 20705 #define DSI_WPCR0_FTXSMCL_Pos (12U) 20706 #define DSI_WPCR0_FTXSMCL_Msk (0x1U << DSI_WPCR0_FTXSMCL_Pos) 20707 #define DSI_WPCR0_FTXSMCL DSI_WPCR0_FTXSMCL_Msk 20708 #define DSI_WPCR0_FTXSMDL_Pos (13U) 20709 #define DSI_WPCR0_FTXSMDL_Msk (0x1U << DSI_WPCR0_FTXSMDL_Pos) 20710 #define DSI_WPCR0_FTXSMDL DSI_WPCR0_FTXSMDL_Msk 20711 #define DSI_WPCR0_CDOFFDL_Pos (14U) 20712 #define DSI_WPCR0_CDOFFDL_Msk (0x1U << DSI_WPCR0_CDOFFDL_Pos) 20713 #define DSI_WPCR0_CDOFFDL DSI_WPCR0_CDOFFDL_Msk 20714 #define DSI_WPCR0_TDDL_Pos (16U) 20715 #define DSI_WPCR0_TDDL_Msk (0x1U << DSI_WPCR0_TDDL_Pos) 20716 #define DSI_WPCR0_TDDL DSI_WPCR0_TDDL_Msk 20717 #define DSI_WPCR0_PDEN_Pos (18U) 20718 #define DSI_WPCR0_PDEN_Msk (0x1U << DSI_WPCR0_PDEN_Pos) 20719 #define DSI_WPCR0_PDEN DSI_WPCR0_PDEN_Msk 20720 #define DSI_WPCR0_TCLKPREPEN_Pos (19U) 20721 #define DSI_WPCR0_TCLKPREPEN_Msk (0x1U << DSI_WPCR0_TCLKPREPEN_Pos) 20722 #define DSI_WPCR0_TCLKPREPEN DSI_WPCR0_TCLKPREPEN_Msk 20723 #define DSI_WPCR0_TCLKZEROEN_Pos (20U) 20724 #define DSI_WPCR0_TCLKZEROEN_Msk (0x1U << DSI_WPCR0_TCLKZEROEN_Pos) 20725 #define DSI_WPCR0_TCLKZEROEN DSI_WPCR0_TCLKZEROEN_Msk 20726 #define DSI_WPCR0_THSPREPEN_Pos (21U) 20727 #define DSI_WPCR0_THSPREPEN_Msk (0x1U << DSI_WPCR0_THSPREPEN_Pos) 20728 #define DSI_WPCR0_THSPREPEN DSI_WPCR0_THSPREPEN_Msk 20729 #define DSI_WPCR0_THSTRAILEN_Pos (22U) 20730 #define DSI_WPCR0_THSTRAILEN_Msk (0x1U << DSI_WPCR0_THSTRAILEN_Pos) 20731 #define DSI_WPCR0_THSTRAILEN DSI_WPCR0_THSTRAILEN_Msk 20732 #define DSI_WPCR0_THSZEROEN_Pos (23U) 20733 #define DSI_WPCR0_THSZEROEN_Msk (0x1U << DSI_WPCR0_THSZEROEN_Pos) 20734 #define DSI_WPCR0_THSZEROEN DSI_WPCR0_THSZEROEN_Msk 20735 #define DSI_WPCR0_TLPXDEN_Pos (24U) 20736 #define DSI_WPCR0_TLPXDEN_Msk (0x1U << DSI_WPCR0_TLPXDEN_Pos) 20737 #define DSI_WPCR0_TLPXDEN DSI_WPCR0_TLPXDEN_Msk 20738 #define DSI_WPCR0_THSEXITEN_Pos (25U) 20739 #define DSI_WPCR0_THSEXITEN_Msk (0x1U << DSI_WPCR0_THSEXITEN_Pos) 20740 #define DSI_WPCR0_THSEXITEN DSI_WPCR0_THSEXITEN_Msk 20741 #define DSI_WPCR0_TLPXCEN_Pos (26U) 20742 #define DSI_WPCR0_TLPXCEN_Msk (0x1U << DSI_WPCR0_TLPXCEN_Pos) 20743 #define DSI_WPCR0_TLPXCEN DSI_WPCR0_TLPXCEN_Msk 20744 #define DSI_WPCR0_TCLKPOSTEN_Pos (27U) 20745 #define DSI_WPCR0_TCLKPOSTEN_Msk (0x1U << DSI_WPCR0_TCLKPOSTEN_Pos) 20746 #define DSI_WPCR0_TCLKPOSTEN DSI_WPCR0_TCLKPOSTEN_Msk 20749 #define DSI_WPCR1_HSTXDCL_Pos (0U) 20750 #define DSI_WPCR1_HSTXDCL_Msk (0x3U << DSI_WPCR1_HSTXDCL_Pos) 20751 #define DSI_WPCR1_HSTXDCL DSI_WPCR1_HSTXDCL_Msk 20752 #define DSI_WPCR1_HSTXDCL0_Pos (0U) 20753 #define DSI_WPCR1_HSTXDCL0_Msk (0x1U << DSI_WPCR1_HSTXDCL0_Pos) 20754 #define DSI_WPCR1_HSTXDCL0 DSI_WPCR1_HSTXDCL0_Msk 20755 #define DSI_WPCR1_HSTXDCL1_Pos (1U) 20756 #define DSI_WPCR1_HSTXDCL1_Msk (0x1U << DSI_WPCR1_HSTXDCL1_Pos) 20757 #define DSI_WPCR1_HSTXDCL1 DSI_WPCR1_HSTXDCL1_Msk 20759 #define DSI_WPCR1_HSTXDDL_Pos (2U) 20760 #define DSI_WPCR1_HSTXDDL_Msk (0x3U << DSI_WPCR1_HSTXDDL_Pos) 20761 #define DSI_WPCR1_HSTXDDL DSI_WPCR1_HSTXDDL_Msk 20762 #define DSI_WPCR1_HSTXDDL0_Pos (2U) 20763 #define DSI_WPCR1_HSTXDDL0_Msk (0x1U << DSI_WPCR1_HSTXDDL0_Pos) 20764 #define DSI_WPCR1_HSTXDDL0 DSI_WPCR1_HSTXDDL0_Msk 20765 #define DSI_WPCR1_HSTXDDL1_Pos (3U) 20766 #define DSI_WPCR1_HSTXDDL1_Msk (0x1U << DSI_WPCR1_HSTXDDL1_Pos) 20767 #define DSI_WPCR1_HSTXDDL1 DSI_WPCR1_HSTXDDL1_Msk 20769 #define DSI_WPCR1_LPSRCCL_Pos (6U) 20770 #define DSI_WPCR1_LPSRCCL_Msk (0x3U << DSI_WPCR1_LPSRCCL_Pos) 20771 #define DSI_WPCR1_LPSRCCL DSI_WPCR1_LPSRCCL_Msk 20772 #define DSI_WPCR1_LPSRCCL0_Pos (6U) 20773 #define DSI_WPCR1_LPSRCCL0_Msk (0x1U << DSI_WPCR1_LPSRCCL0_Pos) 20774 #define DSI_WPCR1_LPSRCCL0 DSI_WPCR1_LPSRCCL0_Msk 20775 #define DSI_WPCR1_LPSRCCL1_Pos (7U) 20776 #define DSI_WPCR1_LPSRCCL1_Msk (0x1U << DSI_WPCR1_LPSRCCL1_Pos) 20777 #define DSI_WPCR1_LPSRCCL1 DSI_WPCR1_LPSRCCL1_Msk 20779 #define DSI_WPCR1_LPSRCDL_Pos (8U) 20780 #define DSI_WPCR1_LPSRCDL_Msk (0x3U << DSI_WPCR1_LPSRCDL_Pos) 20781 #define DSI_WPCR1_LPSRCDL DSI_WPCR1_LPSRCDL_Msk 20782 #define DSI_WPCR1_LPSRCDL0_Pos (8U) 20783 #define DSI_WPCR1_LPSRCDL0_Msk (0x1U << DSI_WPCR1_LPSRCDL0_Pos) 20784 #define DSI_WPCR1_LPSRCDL0 DSI_WPCR1_LPSRCDL0_Msk 20785 #define DSI_WPCR1_LPSRCDL1_Pos (9U) 20786 #define DSI_WPCR1_LPSRCDL1_Msk (0x1U << DSI_WPCR1_LPSRCDL1_Pos) 20787 #define DSI_WPCR1_LPSRCDL1 DSI_WPCR1_LPSRCDL1_Msk 20789 #define DSI_WPCR1_SDDC_Pos (12U) 20790 #define DSI_WPCR1_SDDC_Msk (0x1U << DSI_WPCR1_SDDC_Pos) 20791 #define DSI_WPCR1_SDDC DSI_WPCR1_SDDC_Msk 20793 #define DSI_WPCR1_LPRXVCDL_Pos (14U) 20794 #define DSI_WPCR1_LPRXVCDL_Msk (0x3U << DSI_WPCR1_LPRXVCDL_Pos) 20795 #define DSI_WPCR1_LPRXVCDL DSI_WPCR1_LPRXVCDL_Msk 20796 #define DSI_WPCR1_LPRXVCDL0_Pos (14U) 20797 #define DSI_WPCR1_LPRXVCDL0_Msk (0x1U << DSI_WPCR1_LPRXVCDL0_Pos) 20798 #define DSI_WPCR1_LPRXVCDL0 DSI_WPCR1_LPRXVCDL0_Msk 20799 #define DSI_WPCR1_LPRXVCDL1_Pos (15U) 20800 #define DSI_WPCR1_LPRXVCDL1_Msk (0x1U << DSI_WPCR1_LPRXVCDL1_Pos) 20801 #define DSI_WPCR1_LPRXVCDL1 DSI_WPCR1_LPRXVCDL1_Msk 20803 #define DSI_WPCR1_HSTXSRCCL_Pos (16U) 20804 #define DSI_WPCR1_HSTXSRCCL_Msk (0x3U << DSI_WPCR1_HSTXSRCCL_Pos) 20805 #define DSI_WPCR1_HSTXSRCCL DSI_WPCR1_HSTXSRCCL_Msk 20806 #define DSI_WPCR1_HSTXSRCCL0_Pos (16U) 20807 #define DSI_WPCR1_HSTXSRCCL0_Msk (0x1U << DSI_WPCR1_HSTXSRCCL0_Pos) 20808 #define DSI_WPCR1_HSTXSRCCL0 DSI_WPCR1_HSTXSRCCL0_Msk 20809 #define DSI_WPCR1_HSTXSRCCL1_Pos (17U) 20810 #define DSI_WPCR1_HSTXSRCCL1_Msk (0x1U << DSI_WPCR1_HSTXSRCCL1_Pos) 20811 #define DSI_WPCR1_HSTXSRCCL1 DSI_WPCR1_HSTXSRCCL1_Msk 20813 #define DSI_WPCR1_HSTXSRCDL_Pos (18U) 20814 #define DSI_WPCR1_HSTXSRCDL_Msk (0x3U << DSI_WPCR1_HSTXSRCDL_Pos) 20815 #define DSI_WPCR1_HSTXSRCDL DSI_WPCR1_HSTXSRCDL_Msk 20816 #define DSI_WPCR1_HSTXSRCDL0_Pos (18U) 20817 #define DSI_WPCR1_HSTXSRCDL0_Msk (0x1U << DSI_WPCR1_HSTXSRCDL0_Pos) 20818 #define DSI_WPCR1_HSTXSRCDL0 DSI_WPCR1_HSTXSRCDL0_Msk 20819 #define DSI_WPCR1_HSTXSRCDL1_Pos (19U) 20820 #define DSI_WPCR1_HSTXSRCDL1_Msk (0x1U << DSI_WPCR1_HSTXSRCDL1_Pos) 20821 #define DSI_WPCR1_HSTXSRCDL1 DSI_WPCR1_HSTXSRCDL1_Msk 20823 #define DSI_WPCR1_FLPRXLPM_Pos (22U) 20824 #define DSI_WPCR1_FLPRXLPM_Msk (0x1U << DSI_WPCR1_FLPRXLPM_Pos) 20825 #define DSI_WPCR1_FLPRXLPM DSI_WPCR1_FLPRXLPM_Msk 20827 #define DSI_WPCR1_LPRXFT_Pos (25U) 20828 #define DSI_WPCR1_LPRXFT_Msk (0x3U << DSI_WPCR1_LPRXFT_Pos) 20829 #define DSI_WPCR1_LPRXFT DSI_WPCR1_LPRXFT_Msk 20830 #define DSI_WPCR1_LPRXFT0_Pos (25U) 20831 #define DSI_WPCR1_LPRXFT0_Msk (0x1U << DSI_WPCR1_LPRXFT0_Pos) 20832 #define DSI_WPCR1_LPRXFT0 DSI_WPCR1_LPRXFT0_Msk 20833 #define DSI_WPCR1_LPRXFT1_Pos (26U) 20834 #define DSI_WPCR1_LPRXFT1_Msk (0x1U << DSI_WPCR1_LPRXFT1_Pos) 20835 #define DSI_WPCR1_LPRXFT1 DSI_WPCR1_LPRXFT1_Msk 20838 #define DSI_WPCR2_TCLKPREP_Pos (0U) 20839 #define DSI_WPCR2_TCLKPREP_Msk (0xFFU << DSI_WPCR2_TCLKPREP_Pos) 20840 #define DSI_WPCR2_TCLKPREP DSI_WPCR2_TCLKPREP_Msk 20841 #define DSI_WPCR2_TCLKPREP0_Pos (0U) 20842 #define DSI_WPCR2_TCLKPREP0_Msk (0x1U << DSI_WPCR2_TCLKPREP0_Pos) 20843 #define DSI_WPCR2_TCLKPREP0 DSI_WPCR2_TCLKPREP0_Msk 20844 #define DSI_WPCR2_TCLKPREP1_Pos (1U) 20845 #define DSI_WPCR2_TCLKPREP1_Msk (0x1U << DSI_WPCR2_TCLKPREP1_Pos) 20846 #define DSI_WPCR2_TCLKPREP1 DSI_WPCR2_TCLKPREP1_Msk 20847 #define DSI_WPCR2_TCLKPREP2_Pos (2U) 20848 #define DSI_WPCR2_TCLKPREP2_Msk (0x1U << DSI_WPCR2_TCLKPREP2_Pos) 20849 #define DSI_WPCR2_TCLKPREP2 DSI_WPCR2_TCLKPREP2_Msk 20850 #define DSI_WPCR2_TCLKPREP3_Pos (3U) 20851 #define DSI_WPCR2_TCLKPREP3_Msk (0x1U << DSI_WPCR2_TCLKPREP3_Pos) 20852 #define DSI_WPCR2_TCLKPREP3 DSI_WPCR2_TCLKPREP3_Msk 20853 #define DSI_WPCR2_TCLKPREP4_Pos (4U) 20854 #define DSI_WPCR2_TCLKPREP4_Msk (0x1U << DSI_WPCR2_TCLKPREP4_Pos) 20855 #define DSI_WPCR2_TCLKPREP4 DSI_WPCR2_TCLKPREP4_Msk 20856 #define DSI_WPCR2_TCLKPREP5_Pos (5U) 20857 #define DSI_WPCR2_TCLKPREP5_Msk (0x1U << DSI_WPCR2_TCLKPREP5_Pos) 20858 #define DSI_WPCR2_TCLKPREP5 DSI_WPCR2_TCLKPREP5_Msk 20859 #define DSI_WPCR2_TCLKPREP6_Pos (6U) 20860 #define DSI_WPCR2_TCLKPREP6_Msk (0x1U << DSI_WPCR2_TCLKPREP6_Pos) 20861 #define DSI_WPCR2_TCLKPREP6 DSI_WPCR2_TCLKPREP6_Msk 20862 #define DSI_WPCR2_TCLKPREP7_Pos (7U) 20863 #define DSI_WPCR2_TCLKPREP7_Msk (0x1U << DSI_WPCR2_TCLKPREP7_Pos) 20864 #define DSI_WPCR2_TCLKPREP7 DSI_WPCR2_TCLKPREP7_Msk 20866 #define DSI_WPCR2_TCLKZERO_Pos (8U) 20867 #define DSI_WPCR2_TCLKZERO_Msk (0xFFU << DSI_WPCR2_TCLKZERO_Pos) 20868 #define DSI_WPCR2_TCLKZERO DSI_WPCR2_TCLKZERO_Msk 20869 #define DSI_WPCR2_TCLKZERO0_Pos (8U) 20870 #define DSI_WPCR2_TCLKZERO0_Msk (0x1U << DSI_WPCR2_TCLKZERO0_Pos) 20871 #define DSI_WPCR2_TCLKZERO0 DSI_WPCR2_TCLKZERO0_Msk 20872 #define DSI_WPCR2_TCLKZERO1_Pos (9U) 20873 #define DSI_WPCR2_TCLKZERO1_Msk (0x1U << DSI_WPCR2_TCLKZERO1_Pos) 20874 #define DSI_WPCR2_TCLKZERO1 DSI_WPCR2_TCLKZERO1_Msk 20875 #define DSI_WPCR2_TCLKZERO2_Pos (10U) 20876 #define DSI_WPCR2_TCLKZERO2_Msk (0x1U << DSI_WPCR2_TCLKZERO2_Pos) 20877 #define DSI_WPCR2_TCLKZERO2 DSI_WPCR2_TCLKZERO2_Msk 20878 #define DSI_WPCR2_TCLKZERO3_Pos (11U) 20879 #define DSI_WPCR2_TCLKZERO3_Msk (0x1U << DSI_WPCR2_TCLKZERO3_Pos) 20880 #define DSI_WPCR2_TCLKZERO3 DSI_WPCR2_TCLKZERO3_Msk 20881 #define DSI_WPCR2_TCLKZERO4_Pos (12U) 20882 #define DSI_WPCR2_TCLKZERO4_Msk (0x1U << DSI_WPCR2_TCLKZERO4_Pos) 20883 #define DSI_WPCR2_TCLKZERO4 DSI_WPCR2_TCLKZERO4_Msk 20884 #define DSI_WPCR2_TCLKZERO5_Pos (13U) 20885 #define DSI_WPCR2_TCLKZERO5_Msk (0x1U << DSI_WPCR2_TCLKZERO5_Pos) 20886 #define DSI_WPCR2_TCLKZERO5 DSI_WPCR2_TCLKZERO5_Msk 20887 #define DSI_WPCR2_TCLKZERO6_Pos (14U) 20888 #define DSI_WPCR2_TCLKZERO6_Msk (0x1U << DSI_WPCR2_TCLKZERO6_Pos) 20889 #define DSI_WPCR2_TCLKZERO6 DSI_WPCR2_TCLKZERO6_Msk 20890 #define DSI_WPCR2_TCLKZERO7_Pos (15U) 20891 #define DSI_WPCR2_TCLKZERO7_Msk (0x1U << DSI_WPCR2_TCLKZERO7_Pos) 20892 #define DSI_WPCR2_TCLKZERO7 DSI_WPCR2_TCLKZERO7_Msk 20894 #define DSI_WPCR2_THSPREP_Pos (16U) 20895 #define DSI_WPCR2_THSPREP_Msk (0xFFU << DSI_WPCR2_THSPREP_Pos) 20896 #define DSI_WPCR2_THSPREP DSI_WPCR2_THSPREP_Msk 20897 #define DSI_WPCR2_THSPREP0_Pos (16U) 20898 #define DSI_WPCR2_THSPREP0_Msk (0x1U << DSI_WPCR2_THSPREP0_Pos) 20899 #define DSI_WPCR2_THSPREP0 DSI_WPCR2_THSPREP0_Msk 20900 #define DSI_WPCR2_THSPREP1_Pos (17U) 20901 #define DSI_WPCR2_THSPREP1_Msk (0x1U << DSI_WPCR2_THSPREP1_Pos) 20902 #define DSI_WPCR2_THSPREP1 DSI_WPCR2_THSPREP1_Msk 20903 #define DSI_WPCR2_THSPREP2_Pos (18U) 20904 #define DSI_WPCR2_THSPREP2_Msk (0x1U << DSI_WPCR2_THSPREP2_Pos) 20905 #define DSI_WPCR2_THSPREP2 DSI_WPCR2_THSPREP2_Msk 20906 #define DSI_WPCR2_THSPREP3_Pos (19U) 20907 #define DSI_WPCR2_THSPREP3_Msk (0x1U << DSI_WPCR2_THSPREP3_Pos) 20908 #define DSI_WPCR2_THSPREP3 DSI_WPCR2_THSPREP3_Msk 20909 #define DSI_WPCR2_THSPREP4_Pos (20U) 20910 #define DSI_WPCR2_THSPREP4_Msk (0x1U << DSI_WPCR2_THSPREP4_Pos) 20911 #define DSI_WPCR2_THSPREP4 DSI_WPCR2_THSPREP4_Msk 20912 #define DSI_WPCR2_THSPREP5_Pos (21U) 20913 #define DSI_WPCR2_THSPREP5_Msk (0x1U << DSI_WPCR2_THSPREP5_Pos) 20914 #define DSI_WPCR2_THSPREP5 DSI_WPCR2_THSPREP5_Msk 20915 #define DSI_WPCR2_THSPREP6_Pos (22U) 20916 #define DSI_WPCR2_THSPREP6_Msk (0x1U << DSI_WPCR2_THSPREP6_Pos) 20917 #define DSI_WPCR2_THSPREP6 DSI_WPCR2_THSPREP6_Msk 20918 #define DSI_WPCR2_THSPREP7_Pos (23U) 20919 #define DSI_WPCR2_THSPREP7_Msk (0x1U << DSI_WPCR2_THSPREP7_Pos) 20920 #define DSI_WPCR2_THSPREP7 DSI_WPCR2_THSPREP7_Msk 20922 #define DSI_WPCR2_THSTRAIL_Pos (24U) 20923 #define DSI_WPCR2_THSTRAIL_Msk (0xFFU << DSI_WPCR2_THSTRAIL_Pos) 20924 #define DSI_WPCR2_THSTRAIL DSI_WPCR2_THSTRAIL_Msk 20925 #define DSI_WPCR2_THSTRAIL0_Pos (24U) 20926 #define DSI_WPCR2_THSTRAIL0_Msk (0x1U << DSI_WPCR2_THSTRAIL0_Pos) 20927 #define DSI_WPCR2_THSTRAIL0 DSI_WPCR2_THSTRAIL0_Msk 20928 #define DSI_WPCR2_THSTRAIL1_Pos (25U) 20929 #define DSI_WPCR2_THSTRAIL1_Msk (0x1U << DSI_WPCR2_THSTRAIL1_Pos) 20930 #define DSI_WPCR2_THSTRAIL1 DSI_WPCR2_THSTRAIL1_Msk 20931 #define DSI_WPCR2_THSTRAIL2_Pos (26U) 20932 #define DSI_WPCR2_THSTRAIL2_Msk (0x1U << DSI_WPCR2_THSTRAIL2_Pos) 20933 #define DSI_WPCR2_THSTRAIL2 DSI_WPCR2_THSTRAIL2_Msk 20934 #define DSI_WPCR2_THSTRAIL3_Pos (27U) 20935 #define DSI_WPCR2_THSTRAIL3_Msk (0x1U << DSI_WPCR2_THSTRAIL3_Pos) 20936 #define DSI_WPCR2_THSTRAIL3 DSI_WPCR2_THSTRAIL3_Msk 20937 #define DSI_WPCR2_THSTRAIL4_Pos (28U) 20938 #define DSI_WPCR2_THSTRAIL4_Msk (0x1U << DSI_WPCR2_THSTRAIL4_Pos) 20939 #define DSI_WPCR2_THSTRAIL4 DSI_WPCR2_THSTRAIL4_Msk 20940 #define DSI_WPCR2_THSTRAIL5_Pos (29U) 20941 #define DSI_WPCR2_THSTRAIL5_Msk (0x1U << DSI_WPCR2_THSTRAIL5_Pos) 20942 #define DSI_WPCR2_THSTRAIL5 DSI_WPCR2_THSTRAIL5_Msk 20943 #define DSI_WPCR2_THSTRAIL6_Pos (30U) 20944 #define DSI_WPCR2_THSTRAIL6_Msk (0x1U << DSI_WPCR2_THSTRAIL6_Pos) 20945 #define DSI_WPCR2_THSTRAIL6 DSI_WPCR2_THSTRAIL6_Msk 20946 #define DSI_WPCR2_THSTRAIL7_Pos (31U) 20947 #define DSI_WPCR2_THSTRAIL7_Msk (0x1U << DSI_WPCR2_THSTRAIL7_Pos) 20948 #define DSI_WPCR2_THSTRAIL7 DSI_WPCR2_THSTRAIL7_Msk 20951 #define DSI_WPCR3_THSZERO_Pos (0U) 20952 #define DSI_WPCR3_THSZERO_Msk (0xFFU << DSI_WPCR3_THSZERO_Pos) 20953 #define DSI_WPCR3_THSZERO DSI_WPCR3_THSZERO_Msk 20954 #define DSI_WPCR3_THSZERO0_Pos (0U) 20955 #define DSI_WPCR3_THSZERO0_Msk (0x1U << DSI_WPCR3_THSZERO0_Pos) 20956 #define DSI_WPCR3_THSZERO0 DSI_WPCR3_THSZERO0_Msk 20957 #define DSI_WPCR3_THSZERO1_Pos (1U) 20958 #define DSI_WPCR3_THSZERO1_Msk (0x1U << DSI_WPCR3_THSZERO1_Pos) 20959 #define DSI_WPCR3_THSZERO1 DSI_WPCR3_THSZERO1_Msk 20960 #define DSI_WPCR3_THSZERO2_Pos (2U) 20961 #define DSI_WPCR3_THSZERO2_Msk (0x1U << DSI_WPCR3_THSZERO2_Pos) 20962 #define DSI_WPCR3_THSZERO2 DSI_WPCR3_THSZERO2_Msk 20963 #define DSI_WPCR3_THSZERO3_Pos (3U) 20964 #define DSI_WPCR3_THSZERO3_Msk (0x1U << DSI_WPCR3_THSZERO3_Pos) 20965 #define DSI_WPCR3_THSZERO3 DSI_WPCR3_THSZERO3_Msk 20966 #define DSI_WPCR3_THSZERO4_Pos (4U) 20967 #define DSI_WPCR3_THSZERO4_Msk (0x1U << DSI_WPCR3_THSZERO4_Pos) 20968 #define DSI_WPCR3_THSZERO4 DSI_WPCR3_THSZERO4_Msk 20969 #define DSI_WPCR3_THSZERO5_Pos (5U) 20970 #define DSI_WPCR3_THSZERO5_Msk (0x1U << DSI_WPCR3_THSZERO5_Pos) 20971 #define DSI_WPCR3_THSZERO5 DSI_WPCR3_THSZERO5_Msk 20972 #define DSI_WPCR3_THSZERO6_Pos (6U) 20973 #define DSI_WPCR3_THSZERO6_Msk (0x1U << DSI_WPCR3_THSZERO6_Pos) 20974 #define DSI_WPCR3_THSZERO6 DSI_WPCR3_THSZERO6_Msk 20975 #define DSI_WPCR3_THSZERO7_Pos (7U) 20976 #define DSI_WPCR3_THSZERO7_Msk (0x1U << DSI_WPCR3_THSZERO7_Pos) 20977 #define DSI_WPCR3_THSZERO7 DSI_WPCR3_THSZERO7_Msk 20979 #define DSI_WPCR3_TLPXD_Pos (8U) 20980 #define DSI_WPCR3_TLPXD_Msk (0xFFU << DSI_WPCR3_TLPXD_Pos) 20981 #define DSI_WPCR3_TLPXD DSI_WPCR3_TLPXD_Msk 20982 #define DSI_WPCR3_TLPXD0_Pos (8U) 20983 #define DSI_WPCR3_TLPXD0_Msk (0x1U << DSI_WPCR3_TLPXD0_Pos) 20984 #define DSI_WPCR3_TLPXD0 DSI_WPCR3_TLPXD0_Msk 20985 #define DSI_WPCR3_TLPXD1_Pos (9U) 20986 #define DSI_WPCR3_TLPXD1_Msk (0x1U << DSI_WPCR3_TLPXD1_Pos) 20987 #define DSI_WPCR3_TLPXD1 DSI_WPCR3_TLPXD1_Msk 20988 #define DSI_WPCR3_TLPXD2_Pos (10U) 20989 #define DSI_WPCR3_TLPXD2_Msk (0x1U << DSI_WPCR3_TLPXD2_Pos) 20990 #define DSI_WPCR3_TLPXD2 DSI_WPCR3_TLPXD2_Msk 20991 #define DSI_WPCR3_TLPXD3_Pos (11U) 20992 #define DSI_WPCR3_TLPXD3_Msk (0x1U << DSI_WPCR3_TLPXD3_Pos) 20993 #define DSI_WPCR3_TLPXD3 DSI_WPCR3_TLPXD3_Msk 20994 #define DSI_WPCR3_TLPXD4_Pos (12U) 20995 #define DSI_WPCR3_TLPXD4_Msk (0x1U << DSI_WPCR3_TLPXD4_Pos) 20996 #define DSI_WPCR3_TLPXD4 DSI_WPCR3_TLPXD4_Msk 20997 #define DSI_WPCR3_TLPXD5_Pos (13U) 20998 #define DSI_WPCR3_TLPXD5_Msk (0x1U << DSI_WPCR3_TLPXD5_Pos) 20999 #define DSI_WPCR3_TLPXD5 DSI_WPCR3_TLPXD5_Msk 21000 #define DSI_WPCR3_TLPXD6_Pos (14U) 21001 #define DSI_WPCR3_TLPXD6_Msk (0x1U << DSI_WPCR3_TLPXD6_Pos) 21002 #define DSI_WPCR3_TLPXD6 DSI_WPCR3_TLPXD6_Msk 21003 #define DSI_WPCR3_TLPXD7_Pos (15U) 21004 #define DSI_WPCR3_TLPXD7_Msk (0x1U << DSI_WPCR3_TLPXD7_Pos) 21005 #define DSI_WPCR3_TLPXD7 DSI_WPCR3_TLPXD7_Msk 21007 #define DSI_WPCR3_THSEXIT_Pos (16U) 21008 #define DSI_WPCR3_THSEXIT_Msk (0xFFU << DSI_WPCR3_THSEXIT_Pos) 21009 #define DSI_WPCR3_THSEXIT DSI_WPCR3_THSEXIT_Msk 21010 #define DSI_WPCR3_THSEXIT0_Pos (16U) 21011 #define DSI_WPCR3_THSEXIT0_Msk (0x1U << DSI_WPCR3_THSEXIT0_Pos) 21012 #define DSI_WPCR3_THSEXIT0 DSI_WPCR3_THSEXIT0_Msk 21013 #define DSI_WPCR3_THSEXIT1_Pos (17U) 21014 #define DSI_WPCR3_THSEXIT1_Msk (0x1U << DSI_WPCR3_THSEXIT1_Pos) 21015 #define DSI_WPCR3_THSEXIT1 DSI_WPCR3_THSEXIT1_Msk 21016 #define DSI_WPCR3_THSEXIT2_Pos (18U) 21017 #define DSI_WPCR3_THSEXIT2_Msk (0x1U << DSI_WPCR3_THSEXIT2_Pos) 21018 #define DSI_WPCR3_THSEXIT2 DSI_WPCR3_THSEXIT2_Msk 21019 #define DSI_WPCR3_THSEXIT3_Pos (19U) 21020 #define DSI_WPCR3_THSEXIT3_Msk (0x1U << DSI_WPCR3_THSEXIT3_Pos) 21021 #define DSI_WPCR3_THSEXIT3 DSI_WPCR3_THSEXIT3_Msk 21022 #define DSI_WPCR3_THSEXIT4_Pos (20U) 21023 #define DSI_WPCR3_THSEXIT4_Msk (0x1U << DSI_WPCR3_THSEXIT4_Pos) 21024 #define DSI_WPCR3_THSEXIT4 DSI_WPCR3_THSEXIT4_Msk 21025 #define DSI_WPCR3_THSEXIT5_Pos (21U) 21026 #define DSI_WPCR3_THSEXIT5_Msk (0x1U << DSI_WPCR3_THSEXIT5_Pos) 21027 #define DSI_WPCR3_THSEXIT5 DSI_WPCR3_THSEXIT5_Msk 21028 #define DSI_WPCR3_THSEXIT6_Pos (22U) 21029 #define DSI_WPCR3_THSEXIT6_Msk (0x1U << DSI_WPCR3_THSEXIT6_Pos) 21030 #define DSI_WPCR3_THSEXIT6 DSI_WPCR3_THSEXIT6_Msk 21031 #define DSI_WPCR3_THSEXIT7_Pos (23U) 21032 #define DSI_WPCR3_THSEXIT7_Msk (0x1U << DSI_WPCR3_THSEXIT7_Pos) 21033 #define DSI_WPCR3_THSEXIT7 DSI_WPCR3_THSEXIT7_Msk 21035 #define DSI_WPCR3_TLPXC_Pos (24U) 21036 #define DSI_WPCR3_TLPXC_Msk (0xFFU << DSI_WPCR3_TLPXC_Pos) 21037 #define DSI_WPCR3_TLPXC DSI_WPCR3_TLPXC_Msk 21038 #define DSI_WPCR3_TLPXC0_Pos (24U) 21039 #define DSI_WPCR3_TLPXC0_Msk (0x1U << DSI_WPCR3_TLPXC0_Pos) 21040 #define DSI_WPCR3_TLPXC0 DSI_WPCR3_TLPXC0_Msk 21041 #define DSI_WPCR3_TLPXC1_Pos (25U) 21042 #define DSI_WPCR3_TLPXC1_Msk (0x1U << DSI_WPCR3_TLPXC1_Pos) 21043 #define DSI_WPCR3_TLPXC1 DSI_WPCR3_TLPXC1_Msk 21044 #define DSI_WPCR3_TLPXC2_Pos (26U) 21045 #define DSI_WPCR3_TLPXC2_Msk (0x1U << DSI_WPCR3_TLPXC2_Pos) 21046 #define DSI_WPCR3_TLPXC2 DSI_WPCR3_TLPXC2_Msk 21047 #define DSI_WPCR3_TLPXC3_Pos (27U) 21048 #define DSI_WPCR3_TLPXC3_Msk (0x1U << DSI_WPCR3_TLPXC3_Pos) 21049 #define DSI_WPCR3_TLPXC3 DSI_WPCR3_TLPXC3_Msk 21050 #define DSI_WPCR3_TLPXC4_Pos (28U) 21051 #define DSI_WPCR3_TLPXC4_Msk (0x1U << DSI_WPCR3_TLPXC4_Pos) 21052 #define DSI_WPCR3_TLPXC4 DSI_WPCR3_TLPXC4_Msk 21053 #define DSI_WPCR3_TLPXC5_Pos (29U) 21054 #define DSI_WPCR3_TLPXC5_Msk (0x1U << DSI_WPCR3_TLPXC5_Pos) 21055 #define DSI_WPCR3_TLPXC5 DSI_WPCR3_TLPXC5_Msk 21056 #define DSI_WPCR3_TLPXC6_Pos (30U) 21057 #define DSI_WPCR3_TLPXC6_Msk (0x1U << DSI_WPCR3_TLPXC6_Pos) 21058 #define DSI_WPCR3_TLPXC6 DSI_WPCR3_TLPXC6_Msk 21059 #define DSI_WPCR3_TLPXC7_Pos (31U) 21060 #define DSI_WPCR3_TLPXC7_Msk (0x1U << DSI_WPCR3_TLPXC7_Pos) 21061 #define DSI_WPCR3_TLPXC7 DSI_WPCR3_TLPXC7_Msk 21064 #define DSI_WPCR4_TCLKPOST_Pos (0U) 21065 #define DSI_WPCR4_TCLKPOST_Msk (0xFFU << DSI_WPCR4_TCLKPOST_Pos) 21066 #define DSI_WPCR4_TCLKPOST DSI_WPCR4_TCLKPOST_Msk 21067 #define DSI_WPCR4_TCLKPOST0_Pos (0U) 21068 #define DSI_WPCR4_TCLKPOST0_Msk (0x1U << DSI_WPCR4_TCLKPOST0_Pos) 21069 #define DSI_WPCR4_TCLKPOST0 DSI_WPCR4_TCLKPOST0_Msk 21070 #define DSI_WPCR4_TCLKPOST1_Pos (1U) 21071 #define DSI_WPCR4_TCLKPOST1_Msk (0x1U << DSI_WPCR4_TCLKPOST1_Pos) 21072 #define DSI_WPCR4_TCLKPOST1 DSI_WPCR4_TCLKPOST1_Msk 21073 #define DSI_WPCR4_TCLKPOST2_Pos (2U) 21074 #define DSI_WPCR4_TCLKPOST2_Msk (0x1U << DSI_WPCR4_TCLKPOST2_Pos) 21075 #define DSI_WPCR4_TCLKPOST2 DSI_WPCR4_TCLKPOST2_Msk 21076 #define DSI_WPCR4_TCLKPOST3_Pos (3U) 21077 #define DSI_WPCR4_TCLKPOST3_Msk (0x1U << DSI_WPCR4_TCLKPOST3_Pos) 21078 #define DSI_WPCR4_TCLKPOST3 DSI_WPCR4_TCLKPOST3_Msk 21079 #define DSI_WPCR4_TCLKPOST4_Pos (4U) 21080 #define DSI_WPCR4_TCLKPOST4_Msk (0x1U << DSI_WPCR4_TCLKPOST4_Pos) 21081 #define DSI_WPCR4_TCLKPOST4 DSI_WPCR4_TCLKPOST4_Msk 21082 #define DSI_WPCR4_TCLKPOST5_Pos (5U) 21083 #define DSI_WPCR4_TCLKPOST5_Msk (0x1U << DSI_WPCR4_TCLKPOST5_Pos) 21084 #define DSI_WPCR4_TCLKPOST5 DSI_WPCR4_TCLKPOST5_Msk 21085 #define DSI_WPCR4_TCLKPOST6_Pos (6U) 21086 #define DSI_WPCR4_TCLKPOST6_Msk (0x1U << DSI_WPCR4_TCLKPOST6_Pos) 21087 #define DSI_WPCR4_TCLKPOST6 DSI_WPCR4_TCLKPOST6_Msk 21088 #define DSI_WPCR4_TCLKPOST7_Pos (7U) 21089 #define DSI_WPCR4_TCLKPOST7_Msk (0x1U << DSI_WPCR4_TCLKPOST7_Pos) 21090 #define DSI_WPCR4_TCLKPOST7 DSI_WPCR4_TCLKPOST7_Msk 21093 #define DSI_WRPCR_PLLEN_Pos (0U) 21094 #define DSI_WRPCR_PLLEN_Msk (0x1U << DSI_WRPCR_PLLEN_Pos) 21095 #define DSI_WRPCR_PLLEN DSI_WRPCR_PLLEN_Msk 21096 #define DSI_WRPCR_PLL_NDIV_Pos (2U) 21097 #define DSI_WRPCR_PLL_NDIV_Msk (0x7FU << DSI_WRPCR_PLL_NDIV_Pos) 21098 #define DSI_WRPCR_PLL_NDIV DSI_WRPCR_PLL_NDIV_Msk 21099 #define DSI_WRPCR_PLL_NDIV0_Pos (2U) 21100 #define DSI_WRPCR_PLL_NDIV0_Msk (0x1U << DSI_WRPCR_PLL_NDIV0_Pos) 21101 #define DSI_WRPCR_PLL_NDIV0 DSI_WRPCR_PLL_NDIV0_Msk 21102 #define DSI_WRPCR_PLL_NDIV1_Pos (3U) 21103 #define DSI_WRPCR_PLL_NDIV1_Msk (0x1U << DSI_WRPCR_PLL_NDIV1_Pos) 21104 #define DSI_WRPCR_PLL_NDIV1 DSI_WRPCR_PLL_NDIV1_Msk 21105 #define DSI_WRPCR_PLL_NDIV2_Pos (4U) 21106 #define DSI_WRPCR_PLL_NDIV2_Msk (0x1U << DSI_WRPCR_PLL_NDIV2_Pos) 21107 #define DSI_WRPCR_PLL_NDIV2 DSI_WRPCR_PLL_NDIV2_Msk 21108 #define DSI_WRPCR_PLL_NDIV3_Pos (5U) 21109 #define DSI_WRPCR_PLL_NDIV3_Msk (0x1U << DSI_WRPCR_PLL_NDIV3_Pos) 21110 #define DSI_WRPCR_PLL_NDIV3 DSI_WRPCR_PLL_NDIV3_Msk 21111 #define DSI_WRPCR_PLL_NDIV4_Pos (6U) 21112 #define DSI_WRPCR_PLL_NDIV4_Msk (0x1U << DSI_WRPCR_PLL_NDIV4_Pos) 21113 #define DSI_WRPCR_PLL_NDIV4 DSI_WRPCR_PLL_NDIV4_Msk 21114 #define DSI_WRPCR_PLL_NDIV5_Pos (7U) 21115 #define DSI_WRPCR_PLL_NDIV5_Msk (0x1U << DSI_WRPCR_PLL_NDIV5_Pos) 21116 #define DSI_WRPCR_PLL_NDIV5 DSI_WRPCR_PLL_NDIV5_Msk 21117 #define DSI_WRPCR_PLL_NDIV6_Pos (8U) 21118 #define DSI_WRPCR_PLL_NDIV6_Msk (0x1U << DSI_WRPCR_PLL_NDIV6_Pos) 21119 #define DSI_WRPCR_PLL_NDIV6 DSI_WRPCR_PLL_NDIV6_Msk 21121 #define DSI_WRPCR_PLL_IDF_Pos (11U) 21122 #define DSI_WRPCR_PLL_IDF_Msk (0xFU << DSI_WRPCR_PLL_IDF_Pos) 21123 #define DSI_WRPCR_PLL_IDF DSI_WRPCR_PLL_IDF_Msk 21124 #define DSI_WRPCR_PLL_IDF0_Pos (11U) 21125 #define DSI_WRPCR_PLL_IDF0_Msk (0x1U << DSI_WRPCR_PLL_IDF0_Pos) 21126 #define DSI_WRPCR_PLL_IDF0 DSI_WRPCR_PLL_IDF0_Msk 21127 #define DSI_WRPCR_PLL_IDF1_Pos (12U) 21128 #define DSI_WRPCR_PLL_IDF1_Msk (0x1U << DSI_WRPCR_PLL_IDF1_Pos) 21129 #define DSI_WRPCR_PLL_IDF1 DSI_WRPCR_PLL_IDF1_Msk 21130 #define DSI_WRPCR_PLL_IDF2_Pos (13U) 21131 #define DSI_WRPCR_PLL_IDF2_Msk (0x1U << DSI_WRPCR_PLL_IDF2_Pos) 21132 #define DSI_WRPCR_PLL_IDF2 DSI_WRPCR_PLL_IDF2_Msk 21133 #define DSI_WRPCR_PLL_IDF3_Pos (14U) 21134 #define DSI_WRPCR_PLL_IDF3_Msk (0x1U << DSI_WRPCR_PLL_IDF3_Pos) 21135 #define DSI_WRPCR_PLL_IDF3 DSI_WRPCR_PLL_IDF3_Msk 21137 #define DSI_WRPCR_PLL_ODF_Pos (16U) 21138 #define DSI_WRPCR_PLL_ODF_Msk (0x3U << DSI_WRPCR_PLL_ODF_Pos) 21139 #define DSI_WRPCR_PLL_ODF DSI_WRPCR_PLL_ODF_Msk 21140 #define DSI_WRPCR_PLL_ODF0_Pos (16U) 21141 #define DSI_WRPCR_PLL_ODF0_Msk (0x1U << DSI_WRPCR_PLL_ODF0_Pos) 21142 #define DSI_WRPCR_PLL_ODF0 DSI_WRPCR_PLL_ODF0_Msk 21143 #define DSI_WRPCR_PLL_ODF1_Pos (17U) 21144 #define DSI_WRPCR_PLL_ODF1_Msk (0x1U << DSI_WRPCR_PLL_ODF1_Pos) 21145 #define DSI_WRPCR_PLL_ODF1 DSI_WRPCR_PLL_ODF1_Msk 21147 #define DSI_WRPCR_REGEN_Pos (24U) 21148 #define DSI_WRPCR_REGEN_Msk (0x1U << DSI_WRPCR_REGEN_Pos) 21149 #define DSI_WRPCR_REGEN DSI_WRPCR_REGEN_Msk 21164 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \ 21165 ((__INSTANCE__) == ADC2) || \ 21166 ((__INSTANCE__) == ADC3)) 21167 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 21169 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON) 21172 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \ 21173 ((__INSTANCE__) == CAN2) || \ 21174 ((__INSTANCE__) == CAN3)) 21176 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC) 21179 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1) 21182 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) 21185 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \ 21186 ((INSTANCE) == DFSDM1_Filter1) || \ 21187 ((INSTANCE) == DFSDM1_Filter2) || \ 21188 ((INSTANCE) == DFSDM1_Filter3)) 21190 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \ 21191 ((INSTANCE) == DFSDM1_Channel1) || \ 21192 ((INSTANCE) == DFSDM1_Channel2) || \ 21193 ((INSTANCE) == DFSDM1_Channel3) || \ 21194 ((INSTANCE) == DFSDM1_Channel4) || \ 21195 ((INSTANCE) == DFSDM1_Channel5) || \ 21196 ((INSTANCE) == DFSDM1_Channel6) || \ 21197 ((INSTANCE) == DFSDM1_Channel7)) 21200 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) 21203 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \ 21204 ((__INSTANCE__) == DMA1_Stream1) || \ 21205 ((__INSTANCE__) == DMA1_Stream2) || \ 21206 ((__INSTANCE__) == DMA1_Stream3) || \ 21207 ((__INSTANCE__) == DMA1_Stream4) || \ 21208 ((__INSTANCE__) == DMA1_Stream5) || \ 21209 ((__INSTANCE__) == DMA1_Stream6) || \ 21210 ((__INSTANCE__) == DMA1_Stream7) || \ 21211 ((__INSTANCE__) == DMA2_Stream0) || \ 21212 ((__INSTANCE__) == DMA2_Stream1) || \ 21213 ((__INSTANCE__) == DMA2_Stream2) || \ 21214 ((__INSTANCE__) == DMA2_Stream3) || \ 21215 ((__INSTANCE__) == DMA2_Stream4) || \ 21216 ((__INSTANCE__) == DMA2_Stream5) || \ 21217 ((__INSTANCE__) == DMA2_Stream6) || \ 21218 ((__INSTANCE__) == DMA2_Stream7)) 21221 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \ 21222 ((__INSTANCE__) == GPIOB) || \ 21223 ((__INSTANCE__) == GPIOC) || \ 21224 ((__INSTANCE__) == GPIOD) || \ 21225 ((__INSTANCE__) == GPIOE) || \ 21226 ((__INSTANCE__) == GPIOF) || \ 21227 ((__INSTANCE__) == GPIOG) || \ 21228 ((__INSTANCE__) == GPIOH) || \ 21229 ((__INSTANCE__) == GPIOI) || \ 21230 ((__INSTANCE__) == GPIOJ) || \ 21231 ((__INSTANCE__) == GPIOK)) 21233 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \ 21234 ((__INSTANCE__) == GPIOB) || \ 21235 ((__INSTANCE__) == GPIOC) || \ 21236 ((__INSTANCE__) == GPIOD) || \ 21237 ((__INSTANCE__) == GPIOE) || \ 21238 ((__INSTANCE__) == GPIOF) || \ 21239 ((__INSTANCE__) == GPIOG) || \ 21240 ((__INSTANCE__) == GPIOH) || \ 21241 ((__INSTANCE__) == GPIOI) || \ 21242 ((__INSTANCE__) == GPIOJ) || \ 21243 ((__INSTANCE__) == GPIOK)) 21246 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) 21249 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI) 21253 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \ 21254 ((__INSTANCE__) == I2C2) || \ 21255 ((__INSTANCE__) == I2C3) || \ 21256 ((__INSTANCE__) == I2C4)) 21259 #define IS_SMBUS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \ 21260 ((__INSTANCE__) == I2C2) || \ 21261 ((__INSTANCE__) == I2C3) || \ 21262 ((__INSTANCE__) == I2C4)) 21266 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \ 21267 ((__INSTANCE__) == SPI2) || \ 21268 ((__INSTANCE__) == SPI3)) 21271 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1) 21274 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC) 21277 #define IS_MDIOS_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == MDIOS) 21280 #define IS_JPEG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == JPEG) 21284 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG) 21287 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC) 21290 #define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \ 21291 ((__PERIPH__) == SAI1_Block_B) || \ 21292 ((__PERIPH__) == SAI2_Block_A) || \ 21293 ((__PERIPH__) == SAI2_Block_B)) 21295 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE 21298 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \ 21299 ((__INSTANCE__) == SDMMC2)) 21302 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX) 21305 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \ 21306 ((__INSTANCE__) == SPI2) || \ 21307 ((__INSTANCE__) == SPI3) || \ 21308 ((__INSTANCE__) == SPI4) || \ 21309 ((__INSTANCE__) == SPI5) || \ 21310 ((__INSTANCE__) == SPI6)) 21313 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21314 ((__INSTANCE__) == TIM2) || \ 21315 ((__INSTANCE__) == TIM3) || \ 21316 ((__INSTANCE__) == TIM4) || \ 21317 ((__INSTANCE__) == TIM5) || \ 21318 ((__INSTANCE__) == TIM6) || \ 21319 ((__INSTANCE__) == TIM7) || \ 21320 ((__INSTANCE__) == TIM8) || \ 21321 ((__INSTANCE__) == TIM9) || \ 21322 ((__INSTANCE__) == TIM10) || \ 21323 ((__INSTANCE__) == TIM11) || \ 21324 ((__INSTANCE__) == TIM12) || \ 21325 ((__INSTANCE__) == TIM13) || \ 21326 ((__INSTANCE__) == TIM14)) 21329 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \ 21330 ((__INSTANCE__) == TIM5)) 21333 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 21334 ((INSTANCE) == TIM8)) 21337 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 21338 ((INSTANCE) == TIM8)) 21341 #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 21342 ((INSTANCE) == TIM8)) 21345 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21346 ((__INSTANCE__) == TIM2) || \ 21347 ((__INSTANCE__) == TIM3) || \ 21348 ((__INSTANCE__) == TIM4) || \ 21349 ((__INSTANCE__) == TIM5) || \ 21350 ((__INSTANCE__) == TIM8) || \ 21351 ((__INSTANCE__) == TIM9) || \ 21352 ((__INSTANCE__) == TIM10) || \ 21353 ((__INSTANCE__) == TIM11) || \ 21354 ((__INSTANCE__) == TIM12) || \ 21355 ((__INSTANCE__) == TIM13) || \ 21356 ((__INSTANCE__) == TIM14)) 21359 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21360 ((__INSTANCE__) == TIM2) || \ 21361 ((__INSTANCE__) == TIM3) || \ 21362 ((__INSTANCE__) == TIM4) || \ 21363 ((__INSTANCE__) == TIM5) || \ 21364 ((__INSTANCE__) == TIM8) || \ 21365 ((__INSTANCE__) == TIM9) || \ 21366 ((__INSTANCE__) == TIM12)) 21369 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21370 ((__INSTANCE__) == TIM2) || \ 21371 ((__INSTANCE__) == TIM3) || \ 21372 ((__INSTANCE__) == TIM4) || \ 21373 ((__INSTANCE__) == TIM5) || \ 21374 ((__INSTANCE__) == TIM8)) 21377 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21378 ((__INSTANCE__) == TIM2) || \ 21379 ((__INSTANCE__) == TIM3) || \ 21380 ((__INSTANCE__) == TIM4) || \ 21381 ((__INSTANCE__) == TIM5) || \ 21382 ((__INSTANCE__) == TIM8)) 21385 #define IS_TIM_CC5_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21386 ((__INSTANCE__) == TIM8)) 21389 #define IS_TIM_CC6_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21390 ((__INSTANCE__) == TIM8)) 21393 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21394 ((__INSTANCE__) == TIM8)) 21397 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21398 ((__INSTANCE__) == TIM8) || \ 21399 ((__INSTANCE__) == TIM2) || \ 21400 ((__INSTANCE__) == TIM3) || \ 21401 ((__INSTANCE__) == TIM4) || \ 21402 ((__INSTANCE__) == TIM5) || \ 21403 ((__INSTANCE__) == TIM6) || \ 21404 ((__INSTANCE__) == TIM7)) 21407 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21408 ((__INSTANCE__) == TIM2) || \ 21409 ((__INSTANCE__) == TIM3) || \ 21410 ((__INSTANCE__) == TIM4) || \ 21411 ((__INSTANCE__) == TIM5) || \ 21412 ((__INSTANCE__) == TIM8)) 21415 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21416 ((__INSTANCE__) == TIM2) || \ 21417 ((__INSTANCE__) == TIM3) || \ 21418 ((__INSTANCE__) == TIM4) || \ 21419 ((__INSTANCE__) == TIM5) || \ 21420 ((__INSTANCE__) == TIM8)) 21423 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \ 21424 (((__INSTANCE__) == TIM1) || \ 21425 ((__INSTANCE__) == TIM8)) 21428 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21429 ((__INSTANCE__) == TIM2) || \ 21430 ((__INSTANCE__) == TIM3) || \ 21431 ((__INSTANCE__) == TIM4) || \ 21432 ((__INSTANCE__) == TIM5) || \ 21433 ((__INSTANCE__) == TIM8)) 21436 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21437 ((__INSTANCE__) == TIM2) || \ 21438 ((__INSTANCE__) == TIM3) || \ 21439 ((__INSTANCE__) == TIM4) || \ 21440 ((__INSTANCE__) == TIM5) || \ 21441 ((__INSTANCE__) == TIM8)) 21444 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\ 21445 (((__INSTANCE__) == TIM2) || \ 21446 ((__INSTANCE__) == TIM3) || \ 21447 ((__INSTANCE__) == TIM4) || \ 21448 ((__INSTANCE__) == TIM5)) 21451 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\ 21452 (((__INSTANCE__) == TIM1) || \ 21453 ((__INSTANCE__) == TIM2) || \ 21454 ((__INSTANCE__) == TIM3) || \ 21455 ((__INSTANCE__) == TIM4) || \ 21456 ((__INSTANCE__) == TIM5) || \ 21457 ((__INSTANCE__) == TIM8)) 21460 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\ 21461 (((__INSTANCE__) == TIM1) || \ 21462 ((__INSTANCE__) == TIM2) || \ 21463 ((__INSTANCE__) == TIM3) || \ 21464 ((__INSTANCE__) == TIM4) || \ 21465 ((__INSTANCE__) == TIM5) || \ 21466 ((__INSTANCE__) == TIM8)) 21469 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21470 ((__INSTANCE__) == TIM8)) 21473 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21474 ((__INSTANCE__) == TIM2) || \ 21475 ((__INSTANCE__) == TIM3) || \ 21476 ((__INSTANCE__) == TIM4) || \ 21477 ((__INSTANCE__) == TIM5) || \ 21478 ((__INSTANCE__) == TIM8)) 21481 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21482 ((__INSTANCE__) == TIM2) || \ 21483 ((__INSTANCE__) == TIM3) || \ 21484 ((__INSTANCE__) == TIM4) || \ 21485 ((__INSTANCE__) == TIM5) || \ 21486 ((__INSTANCE__) == TIM6) || \ 21487 ((__INSTANCE__) == TIM7) || \ 21488 ((__INSTANCE__) == TIM8)) 21491 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21492 ((__INSTANCE__) == TIM2) || \ 21493 ((__INSTANCE__) == TIM3) || \ 21494 ((__INSTANCE__) == TIM4) || \ 21495 ((__INSTANCE__) == TIM5) || \ 21496 ((__INSTANCE__) == TIM8) || \ 21497 ((__INSTANCE__) == TIM9) || \ 21498 ((__INSTANCE__) == TIM12)) 21501 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21502 ((__INSTANCE__) == TIM2) || \ 21503 ((__INSTANCE__) == TIM3) || \ 21504 ((__INSTANCE__) == TIM4) || \ 21505 ((__INSTANCE__) == TIM5) || \ 21506 ((__INSTANCE__) == TIM8)) 21509 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \ 21510 ((__INSTANCE__) == TIM5) || \ 21511 ((__INSTANCE__) == TIM11)) 21514 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \ 21515 ((((__INSTANCE__) == TIM1) && \ 21516 (((__CHANNEL__) == TIM_CHANNEL_1) || \ 21517 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 21518 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 21519 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 21520 ((__CHANNEL__) == TIM_CHANNEL_5) || \ 21521 ((__CHANNEL__) == TIM_CHANNEL_6))) \ 21523 (((__INSTANCE__) == TIM2) && \ 21524 (((__CHANNEL__) == TIM_CHANNEL_1) || \ 21525 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 21526 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 21527 ((__CHANNEL__) == TIM_CHANNEL_4))) \ 21529 (((__INSTANCE__) == TIM3) && \ 21530 (((__CHANNEL__) == TIM_CHANNEL_1) || \ 21531 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 21532 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 21533 ((__CHANNEL__) == TIM_CHANNEL_4))) \ 21535 (((__INSTANCE__) == TIM4) && \ 21536 (((__CHANNEL__) == TIM_CHANNEL_1) || \ 21537 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 21538 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 21539 ((__CHANNEL__) == TIM_CHANNEL_4))) \ 21541 (((__INSTANCE__) == TIM5) && \ 21542 (((__CHANNEL__) == TIM_CHANNEL_1) || \ 21543 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 21544 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 21545 ((__CHANNEL__) == TIM_CHANNEL_4))) \ 21547 (((__INSTANCE__) == TIM8) && \ 21548 (((__CHANNEL__) == TIM_CHANNEL_1) || \ 21549 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 21550 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 21551 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 21552 ((__CHANNEL__) == TIM_CHANNEL_5) || \ 21553 ((__CHANNEL__) == TIM_CHANNEL_6))) \ 21555 (((__INSTANCE__) == TIM9) && \ 21556 (((__CHANNEL__) == TIM_CHANNEL_1) || \ 21557 ((__CHANNEL__) == TIM_CHANNEL_2))) \ 21559 (((__INSTANCE__) == TIM10) && \ 21560 (((__CHANNEL__) == TIM_CHANNEL_1))) \ 21562 (((__INSTANCE__) == TIM11) && \ 21563 (((__CHANNEL__) == TIM_CHANNEL_1))) \ 21565 (((__INSTANCE__) == TIM12) && \ 21566 (((__CHANNEL__) == TIM_CHANNEL_1) || \ 21567 ((__CHANNEL__) == TIM_CHANNEL_2))) \ 21569 (((__INSTANCE__) == TIM13) && \ 21570 (((__CHANNEL__) == TIM_CHANNEL_1))) \ 21572 (((__INSTANCE__) == TIM14) && \ 21573 (((__CHANNEL__) == TIM_CHANNEL_1)))) 21576 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \ 21577 ((((__INSTANCE__) == TIM1) && \ 21578 (((__CHANNEL__) == TIM_CHANNEL_1) || \ 21579 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 21580 ((__CHANNEL__) == TIM_CHANNEL_3))) \ 21582 (((__INSTANCE__) == TIM8) && \ 21583 (((__CHANNEL__) == TIM_CHANNEL_1) || \ 21584 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 21585 ((__CHANNEL__) == TIM_CHANNEL_3)))) 21588 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\ 21589 (((__INSTANCE__) == TIM1) || \ 21590 ((__INSTANCE__) == TIM8) ) 21593 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\ 21594 (((__INSTANCE__) == TIM1) || \ 21595 ((__INSTANCE__) == TIM2) || \ 21596 ((__INSTANCE__) == TIM3) || \ 21597 ((__INSTANCE__) == TIM4) || \ 21598 ((__INSTANCE__) == TIM5) || \ 21599 ((__INSTANCE__) == TIM6) || \ 21600 ((__INSTANCE__) == TIM7) || \ 21601 ((__INSTANCE__) == TIM8)) 21604 #define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21605 ((__INSTANCE__) == TIM2) || \ 21606 ((__INSTANCE__) == TIM3) || \ 21607 ((__INSTANCE__) == TIM4) || \ 21608 ((__INSTANCE__) == TIM5) || \ 21609 ((__INSTANCE__) == TIM8) || \ 21610 ((__INSTANCE__) == TIM9) || \ 21611 ((__INSTANCE__) == TIM10) || \ 21612 ((__INSTANCE__) == TIM11) || \ 21613 ((__INSTANCE__) == TIM12) || \ 21614 ((__INSTANCE__) == TIM13) || \ 21615 ((__INSTANCE__) == TIM14)) 21618 #define IS_TIM_REPETITION_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21619 ((__INSTANCE__) == TIM8)) 21622 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21623 ((__INSTANCE__) == TIM2) || \ 21624 ((__INSTANCE__) == TIM3) || \ 21625 ((__INSTANCE__) == TIM4) || \ 21626 ((__INSTANCE__) == TIM5) || \ 21627 ((__INSTANCE__) == TIM8) || \ 21628 ((__INSTANCE__) == TIM9) || \ 21629 ((__INSTANCE__) == TIM12)) 21632 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21633 ((__INSTANCE__) == TIM2) || \ 21634 ((__INSTANCE__) == TIM3) || \ 21635 ((__INSTANCE__) == TIM4) || \ 21636 ((__INSTANCE__) == TIM5) || \ 21637 ((__INSTANCE__) == TIM8)) 21640 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21641 ((__INSTANCE__) == TIM2) || \ 21642 ((__INSTANCE__) == TIM3) || \ 21643 ((__INSTANCE__) == TIM4) || \ 21644 ((__INSTANCE__) == TIM5) || \ 21645 ((__INSTANCE__) == TIM8)) 21648 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \ 21649 ((__INSTANCE__) == TIM8)) 21652 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \ 21653 ((__INSTANCE__) == USART2) || \ 21654 ((__INSTANCE__) == USART3) || \ 21655 ((__INSTANCE__) == USART6)) 21658 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \ 21659 ((__INSTANCE__) == USART2) || \ 21660 ((__INSTANCE__) == USART3) || \ 21661 ((__INSTANCE__) == UART4) || \ 21662 ((__INSTANCE__) == UART5) || \ 21663 ((__INSTANCE__) == USART6) || \ 21664 ((__INSTANCE__) == UART7) || \ 21665 ((__INSTANCE__) == UART8)) 21668 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \ 21669 ((__INSTANCE__) == USART2) || \ 21670 ((__INSTANCE__) == USART3) || \ 21671 ((__INSTANCE__) == USART6)) 21674 #define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \ 21675 ((__INSTANCE__) == USART2) || \ 21676 ((__INSTANCE__) == USART3) || \ 21677 ((__INSTANCE__) == UART4) || \ 21678 ((__INSTANCE__) == UART5) || \ 21679 ((__INSTANCE__) == USART6) || \ 21680 ((__INSTANCE__) == UART7) || \ 21681 ((__INSTANCE__) == UART8)) 21684 #define IS_UART_HALFDUPLEX_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \ 21685 ((__INSTANCE__) == USART2) || \ 21686 ((__INSTANCE__) == USART3) || \ 21687 ((__INSTANCE__) == UART4) || \ 21688 ((__INSTANCE__) == UART5) || \ 21689 ((__INSTANCE__) == USART6) || \ 21690 ((__INSTANCE__) == UART7) || \ 21691 ((__INSTANCE__) == UART8)) 21694 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \ 21695 ((__INSTANCE__) == USART2) || \ 21696 ((__INSTANCE__) == USART3) || \ 21697 ((__INSTANCE__) == UART4) || \ 21698 ((__INSTANCE__) == UART5) || \ 21699 ((__INSTANCE__) == USART6) || \ 21700 ((__INSTANCE__) == UART7) || \ 21701 ((__INSTANCE__) == UART8)) 21704 #define IS_UART_LIN_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \ 21705 ((__INSTANCE__) == USART2) || \ 21706 ((__INSTANCE__) == USART3) || \ 21707 ((__INSTANCE__) == UART4) || \ 21708 ((__INSTANCE__) == UART5) || \ 21709 ((__INSTANCE__) == USART6) || \ 21710 ((__INSTANCE__) == UART7) || \ 21711 ((__INSTANCE__) == UART8)) 21714 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \ 21715 ((__INSTANCE__) == USART2) || \ 21716 ((__INSTANCE__) == USART3) || \ 21717 ((__INSTANCE__) == USART6)) 21720 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \ 21721 ((__INSTANCE__) == USART2) || \ 21722 ((__INSTANCE__) == USART3) || \ 21723 ((__INSTANCE__) == UART4) || \ 21724 ((__INSTANCE__) == UART5) || \ 21725 ((__INSTANCE__) == USART6) || \ 21726 ((__INSTANCE__) == UART7) || \ 21727 ((__INSTANCE__) == UART8)) 21730 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG) 21733 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG) 21745 #define HASH_RNG_IRQn RNG_IRQn 21748 #define HASH_RNG_IRQHandler RNG_IRQHandler __IO uint32_t RXCRCR
Definition: stm32f769xx.h:942
__IO uint32_t DINR18
Definition: stm32f769xx.h:1259
__IO uint32_t DMABMR
Definition: stm32f769xx.h:545
__IO uint32_t SR
Definition: stm32f769xx.h:979
__IO uint32_t DINR8
Definition: stm32f769xx.h:1249
__IO uint32_t SR
Definition: stm32f769xx.h:585
__IO uint32_t VMCCR
Definition: stm32f769xx.h:1363
__IO uint32_t CR1
Definition: stm32f769xx.h:975
__IO uint32_t ACR
Definition: stm32f769xx.h:582
__IO uint32_t SQR3
Definition: stm32f769xx.h:233
__IO uint32_t SR
Definition: stm32f769xx.h:421
__IO uint32_t BKP27R
Definition: stm32f769xx.h:859
__IO uint32_t I2SCFGR
Definition: stm32f769xx.h:944
__IO uint32_t MCR
Definition: stm32f769xx.h:1323
__IO uint32_t ALRMBR
Definition: stm32f769xx.h:820
__IO uint32_t SSCGR
Definition: stm32f769xx.h:798
__IO uint32_t CRDFR
Definition: stm32f769xx.h:1237
__IO uint32_t AMTCR
Definition: stm32f769xx.h:480
__IO uint32_t FLTICR
Definition: stm32f769xx.h:375
__IO uint32_t LPTR
Definition: stm32f769xx.h:966
__IO uint32_t DOUTR23
Definition: stm32f769xx.h:1296
LCD-TFT Display Controller.
Definition: stm32f769xx.h:707
__IO uint32_t WRPCR
Definition: stm32f769xx.h:1385
__IO uint32_t BKP25R
Definition: stm32f769xx.h:857
Controller Area Network FIFOMailBox.
Definition: stm32f769xx.h:267
__IO uint32_t DINR17
Definition: stm32f769xx.h:1258
System configuration controller.
Definition: stm32f769xx.h:660
__IO uint32_t DOUTR31
Definition: stm32f769xx.h:1304
__IO uint32_t RLR
Definition: stm32f769xx.h:697
__IO uint32_t DOEPINT
Definition: stm32f769xx.h:1151
Serial Peripheral Interface.
Definition: stm32f769xx.h:935
__IO uint32_t DOUTR28
Definition: stm32f769xx.h:1301
Definition: stm32f769xx.h:163
Definition: stm32f769xx.h:92
__IO uint32_t VCCR
Definition: stm32f769xx.h:1326
__IO uint32_t DHR8R2
Definition: stm32f769xx.h:358
__IO uint32_t ISR
Definition: stm32f769xx.h:1033
__IO uint32_t CPSR
Definition: stm32f769xx.h:724
__IO uint32_t DR
Definition: stm32f769xx.h:1060
__IO uint32_t OPTKEYR
Definition: stm32f769xx.h:584
Definition: stm32f769xx.h:145
__IO uint32_t DTXFSTS
Definition: stm32f769xx.h:1139
__IO uint32_t AHB1RSTR
Definition: stm32f769xx.h:774
Definition: stm32f769xx.h:121
uint32_t RESERVED2
Definition: stm32f769xx.h:784
__IO uint32_t VVBPCCR
Definition: stm32f769xx.h:1371
__IO uint32_t OTYPER
Definition: stm32f769xx.h:646
__IO uint32_t DEACHMSK
Definition: stm32f769xx.h:1120
__IO uint32_t DHR8RD
Definition: stm32f769xx.h:361
__IO uint32_t JSQR
Definition: stm32f769xx.h:234
__IO uint32_t CFR
Definition: stm32f769xx.h:1047
__IO uint32_t SMPR2
Definition: stm32f769xx.h:224
__IO uint32_t APB2ENR
Definition: stm32f769xx.h:786
__IO uint32_t DSTS
Definition: stm32f769xx.h:1107
__IO uint32_t SSCR
Definition: stm32f769xx.h:710
__IO uint32_t TAMPCR
Definition: stm32f769xx.h:828
Definition: stm32f769xx.h:74
__IO uint32_t SR
Definition: stm32f769xx.h:1048
Definition: stm32f769xx.h:148
Definition: stm32f769xx.h:154
__IO uint32_t BKP13R
Definition: stm32f769xx.h:845
Definition: stm32f769xx.h:149
Definition: stm32f769xx.h:89
__IO uint32_t PUPDR
Definition: stm32f769xx.h:648
__IO uint32_t DOUTR29
Definition: stm32f769xx.h:1302
__IO uint32_t SHIFTR
Definition: stm32f769xx.h:823
__IO uint32_t HPTXSTS
Definition: stm32f769xx.h:1168
__IO uint32_t HTR
Definition: stm32f769xx.h:229
__IO uint32_t DINR16
Definition: stm32f769xx.h:1257
__IO uint32_t BKP31R
Definition: stm32f769xx.h:863
__IO uint32_t DR
Definition: stm32f769xx.h:940
__IO uint32_t CR1
Definition: stm32f769xx.h:221
Definition: stm32f769xx.h:109
__IO uint32_t TSSSR
Definition: stm32f769xx.h:826
__IO uint32_t GAHBCFG
Definition: stm32f769xx.h:1074
__IO uint32_t DCFG
Definition: stm32f769xx.h:1105
__IO uint32_t PTPTTHR
Definition: stm32f769xx.h:540
__IO uint32_t DOUTR6
Definition: stm32f769xx.h:1279
__IO uint32_t MACDBGR
Definition: stm32f769xx.h:505
__IO uint32_t IER
Definition: stm32f769xx.h:423
Definition: stm32f769xx.h:178
__IO uint32_t VHBPCCR
Definition: stm32f769xx.h:1368
__IO uint32_t PR
Definition: stm32f769xx.h:573
__IO uint32_t SMCR
Definition: stm32f769xx.h:977
__IO uint32_t CFBLR
Definition: stm32f769xx.h:744
__IO uint32_t IER
Definition: stm32f769xx.h:326
__IO uint32_t HFNUM
Definition: stm32f769xx.h:1166
Definition: stm32f769xx.h:171
__IO uint32_t CR
Definition: stm32f769xx.h:954
Definition: stm32f769xx.h:169
Definition: stm32f769xx.h:97
__IO uint32_t IDCODE
Definition: stm32f769xx.h:408
__IO uint32_t IFCR
Definition: stm32f769xx.h:897
__IO uint32_t BKP17R
Definition: stm32f769xx.h:849
Definition: stm32f769xx.h:101
__IO uint32_t CSR1
Definition: stm32f769xx.h:758
__IO uint32_t RTSR
Definition: stm32f769xx.h:570
Definition: stm32f769xx.h:86
__IO uint32_t WHPCR
Definition: stm32f769xx.h:735
uint32_t RESERVED10
Definition: stm32f769xx.h:1384
__IO uint32_t LVCIDR
Definition: stm32f769xx.h:1316
__IO uint32_t DCCR
Definition: stm32f769xx.h:740
__IO uint32_t CR2
Definition: stm32f769xx.h:677
__IO uint32_t DOEPDMA
Definition: stm32f769xx.h:1154
__IO uint32_t CR
Definition: stm32f769xx.h:894
External Interrupt/Event Controller.
Definition: stm32f769xx.h:566
__IO uint32_t CFBAR
Definition: stm32f769xx.h:743
Definition: stm32f769xx.h:181
__IO uint32_t CR
Definition: stm32f769xx.h:1233
__IO uint32_t MACHTLR
Definition: stm32f769xx.h:496
__IO uint32_t ALRMAR
Definition: stm32f769xx.h:819
Definition: stm32f769xx.h:136
__IO uint32_t DOUTR25
Definition: stm32f769xx.h:1298
Definition: stm32f769xx.h:173
__IO uint32_t CLKCR
Definition: stm32f769xx.h:910
Definition: stm32f769xx.h:119
__IO uint32_t LCCCR
Definition: stm32f769xx.h:1359
__IO uint32_t MMCRFCECR
Definition: stm32f769xx.h:528
__IO uint32_t RISR
Definition: stm32f769xx.h:422
Definition: stm32f769xx.h:183
__IO uint32_t LISR
Definition: stm32f769xx.h:449
__IO uint32_t GPDR
Definition: stm32f769xx.h:1338
__IO uint32_t PTPSSIR
Definition: stm32f769xx.h:534
__IO uint32_t ESUR
Definition: stm32f769xx.h:427
__IO uint32_t CCR
Definition: stm32f769xx.h:1315
__IO uint32_t BKP7R
Definition: stm32f769xx.h:839
__IO uint32_t VHSACCR
Definition: stm32f769xx.h:1367
__IO uint32_t DINR9
Definition: stm32f769xx.h:1250
__IO uint32_t LCOLCR
Definition: stm32f769xx.h:1317
uint32_t Reserved9
Definition: stm32f769xx.h:1114
__IO uint32_t ICR
Definition: stm32f769xx.h:1034
__IO uint32_t CR1
Definition: stm32f769xx.h:878
uint32_t Reserved18
Definition: stm32f769xx.h:1140
__IO uint32_t LWR
Definition: stm32f769xx.h:479
__IO uint32_t PRER
Definition: stm32f769xx.h:816
__IO uint32_t CLRFR
Definition: stm32f769xx.h:884
__IO uint32_t BDCR
Definition: stm32f769xx.h:795
__IO uint32_t MMCTGFCR
Definition: stm32f769xx.h:526
__IO uint32_t FRCR
Definition: stm32f769xx.h:880
__IO uint32_t OR
Definition: stm32f769xx.h:995
__IO uint32_t FLTAWLTR
Definition: stm32f769xx.h:381
__IO uint32_t BKP4R
Definition: stm32f769xx.h:836
SPDIF-RX Interface.
Definition: stm32f769xx.h:892
HDMI-CEC.
Definition: stm32f769xx.h:319
__IO uint32_t CCR6
Definition: stm32f769xx.h:998
Definition: stm32f769xx.h:162
Definition: stm32f769xx.h:132
Definition: stm32f769xx.h:165
Definition: stm32f769xx.h:105
__IO uint32_t DCTL
Definition: stm32f769xx.h:1106
__IO uint32_t PCTLR
Definition: stm32f769xx.h:1345
Flexible Memory Controller Bank3.
Definition: stm32f769xx.h:615
uint32_t RESERVED4
Definition: stm32f769xx.h:309
__IO uint32_t FR2
Definition: stm32f769xx.h:282
__IO uint32_t CR2
Definition: stm32f769xx.h:976
__IO uint32_t FLTEXMAX
Definition: stm32f769xx.h:384
__IO uint32_t DOUTR11
Definition: stm32f769xx.h:1284
__IO uint32_t DIEPINT
Definition: stm32f769xx.h:1135
__IO uint32_t ARG
Definition: stm32f769xx.h:911
__IO uint32_t BKP0R
Definition: stm32f769xx.h:832
CRC calculation unit.
Definition: stm32f769xx.h:333
__IO uint32_t GRXSTSR
Definition: stm32f769xx.h:1079
__IO uint32_t CR
Definition: stm32f769xx.h:439
__IO uint32_t DINEP1MSK
Definition: stm32f769xx.h:1122
__IO uint32_t GRXSTSP
Definition: stm32f769xx.h:1080
__IO uint32_t BKP21R
Definition: stm32f769xx.h:853
__I uint32_t RESPCMD
Definition: stm32f769xx.h:913
__IO uint32_t GUSBCFG
Definition: stm32f769xx.h:1075
__IO uint32_t ISR
Definition: stm32f769xx.h:462
__IO uint32_t CR2
Definition: stm32f769xx.h:1027
__IO uint32_t VR
Definition: stm32f769xx.h:1313
__IO uint32_t VVACR
Definition: stm32f769xx.h:1334
__IO uint32_t CR
Definition: stm32f769xx.h:461
__IO uint32_t GPSR
Definition: stm32f769xx.h:1339
__IO uint32_t BKP9R
Definition: stm32f769xx.h:841
__IO uint32_t CMP
Definition: stm32f769xx.h:1014
__IO uint32_t DMAMFBOCR
Definition: stm32f769xx.h:553
Definition: stm32f769xx.h:102
__IO uint32_t DEACHINT
Definition: stm32f769xx.h:1119
__IO uint32_t SR
Definition: stm32f769xx.h:1205
__IO uint32_t TIMEOUTR
Definition: stm32f769xx.h:681
__IO uint32_t DINR6
Definition: stm32f769xx.h:1247
__IO uint32_t GOTGINT
Definition: stm32f769xx.h:1073
__IO uint32_t DMASR
Definition: stm32f769xx.h:550
__IO uint32_t GLPMCFG
Definition: stm32f769xx.h:1090
__IO uint32_t CSR
Definition: stm32f769xx.h:796
__IO uint32_t DOUTR27
Definition: stm32f769xx.h:1300
__IO uint32_t PSMAR
Definition: stm32f769xx.h:964
__IO uint32_t MMCTIR
Definition: stm32f769xx.h:519
uint32_t Reserved04
Definition: stm32f769xx.h:1150
Definition: stm32f769xx.h:177
__IO uint32_t DOUTR1
Definition: stm32f769xx.h:1274
__IO uint32_t WPR
Definition: stm32f769xx.h:821
__IO uint32_t VPCR
Definition: stm32f769xx.h:1325
__IO uint32_t GCCFG
Definition: stm32f769xx.h:1085
Definition: stm32f769xx.h:100
__IO uint32_t ICR
Definition: stm32f769xx.h:1010
__IO uint32_t DMACHRBAR
Definition: stm32f769xx.h:559
__IO uint32_t JOFR4
Definition: stm32f769xx.h:228
Definition: stm32f769xx.h:135
__IO uint32_t WIFCR
Definition: stm32f769xx.h:1381
Definition: stm32f769xx.h:172
__IO uint32_t FGPFCCR
Definition: stm32f769xx.h:468
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32f769xx.h:1131
Definition: stm32f769xx.h:128
__IO uint32_t CR
Definition: stm32f769xx.h:1013
__IO uint32_t DINR28
Definition: stm32f769xx.h:1269
__IO uint32_t BKP2R
Definition: stm32f769xx.h:834
__IO uint32_t SDCMR
Definition: stm32f769xx.h:633
uint32_t Reserved3c
Definition: stm32f769xx.h:1207
__IO uint32_t VLCCR
Definition: stm32f769xx.h:1369
__IO uint32_t DINR2
Definition: stm32f769xx.h:1243
__IO uint32_t BKP6R
Definition: stm32f769xx.h:838
uint32_t Reserved40
Definition: stm32f769xx.h:1121
__IO uint32_t BFCR
Definition: stm32f769xx.h:741
__IO uint32_t DTIMER
Definition: stm32f769xx.h:918
__IO uint32_t DINR23
Definition: stm32f769xx.h:1264
__IO uint32_t DOUTR19
Definition: stm32f769xx.h:1292
__IO uint32_t ISR
Definition: stm32f769xx.h:815
__IO uint32_t GHCR
Definition: stm32f769xx.h:1337
__IO uint32_t APB1FZ
Definition: stm32f769xx.h:410
__IO uint32_t WCR
Definition: stm32f769xx.h:1378
__IO uint32_t KEYR
Definition: stm32f769xx.h:583
Definition: stm32f769xx.h:113
Definition: stm32f769xx.h:139
__IO uint32_t AHB2ENR
Definition: stm32f769xx.h:782
Definition: stm32f769xx.h:88
Definition: stm32f769xx.h:144
__IO uint32_t CR
Definition: stm32f769xx.h:734
Flexible Memory Controller Bank1E.
Definition: stm32f769xx.h:606
uint8_t RESERVED0
Definition: stm32f769xx.h:337
__IO uint32_t CLTCR
Definition: stm32f769xx.h:1343
Definition: stm32f769xx.h:447
__IO uint32_t ISR
Definition: stm32f769xx.h:1009
__IO uint32_t MODER
Definition: stm32f769xx.h:645
__IO uint32_t CR
Definition: stm32f769xx.h:351
__IO uint32_t OSPEEDR
Definition: stm32f769xx.h:647
__IO uint32_t LIPCR
Definition: stm32f769xx.h:723
Definition: stm32f769xx.h:81
__IO uint32_t LCVCIDR
Definition: stm32f769xx.h:1358
__IO uint32_t CONFR2
Definition: stm32f769xx.h:1197
Window WATCHDOG.
Definition: stm32f769xx.h:1044
__IO uint8_t IDR
Definition: stm32f769xx.h:336
__IO uint32_t SLOTR
Definition: stm32f769xx.h:881
__IO uint32_t ISR
Definition: stm32f769xx.h:721
__IO uint32_t CR
Definition: stm32f769xx.h:1314
__IO uint32_t BPCR
Definition: stm32f769xx.h:711
Definition: stm32f769xx.h:179
__IO uint32_t SR
Definition: stm32f769xx.h:1059
__IO uint32_t VNPCR
Definition: stm32f769xx.h:1327
__IO uint32_t DOUTR13
Definition: stm32f769xx.h:1286
__IO uint32_t TXDR
Definition: stm32f769xx.h:686
__IO uint32_t IDR
Definition: stm32f769xx.h:649
Definition: stm32f769xx.h:131
Definition: stm32f769xx.h:96
__IO uint32_t DIEPEMPMSK
Definition: stm32f769xx.h:1118
Definition: stm32f769xx.h:120
__IO uint32_t ABR
Definition: stm32f769xx.h:961
__IO uint32_t FLTFCR
Definition: stm32f769xx.h:377
__IO uint32_t OAR1
Definition: stm32f769xx.h:678
__I uint32_t RESP3
Definition: stm32f769xx.h:916
__IO uint32_t DCR
Definition: stm32f769xx.h:955
__IO uint32_t SSR
Definition: stm32f769xx.h:822
__IO uint32_t ICR
Definition: stm32f769xx.h:683
__IO uint32_t DMACHTBAR
Definition: stm32f769xx.h:558
#define __I
Definition: core_cm0.h:210
__IO uint32_t M1AR
Definition: stm32f769xx.h:443
__IO uint32_t AHB1LPENR
Definition: stm32f769xx.h:788
__IO uint32_t MACPMTCSR
Definition: stm32f769xx.h:503
__IO uint32_t PMC
Definition: stm32f769xx.h:663
__IO uint32_t CWSIZER
Definition: stm32f769xx.h:429
__IO uint32_t DINR19
Definition: stm32f769xx.h:1260
uint32_t RESERVED1
Definition: stm32f769xx.h:504
__IO uint32_t APB1LPENR
Definition: stm32f769xx.h:792
__IO uint32_t SRCR
Definition: stm32f769xx.h:716
Definition: stm32f769xx.h:95
uint32_t RESERVED5
Definition: stm32f769xx.h:1360
__IO uint32_t ICR
Definition: stm32f769xx.h:425
__IO uint32_t CR
Definition: stm32f769xx.h:770
__IO uint32_t MACVLANTR
Definition: stm32f769xx.h:500
__IO uint32_t WRFR
Definition: stm32f769xx.h:1234
__IO uint32_t PUCR
Definition: stm32f769xx.h:1347
__IO uint32_t DOUTR16
Definition: stm32f769xx.h:1289
__IO uint32_t HFIR
Definition: stm32f769xx.h:1165
__IO uint32_t DOUTR15
Definition: stm32f769xx.h:1288
__IO uint32_t JOFR1
Definition: stm32f769xx.h:225
__IO uint32_t DINR21
Definition: stm32f769xx.h:1262
Definition: stm32f769xx.h:115
__IO uint32_t PSC
Definition: stm32f769xx.h:985
__IO uint32_t ODR
Definition: stm32f769xx.h:650
__IO uint32_t HCINTMSK
Definition: stm32f769xx.h:1181
uint32_t RESERVED9
Definition: stm32f769xx.h:1382
uint32_t Reserved40C
Definition: stm32f769xx.h:1167
uint32_t reserved
Definition: stm32f769xx.h:818
LCD-TFT Display layer x Controller.
Definition: stm32f769xx.h:732
__IO uint32_t CR1
Definition: stm32f769xx.h:937
__IO uint32_t DIER
Definition: stm32f769xx.h:978
__IO uint32_t BKP5R
Definition: stm32f769xx.h:837
__IO uint32_t CBR
Definition: stm32f769xx.h:666
__IO uint32_t DLTCR
Definition: stm32f769xx.h:1344
__IO uint32_t LIFCR
Definition: stm32f769xx.h:451
__IO uint32_t TDCR
Definition: stm32f769xx.h:1341
__IO uint32_t OCOLR
Definition: stm32f769xx.h:475
Definition: stm32f769xx.h:184
__IO uint32_t SWTRIGR
Definition: stm32f769xx.h:352
__IO uint32_t FFA1R
Definition: stm32f769xx.h:308
__IO uint32_t CSR2
Definition: stm32f769xx.h:760
__IO uint32_t DHR12LD
Definition: stm32f769xx.h:360
__IO uint32_t DINR10
Definition: stm32f769xx.h:1251
__IO uint32_t DLEN
Definition: stm32f769xx.h:919
__IO uint32_t CR2
Definition: stm32f769xx.h:879
__IO uint32_t GINTMSK
Definition: stm32f769xx.h:1078
__IO uint32_t CMD
Definition: stm32f769xx.h:912
__IO uint32_t SR
Definition: stm32f769xx.h:1238
__IO uint32_t CFR
Definition: stm32f769xx.h:1206
__IO uint32_t CIR
Definition: stm32f769xx.h:773
__IO uint32_t FR1
Definition: stm32f769xx.h:281
USB_OTG_Core_Registers.
Definition: stm32f769xx.h:1070
__IO uint32_t DIR
Definition: stm32f769xx.h:900
Definition: stm32f769xx.h:91
__IO uint32_t GADPCTL
Definition: stm32f769xx.h:1093
__IO uint32_t DHR12RD
Definition: stm32f769xx.h:359
__IO uint32_t MISR
Definition: stm32f769xx.h:424
__IO uint32_t SR
Definition: stm32f769xx.h:618
__IO uint32_t DINR4
Definition: stm32f769xx.h:1245
__IO uint32_t MACA3HR
Definition: stm32f769xx.h:514
__IO uint32_t PSR
Definition: stm32f769xx.h:1349
__IO uint32_t CKCR
Definition: stm32f769xx.h:737
__IO uint32_t OMAR
Definition: stm32f769xx.h:476
__IO uint32_t NDTR
Definition: stm32f769xx.h:440
__IO uint32_t DR
Definition: stm32f769xx.h:813
__IO uint32_t CWRFR
Definition: stm32f769xx.h:1235
__IO uint32_t DINR0
Definition: stm32f769xx.h:1241
__IO uint32_t DCKCFGR2
Definition: stm32f769xx.h:802
__IO uint32_t CSR
Definition: stm32f769xx.h:244
__IO uint32_t CHWDATAR
Definition: stm32f769xx.h:398
__IO uint32_t CCR4
Definition: stm32f769xx.h:991
__IO uint32_t GRSTCTL
Definition: stm32f769xx.h:1076
__IO uint32_t ICR
Definition: stm32f769xx.h:923
__IO uint32_t MMCTGFSCCR
Definition: stm32f769xx.h:523
__IO uint32_t BKP11R
Definition: stm32f769xx.h:843
Definition: stm32f769xx.h:76
Definition: stm32f769xx.h:160
__IO uint32_t DINR24
Definition: stm32f769xx.h:1265
__IO uint32_t DINR5
Definition: stm32f769xx.h:1246
__IO uint32_t CCR5
Definition: stm32f769xx.h:997
General Purpose I/O.
Definition: stm32f769xx.h:643
Definition: stm32f769xx.h:72
Definition: stm32f769xx.h:112
__IO uint32_t DOUTR24
Definition: stm32f769xx.h:1297
__IO uint32_t BKP29R
Definition: stm32f769xx.h:861
__I uint32_t RESP4
Definition: stm32f769xx.h:917
__IO uint32_t DINR30
Definition: stm32f769xx.h:1271
__IO uint32_t TXDR
Definition: stm32f769xx.h:323
Definition: stm32f769xx.h:187
Definition: stm32f769xx.h:124
__IO uint32_t JDR3
Definition: stm32f769xx.h:237
__IO uint32_t BKP12R
Definition: stm32f769xx.h:844
QUAD Serial Peripheral Interface.
Definition: stm32f769xx.h:952
__IO uint32_t DOUTR9
Definition: stm32f769xx.h:1282
uint32_t RESERVED2
Definition: stm32f769xx.h:305
__IO uint32_t CALR
Definition: stm32f769xx.h:827
__IO uint32_t APB2FZ
Definition: stm32f769xx.h:411
__IO uint32_t MASK
Definition: stm32f769xx.h:924
__IO uint32_t DIEPDMA
Definition: stm32f769xx.h:1138
__IO uint32_t HNPTXSTS
Definition: stm32f769xx.h:1083
__IO uint32_t DOUTR14
Definition: stm32f769xx.h:1287
__IO uint32_t FLTCR2
Definition: stm32f769xx.h:373
__IO uint32_t AHB2LPENR
Definition: stm32f769xx.h:789
__IO uint32_t PTPTSLUR
Definition: stm32f769xx.h:538
Definition: stm32f769xx.h:142
__IO uint32_t DINR27
Definition: stm32f769xx.h:1268
__IO uint32_t TDCCR
Definition: stm32f769xx.h:1375
__IO uint32_t CR2
Definition: stm32f769xx.h:938
Definition: stm32f769xx.h:110
Controller Area Network.
Definition: stm32f769xx.h:289
LPTIMIMER.
Definition: stm32f769xx.h:1007
__IO uint32_t BTR
Definition: stm32f769xx.h:298
__IO uint32_t CR
Definition: stm32f769xx.h:321
Definition: stm32f769xx.h:127
__IO uint32_t CMPCR
Definition: stm32f769xx.h:667
__IO uint32_t FLTAWHTR
Definition: stm32f769xx.h:380
__IO uint32_t IER
Definition: stm32f769xx.h:720
__IO uint32_t CRCPR
Definition: stm32f769xx.h:941
__IO uint32_t CMCR
Definition: stm32f769xx.h:1336
__IO uint32_t RTOR
Definition: stm32f769xx.h:1031
__IO uint32_t PAR
Definition: stm32f769xx.h:441
__IO uint32_t MACIMR
Definition: stm32f769xx.h:507
Definition: stm32f769xx.h:157
Definition: stm32f769xx.h:134
__IO uint32_t CONFR3
Definition: stm32f769xx.h:1198
__IO uint32_t FMR
Definition: stm32f769xx.h:303
__IO uint32_t VVFPCCR
Definition: stm32f769xx.h:1372
__IO uint32_t DOUTR4
Definition: stm32f769xx.h:1277
DMA2D Controller.
Definition: stm32f769xx.h:459
Definition: stm32f769xx.h:84
__IO uint32_t MACMIIAR
Definition: stm32f769xx.h:497
__IO uint32_t OPTCR
Definition: stm32f769xx.h:587
__IO uint32_t TSDR
Definition: stm32f769xx.h:825
__IO uint32_t PATT
Definition: stm32f769xx.h:620
__IO uint32_t DHR12R1
Definition: stm32f769xx.h:353
Definition: stm32f769xx.h:151
__IO uint32_t DMACHRDR
Definition: stm32f769xx.h:557
uint32_t Reserved4FC
Definition: stm32f769xx.h:1219
#define __IO
Definition: core_cm0.h:213
__IO uint32_t TXCRCR
Definition: stm32f769xx.h:943
__IO uint32_t VSCR
Definition: stm32f769xx.h:1356
__IO uint32_t BKP24R
Definition: stm32f769xx.h:856
Analog to Digital Converter.
Definition: stm32f769xx.h:218
__IO uint32_t ALRMBSSR
Definition: stm32f769xx.h:830
__I uint32_t RESP2
Definition: stm32f769xx.h:915
__IO uint32_t GCR
Definition: stm32f769xx.h:714
__IO uint32_t GPWRDN
Definition: stm32f769xx.h:1091
__IO uint32_t DAINT
Definition: stm32f769xx.h:1111
__IO uint32_t DMAIER
Definition: stm32f769xx.h:552
__IO uint32_t BKP23R
Definition: stm32f769xx.h:855
__IO uint32_t AF1
Definition: stm32f769xx.h:999
__IO uint32_t RCR
Definition: stm32f769xx.h:987
__IO uint32_t DOUTR17
Definition: stm32f769xx.h:1290
__IO uint32_t ICR
Definition: stm32f769xx.h:722
Definition: stm32f769xx.h:77
__IO uint32_t CONFR0
Definition: stm32f769xx.h:1195
__IO uint32_t IMR
Definition: stm32f769xx.h:895
__IO uint32_t DINR25
Definition: stm32f769xx.h:1266
__IO uint32_t DR
Definition: stm32f769xx.h:430
__IO uint32_t FLTISR
Definition: stm32f769xx.h:374
__IO uint32_t MACSR
Definition: stm32f769xx.h:506
__IO uint32_t DLR
Definition: stm32f769xx.h:958
__IO uint32_t CR
Definition: stm32f769xx.h:1058
__IO uint32_t VVACCR
Definition: stm32f769xx.h:1373
Serial Audio Interface.
Definition: stm32f769xx.h:871
__IO uint32_t LCKR
Definition: stm32f769xx.h:652
__IO uint32_t RXDR
Definition: stm32f769xx.h:685
__IO uint32_t CHDATINR
Definition: stm32f769xx.h:399
Definition: stm32f769xx.h:90
__IO uint32_t RDLR
Definition: stm32f769xx.h:271
__IO uint32_t FS1R
Definition: stm32f769xx.h:306
uint32_t Reserved20
Definition: stm32f769xx.h:1113
__IO uint32_t DINR15
Definition: stm32f769xx.h:1256
__IO uint32_t FA1R
Definition: stm32f769xx.h:310
__IO uint32_t CCMR1
Definition: stm32f769xx.h:981
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32f769xx.h:1162
__IO uint32_t PTPTSHR
Definition: stm32f769xx.h:535
__IO uint32_t GCR
Definition: stm32f769xx.h:873
__IO uint32_t MCR
Definition: stm32f769xx.h:291
__IO uint32_t AF2
Definition: stm32f769xx.h:1000
__IO uint32_t DCR
Definition: stm32f769xx.h:993
__IO uint32_t APB1ENR
Definition: stm32f769xx.h:785
__IO uint32_t VMCR
Definition: stm32f769xx.h:1324
__IO uint32_t MACFCR
Definition: stm32f769xx.h:499
__IO uint32_t VHBPCR
Definition: stm32f769xx.h:1329
IRQn_Type
STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f769xx.h:67
__IO uint32_t BGCOLR
Definition: stm32f769xx.h:471
__IO uint32_t DR
Definition: stm32f769xx.h:962
Definition: stm32f769xx.h:170
__IO uint32_t PIR
Definition: stm32f769xx.h:965
__IO uint32_t BKP14R
Definition: stm32f769xx.h:846
__IO uint32_t BKP30R
Definition: stm32f769xx.h:862
Controller Area Network TxMailBox.
Definition: stm32f769xx.h:255
Ethernet MAC.
Definition: stm32f769xx.h:491
__IO uint32_t VPCCR
Definition: stm32f769xx.h:1364
__IO uint32_t RDFR
Definition: stm32f769xx.h:1236
Definition: stm32f769xx.h:107
__IO uint32_t CR
Definition: stm32f769xx.h:1046
__IO uint32_t DINR22
Definition: stm32f769xx.h:1263
__IO uint32_t FLTJCHGR
Definition: stm32f769xx.h:376
Definition: stm32f769xx.h:130
__IO uint32_t VVSACCR
Definition: stm32f769xx.h:1370
__IO uint32_t BKP20R
Definition: stm32f769xx.h:852
__IO uint32_t OR
Definition: stm32f769xx.h:831
__IO uint32_t TSR
Definition: stm32f769xx.h:293
__IO uint32_t CWSTRTR
Definition: stm32f769xx.h:428
__IO uint32_t DOUTR2
Definition: stm32f769xx.h:1275
__IO uint32_t CONFR5
Definition: stm32f769xx.h:1200
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f769xx.h:1024
__IO uint32_t CCR
Definition: stm32f769xx.h:959
__IO uint32_t OPFCCR
Definition: stm32f769xx.h:474
__IO uint32_t DCKCFGR1
Definition: stm32f769xx.h:801
__IO uint32_t OPTCR1
Definition: stm32f769xx.h:588
TIM.
Definition: stm32f769xx.h:973
__IO uint32_t MMCTGFMSCCR
Definition: stm32f769xx.h:524
__IO uint32_t PTPTSSR
Definition: stm32f769xx.h:543
__IO uint32_t HPTXFSIZ
Definition: stm32f769xx.h:1095
__IO uint32_t DINR13
Definition: stm32f769xx.h:1254
uint32_t Reserved0C
Definition: stm32f769xx.h:1108
__IO uint32_t DHR8R1
Definition: stm32f769xx.h:355
Definition: stm32f769xx.h:126
Definition: stm32f769xx.h:147
__IO uint32_t OOR
Definition: stm32f769xx.h:477
DFSDM module registers.
Definition: stm32f769xx.h:370
Definition: stm32f769xx.h:116
__IO uint32_t MACA1LR
Definition: stm32f769xx.h:511
__IO uint32_t HCINT
Definition: stm32f769xx.h:1180
__IO uint32_t SR
Definition: stm32f769xx.h:956
__IO uint32_t MACA1HR
Definition: stm32f769xx.h:510
__IO uint32_t DOUTR20
Definition: stm32f769xx.h:1293
__IO uint32_t FTSR
Definition: stm32f769xx.h:571
__IO uint32_t FLTJDATAR
Definition: stm32f769xx.h:378
DMA Controller.
Definition: stm32f769xx.h:437
Digital to Analog Converter.
Definition: stm32f769xx.h:349
__IO uint32_t DOUTR22
Definition: stm32f769xx.h:1295
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32f769xx.h:1176
Definition: stm32f769xx.h:155
__IO uint32_t FLTRDATAR
Definition: stm32f769xx.h:379
__IO uint32_t DINR3
Definition: stm32f769xx.h:1244
Definition: stm32f769xx.h:174
FLASH Registers.
Definition: stm32f769xx.h:580
__I uint32_t RESP1
Definition: stm32f769xx.h:914
__IO uint32_t FGOR
Definition: stm32f769xx.h:465
__IO uint32_t PLLCFGR
Definition: stm32f769xx.h:771
__IO uint32_t AHB1ENR
Definition: stm32f769xx.h:781
__IO uint32_t TIR
Definition: stm32f769xx.h:257
__IO uint32_t CR
Definition: stm32f769xx.h:1204
__IO uint32_t JDR1
Definition: stm32f769xx.h:235
__I uint32_t DCOUNT
Definition: stm32f769xx.h:921
Definition: stm32f769xx.h:137
Power Control.
Definition: stm32f769xx.h:755
__IO uint32_t DOUTR21
Definition: stm32f769xx.h:1294
__IO uint32_t TIMINGR
Definition: stm32f769xx.h:680
__IO uint32_t NLR
Definition: stm32f769xx.h:478
Definition: stm32f769xx.h:80
__IO uint32_t PCR
Definition: stm32f769xx.h:617
__IO uint32_t DOUTR18
Definition: stm32f769xx.h:1291
__IO uint32_t MACA2LR
Definition: stm32f769xx.h:513
Definition: stm32f769xx.h:140
Independent WATCHDOG.
Definition: stm32f769xx.h:693
Definition: stm32f769xx.h:176
__IO uint32_t DOR2
Definition: stm32f769xx.h:363
Definition: stm32f769xx.h:159
DFSDM channel configuration registers.
Definition: stm32f769xx.h:392
__IO uint32_t DIEPTXF0_HNPTXFSIZ
Definition: stm32f769xx.h:1082
__IO uint32_t DR
Definition: stm32f769xx.h:335
__IO uint32_t SWIER
Definition: stm32f769xx.h:572
__IO uint32_t TDHR
Definition: stm32f769xx.h:260
Definition: stm32f769xx.h:153
__IO uint32_t CCR1
Definition: stm32f769xx.h:988
__IO uint32_t SR
Definition: stm32f769xx.h:939
__IO uint32_t PTPTSHUR
Definition: stm32f769xx.h:537
__IO uint32_t POL
Definition: stm32f769xx.h:342
__IO uint32_t GOTGCTL
Definition: stm32f769xx.h:1072
__IO uint32_t FCR
Definition: stm32f769xx.h:957
__IO uint32_t DHR12R2
Definition: stm32f769xx.h:356
__IO uint32_t BGPFCCR
Definition: stm32f769xx.h:470
__IO uint32_t GTPR
Definition: stm32f769xx.h:1030
__IO uint32_t CONFR6
Definition: stm32f769xx.h:1201
JPEG Codec.
Definition: stm32f769xx.h:1193
__IO uint32_t ESCR
Definition: stm32f769xx.h:426
__IO uint32_t CR
Definition: stm32f769xx.h:814
Definition: stm32f769xx.h:242
uint32_t Reserved6
Definition: stm32f769xx.h:1089
__IO uint32_t DR
Definition: stm32f769xx.h:239
Definition: stm32f769xx.h:93
Definition: stm32f769xx.h:82
__IO uint32_t BKP16R
Definition: stm32f769xx.h:848
__IO uint32_t BKP28R
Definition: stm32f769xx.h:860
__IO uint32_t CHCFGR2
Definition: stm32f769xx.h:395
__IO uint32_t MACHTHR
Definition: stm32f769xx.h:495
__IO uint32_t DOUTR5
Definition: stm32f769xx.h:1278
__IO uint32_t DINR26
Definition: stm32f769xx.h:1267
__IO uint32_t HCSPLT
Definition: stm32f769xx.h:1179
__IO uint32_t CR2
Definition: stm32f769xx.h:222
__IO uint32_t HISR
Definition: stm32f769xx.h:450
Reset and Clock Control.
Definition: stm32f769xx.h:768
__IO uint32_t DHR12L1
Definition: stm32f769xx.h:354
__IO uint32_t WVPCR
Definition: stm32f769xx.h:736
__IO uint32_t DOUTR0
Definition: stm32f769xx.h:1273
__IO uint32_t LPCR
Definition: stm32f769xx.h:1318
__IO uint32_t CR2
Definition: stm32f769xx.h:759
__IO uint32_t WUTR
Definition: stm32f769xx.h:817
__IO uint32_t FM1R
Definition: stm32f769xx.h:304
__IO uint32_t CHAWSCDR
Definition: stm32f769xx.h:396
Definition: stm32f769xx.h:79
__IO uint32_t BSRR
Definition: stm32f769xx.h:651
__IO uint32_t DOEPCTL
Definition: stm32f769xx.h:1149
__IO uint32_t AHB3LPENR
Definition: stm32f769xx.h:790
__IO uint32_t LCCR
Definition: stm32f769xx.h:1335
Definition: stm32f769xx.h:143
__IO uint32_t CACR
Definition: stm32f769xx.h:739
Definition: stm32f769xx.h:122
__IO uint32_t CSR
Definition: stm32f769xx.h:899
__IO uint32_t APB1RSTR
Definition: stm32f769xx.h:778
__IO uint32_t MACFFR
Definition: stm32f769xx.h:494
Definition: stm32f769xx.h:168
__IO uint32_t DOEPTSIZ
Definition: stm32f769xx.h:1153
Definition: stm32f769xx.h:152
__IO uint32_t CR
Definition: stm32f769xx.h:339
__IO uint32_t CR
Definition: stm32f769xx.h:420
Controller Area Network FilterRegister.
Definition: stm32f769xx.h:279
__IO uint32_t MACA2HR
Definition: stm32f769xx.h:512
__IO uint32_t CONFR1
Definition: stm32f769xx.h:1196
Definition: stm32f769xx.h:98
__IO uint32_t DINR1
Definition: stm32f769xx.h:1242
Definition: stm32f769xx.h:75
__IO uint32_t WIER
Definition: stm32f769xx.h:1379
__IO uint32_t MACMIIDR
Definition: stm32f769xx.h:498
__IO uint32_t OAR2
Definition: stm32f769xx.h:679
__IO uint32_t DIEPMSK
Definition: stm32f769xx.h:1109
Flexible Memory Controller.
Definition: stm32f769xx.h:597
__IO uint32_t KR
Definition: stm32f769xx.h:695
__IO uint32_t FLTEXMIN
Definition: stm32f769xx.h:385
__IO uint32_t MACRWUFFR
Definition: stm32f769xx.h:502
__IO uint32_t DOUTR12
Definition: stm32f769xx.h:1285
__IO uint32_t PTPTTLR
Definition: stm32f769xx.h:541
__IO uint32_t EGR
Definition: stm32f769xx.h:980
Definition: stm32f769xx.h:94
Definition: stm32f769xx.h:133
__IO uint32_t DINR29
Definition: stm32f769xx.h:1270
__IO uint32_t FLTAWCFR
Definition: stm32f769xx.h:383
Definition: stm32f769xx.h:175
__I uint32_t FIFOCNT
Definition: stm32f769xx.h:926
__IO uint32_t GDFIFOCFG
Definition: stm32f769xx.h:1092
Real-Time Clock.
Definition: stm32f769xx.h:810
__IO uint32_t BRR
Definition: stm32f769xx.h:1029
Definition: stm32f769xx.h:141
__IO uint32_t MMCRIMR
Definition: stm32f769xx.h:520
DCMI.
Definition: stm32f769xx.h:418
__IO uint32_t RDHR
Definition: stm32f769xx.h:272
Definition: stm32f769xx.h:111
__IO uint32_t MMCRGUFCR
Definition: stm32f769xx.h:531
__IO uint32_t AHB3RSTR
Definition: stm32f769xx.h:776
__IO uint32_t CR1
Definition: stm32f769xx.h:676
__IO uint32_t JDR2
Definition: stm32f769xx.h:236
__IO uint32_t CID
Definition: stm32f769xx.h:1086
__IO uint32_t LPMCCR
Definition: stm32f769xx.h:1361
Flexible Memory Controller Bank5_6.
Definition: stm32f769xx.h:629
uint32_t Reserved0C
Definition: stm32f769xx.h:1136
uint16_t RESERVED1
Definition: stm32f769xx.h:338
__IO uint32_t DTHRCTL
Definition: stm32f769xx.h:1117
__IO uint32_t CFGR
Definition: stm32f769xx.h:322
Definition: stm32f769xx.h:156
__IO uint32_t APB2RSTR
Definition: stm32f769xx.h:779
Definition: stm32f769xx.h:106
__IO uint32_t TR
Definition: stm32f769xx.h:812
__IO uint32_t DMARDLAR
Definition: stm32f769xx.h:548
uint32_t RESERVED2
Definition: stm32f769xx.h:340
__IO uint32_t TDR
Definition: stm32f769xx.h:1036
__IO uint32_t DMAR
Definition: stm32f769xx.h:994
__IO uint32_t CLRFR
Definition: stm32f769xx.h:1239
__IO uint32_t CNT
Definition: stm32f769xx.h:984
Definition: stm32f769xx.h:158
__IO uint32_t CONFR7
Definition: stm32f769xx.h:1202
__IO uint32_t BDTR
Definition: stm32f769xx.h:992
__IO uint32_t MACCR
Definition: stm32f769xx.h:493
__IO uint32_t INIT
Definition: stm32f769xx.h:341
__IO uint32_t DAINTMSK
Definition: stm32f769xx.h:1112
__IO uint32_t DOUTR3
Definition: stm32f769xx.h:1276
__IO uint32_t ISR
Definition: stm32f769xx.h:325
__IO uint32_t DINR12
Definition: stm32f769xx.h:1253
__IO uint32_t HAINTMSK
Definition: stm32f769xx.h:1170
__IO uint32_t JDR4
Definition: stm32f769xx.h:238
__IO uint32_t MACA3LR
Definition: stm32f769xx.h:515
__I uint32_t STA
Definition: stm32f769xx.h:922
Definition: stm32f769xx.h:83
__IO uint32_t FGMAR
Definition: stm32f769xx.h:464
__IO uint32_t FGCOLR
Definition: stm32f769xx.h:469
Definition: stm32f769xx.h:138
__IO uint32_t ESR
Definition: stm32f769xx.h:297
uint32_t RESERVED0
Definition: stm32f769xx.h:777
__IO uint32_t RXDR
Definition: stm32f769xx.h:324
__IO uint32_t DIEPCTL
Definition: stm32f769xx.h:1133
__IO uint32_t CNT
Definition: stm32f769xx.h:1016
Definition: stm32f769xx.h:186
__IO uint32_t FGCMAR
Definition: stm32f769xx.h:472
__IO uint32_t CHCFGR1
Definition: stm32f769xx.h:394
Inter-integrated Circuit Interface.
Definition: stm32f769xx.h:674
Definition: stm32f769xx.h:123
__IO uint32_t MMCCR
Definition: stm32f769xx.h:517
__IO uint32_t PECR
Definition: stm32f769xx.h:684
__IO uint32_t PLLSAICFGR
Definition: stm32f769xx.h:800
__IO uint32_t SR
Definition: stm32f769xx.h:896
uint32_t RESERVED4
Definition: stm32f769xx.h:791
__IO uint32_t DCTRL
Definition: stm32f769xx.h:920
__IO uint32_t DINR7
Definition: stm32f769xx.h:1248
__IO uint32_t MACA0LR
Definition: stm32f769xx.h:509
__IO uint32_t IER
Definition: stm32f769xx.h:296
uint32_t Reserved0C
Definition: stm32f769xx.h:1152
__IO uint32_t JOFR2
Definition: stm32f769xx.h:226
__IO uint32_t DMATPDR
Definition: stm32f769xx.h:546
__IO uint32_t BCCR
Definition: stm32f769xx.h:718
__IO uint32_t BKP1R
Definition: stm32f769xx.h:833
__IO uint32_t DOUTR8
Definition: stm32f769xx.h:1281
__IO uint32_t DMARPDR
Definition: stm32f769xx.h:547
__IO uint32_t SQR2
Definition: stm32f769xx.h:232
__IO uint32_t PSMKR
Definition: stm32f769xx.h:963
__IO uint32_t GINTSTS
Definition: stm32f769xx.h:1077
__IO uint32_t RDR
Definition: stm32f769xx.h:1035
uint32_t RESERVED
Definition: stm32f769xx.h:665
__IO uint32_t JOFR3
Definition: stm32f769xx.h:227
uint32_t RESERVED0
Definition: stm32f769xx.h:621
__IO uint32_t FLTAWSR
Definition: stm32f769xx.h:382
__IO uint32_t CR3
Definition: stm32f769xx.h:1028
__IO uint32_t HIFCR
Definition: stm32f769xx.h:452
__IO uint32_t ISR
Definition: stm32f769xx.h:682
__IO uint32_t PFCR
Definition: stm32f769xx.h:738
__IO uint32_t DOUTR30
Definition: stm32f769xx.h:1303
uint32_t RESERVED3
Definition: stm32f769xx.h:307
__IO uint32_t DOUTR10
Definition: stm32f769xx.h:1283
RNG.
Definition: stm32f769xx.h:1056
__IO uint32_t GHWCFG3
Definition: stm32f769xx.h:1088
__IO uint32_t AWCR
Definition: stm32f769xx.h:712
__IO uint32_t CDR
Definition: stm32f769xx.h:246
__IO uint32_t HCTSIZ
Definition: stm32f769xx.h:1182
__IO uint32_t PTPTSLR
Definition: stm32f769xx.h:536
__IO uint32_t VLCR
Definition: stm32f769xx.h:1330
__IO uint32_t DMARSWTR
Definition: stm32f769xx.h:554
__IO uint32_t SDRTR
Definition: stm32f769xx.h:634
__IO uint32_t RIR
Definition: stm32f769xx.h:269
Definition: stm32f769xx.h:164
__IO uint32_t TSTR
Definition: stm32f769xx.h:824
Definition: stm32f769xx.h:103
Definition: stm32f769xx.h:104
__IO uint32_t CLUTWR
Definition: stm32f769xx.h:747
__IO uint32_t CR
Definition: stm32f769xx.h:586
__IO uint32_t FIFO
Definition: stm32f769xx.h:928
__IO uint32_t CCER
Definition: stm32f769xx.h:983
__IO uint32_t CR1
Definition: stm32f769xx.h:1026
__IO uint32_t PR
Definition: stm32f769xx.h:696
__IO uint32_t DVBUSPULSE
Definition: stm32f769xx.h:1116
__IO uint32_t BGMAR
Definition: stm32f769xx.h:466
__IO uint32_t DINR11
Definition: stm32f769xx.h:1252
__IO uint32_t PTTCR
Definition: stm32f769xx.h:1348
Debug MCU.
Definition: stm32f769xx.h:406
__IO uint32_t FLTCR1
Definition: stm32f769xx.h:372
__IO uint32_t AHB3ENR
Definition: stm32f769xx.h:783
__IO uint32_t TDLR
Definition: stm32f769xx.h:259
__IO uint32_t PTPTSCR
Definition: stm32f769xx.h:533
__IO uint32_t RF1R
Definition: stm32f769xx.h:295
Definition: stm32f769xx.h:114
__IO uint32_t PLLI2SCFGR
Definition: stm32f769xx.h:799
Definition: stm32f769xx.h:108
__IO uint32_t VNPCCR
Definition: stm32f769xx.h:1366
__IO uint32_t HCDMA
Definition: stm32f769xx.h:1183
__IO uint32_t CCMR3
Definition: stm32f769xx.h:996
uint32_t Reserved04
Definition: stm32f769xx.h:1134
__IO uint32_t BKP22R
Definition: stm32f769xx.h:854
__IO uint32_t CONFR4
Definition: stm32f769xx.h:1199
__IO uint32_t POWER
Definition: stm32f769xx.h:909
__IO uint32_t DINR20
Definition: stm32f769xx.h:1261
__IO uint32_t BGCMAR
Definition: stm32f769xx.h:473
__IO uint32_t WISR
Definition: stm32f769xx.h:1380
__IO uint32_t VVBPCR
Definition: stm32f769xx.h:1332
__IO uint32_t DIR
Definition: stm32f769xx.h:1208
Definition: stm32f769xx.h:70
__IO uint32_t BKP19R
Definition: stm32f769xx.h:851
__IO uint32_t AHB2RSTR
Definition: stm32f769xx.h:775
SD host Interface.
Definition: stm32f769xx.h:907
__IO uint32_t LPMCR
Definition: stm32f769xx.h:1319
__IO uint32_t RDTR
Definition: stm32f769xx.h:270
Definition: stm32f769xx.h:125
__IO uint32_t DMATDLAR
Definition: stm32f769xx.h:549
__IO uint32_t GVCIDR
Definition: stm32f769xx.h:1322
Definition: stm32f769xx.h:876
__IO uint32_t ALRMASSR
Definition: stm32f769xx.h:829
__IO uint32_t ARR
Definition: stm32f769xx.h:1015
__IO uint32_t BKP18R
Definition: stm32f769xx.h:850
Definition: stm32f769xx.h:85
__IO uint32_t LTR
Definition: stm32f769xx.h:230
__IO uint32_t ECCR
Definition: stm32f769xx.h:622
__IO uint32_t BKP10R
Definition: stm32f769xx.h:842
__IO uint32_t IFCR
Definition: stm32f769xx.h:463
Definition: stm32f769xx.h:166
__IO uint32_t IMR
Definition: stm32f769xx.h:568
__IO uint32_t MACA0HR
Definition: stm32f769xx.h:508
__IO uint32_t SR
Definition: stm32f769xx.h:698
__IO uint32_t DOR1
Definition: stm32f769xx.h:362
__IO uint32_t MMCRFAECR
Definition: stm32f769xx.h:529
__IO uint32_t HCFG
Definition: stm32f769xx.h:1164
__IO uint32_t DOUTR26
Definition: stm32f769xx.h:1299
__IO uint32_t MSR
Definition: stm32f769xx.h:292
__IO uint32_t TDTR
Definition: stm32f769xx.h:258
__IO uint32_t RF0R
Definition: stm32f769xx.h:294
__IO uint32_t SR
Definition: stm32f769xx.h:220
__IO uint32_t PCR
Definition: stm32f769xx.h:1321
__IO uint32_t DMAOMR
Definition: stm32f769xx.h:551
Definition: stm32f769xx.h:87
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32f769xx.h:1147
Definition: stm32f769xx.h:167
__IO uint32_t SDSR
Definition: stm32f769xx.h:635
Definition: stm32f769xx.h:118
Definition: stm32f769xx.h:180
__IO uint32_t IMR
Definition: stm32f769xx.h:882
__IO uint32_t WINR
Definition: stm32f769xx.h:699
__IO uint32_t VCCCR
Definition: stm32f769xx.h:1365
__IO uint32_t SR
Definition: stm32f769xx.h:364
__IO uint32_t I2SPR
Definition: stm32f769xx.h:945
__IO uint32_t CR
Definition: stm32f769xx.h:409
__IO uint32_t DIEPTSIZ
Definition: stm32f769xx.h:1137
__IO uint32_t RQR
Definition: stm32f769xx.h:1032
__IO uint32_t DVBUSDIS
Definition: stm32f769xx.h:1115
MDIOS.
Definition: stm32f769xx.h:1231
Definition: stm32f769xx.h:117
__IO uint32_t CCR2
Definition: stm32f769xx.h:989
__IO uint32_t CFBLNR
Definition: stm32f769xx.h:745
__IO uint32_t DR
Definition: stm32f769xx.h:885
__IO uint32_t FLTCNVTIMR
Definition: stm32f769xx.h:386
__IO uint32_t DOUTEP1MSK
Definition: stm32f769xx.h:1124
__IO uint32_t CLCR
Definition: stm32f769xx.h:1342
__IO uint32_t CCR3
Definition: stm32f769xx.h:990
__IO uint32_t DINR14
Definition: stm32f769xx.h:1255
__IO uint32_t ARR
Definition: stm32f769xx.h:986
__IO uint32_t CR1
Definition: stm32f769xx.h:757
__IO uint32_t APB2LPENR
Definition: stm32f769xx.h:793
__IO uint32_t BKP15R
Definition: stm32f769xx.h:847
__IO uint32_t M0AR
Definition: stm32f769xx.h:442
__IO uint32_t CFGR
Definition: stm32f769xx.h:1012
__IO uint32_t DINR31
Definition: stm32f769xx.h:1272
__IO uint32_t DR
Definition: stm32f769xx.h:898
__IO uint32_t WCFGR
Definition: stm32f769xx.h:1377
__IO uint32_t VVFPCR
Definition: stm32f769xx.h:1333
Definition: stm32f769xx.h:161
__IO uint32_t DOEPMSK
Definition: stm32f769xx.h:1110
__IO uint32_t SMPR1
Definition: stm32f769xx.h:223
__IO uint32_t MMCRIR
Definition: stm32f769xx.h:518
__IO uint32_t GRXFSIZ
Definition: stm32f769xx.h:1081
__IO uint32_t AR
Definition: stm32f769xx.h:960
__IO uint32_t VHSACR
Definition: stm32f769xx.h:1328
Definition: stm32f769xx.h:185
__IO uint32_t HCCHAR
Definition: stm32f769xx.h:1178
__IO uint32_t PMEM
Definition: stm32f769xx.h:619
Definition: stm32f769xx.h:146
Definition: stm32f769xx.h:73
__IO uint32_t BKP8R
Definition: stm32f769xx.h:840
__IO uint32_t BKP3R
Definition: stm32f769xx.h:835
__IO uint32_t DOUTR7
Definition: stm32f769xx.h:1280
__IO uint32_t HAINT
Definition: stm32f769xx.h:1169
__IO uint32_t TWCR
Definition: stm32f769xx.h:713
__IO uint32_t SQR1
Definition: stm32f769xx.h:231
__IO uint32_t CCR
Definition: stm32f769xx.h:245
__IO uint32_t CFGR
Definition: stm32f769xx.h:772
Definition: stm32f769xx.h:71
USB_OTG_device_Registers.
Definition: stm32f769xx.h:1103
__IO uint32_t DOR
Definition: stm32f769xx.h:1209
__IO uint32_t DMACHTDR
Definition: stm32f769xx.h:556
Definition: stm32f769xx.h:129
__IO uint32_t IER
Definition: stm32f769xx.h:1011
__IO uint32_t VVSACR
Definition: stm32f769xx.h:1331
Definition: stm32f769xx.h:182
__IO uint32_t MEMRMP
Definition: stm32f769xx.h:662
__IO uint32_t MMCTIMR
Definition: stm32f769xx.h:521
__IO uint32_t RESERVED8
Definition: stm32f769xx.h:542
DSI Controller.
Definition: stm32f769xx.h:1311
__IO uint32_t SR
Definition: stm32f769xx.h:883
Definition: stm32f769xx.h:150
__IO uint32_t CCMR2
Definition: stm32f769xx.h:982
__IO uint32_t EMR
Definition: stm32f769xx.h:569
__IO uint32_t PCONFR
Definition: stm32f769xx.h:1346
__IO uint32_t BGOR
Definition: stm32f769xx.h:467
Definition: stm32f769xx.h:99
__IO uint32_t DHR12L2
Definition: stm32f769xx.h:357
__IO uint32_t FCR
Definition: stm32f769xx.h:444
__IO uint32_t BKP26R
Definition: stm32f769xx.h:858
__IO uint32_t CDSR
Definition: stm32f769xx.h:725
__IO uint32_t PTPTSAR
Definition: stm32f769xx.h:539